1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/rcar_i2c.c
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
8 * NOTE: This driver should be converted to driver model before June 2017.
9 * Please see doc/driver-model/i2c-howto.txt for instructions.
16 DECLARE_GLOBAL_DATA_PTR;
35 #define MCR_MDBS 0x80 /* non-fifo mode switch */
36 #define MCR_FSCL 0x40 /* override SCL pin */
37 #define MCR_FSDA 0x20 /* override SDA pin */
38 #define MCR_OBPC 0x10 /* override pins */
39 #define MCR_MIE 0x08 /* master if enable */
41 #define MCR_FSB 0x02 /* force stop bit */
42 #define MCR_ESG 0x01 /* en startbit gen. */
45 #define MSR_MNR 0x40 /* nack received */
46 #define MSR_MAL 0x20 /* arbitration lost */
47 #define MSR_MST 0x10 /* sent a stop */
51 #define MSR_MAT 0x01 /* slave addr xfer done */
53 static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
54 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
55 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
56 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
57 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
60 static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
62 /* set slave address */
63 writel(chip << 1, &dev->icmar);
64 /* set register address */
65 writel(addr, &dev->icrxdtxd);
67 writel(0, &dev->icmsr);
68 /* start master send */
69 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
71 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
72 != (MSR_MAT | MSR_MDE))
76 writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
78 writel(~(MSR_MAT | MSR_MDE), &dev->icmsr);
80 while (!(readl(&dev->icmsr) & MSR_MDE))
84 static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
86 while (!(readl(&dev->icmsr) & MSR_MST))
89 writel(0, &dev->icmcr);
93 rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
95 rcar_i2c_raw_rw_common(dev, chip, addr);
98 writel(*val, &dev->icrxdtxd);
100 writel(~MSR_MDE, &dev->icmsr);
102 while (!(readl(&dev->icmsr) & MSR_MDE))
105 /* set stop condition */
106 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
108 writel(~MSR_MDE, &dev->icmsr);
110 rcar_i2c_raw_rw_finish(dev);
116 rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
120 rcar_i2c_raw_rw_common(dev, chip, addr);
122 /* set slave address, receive */
123 writel((chip << 1) | 1, &dev->icmar);
124 /* start master receive */
125 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
127 writel(0, &dev->icmsr);
129 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR))
130 != (MSR_MAT | MSR_MDR))
134 writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
135 /* prepare stop condition */
136 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
138 writel(~(MSR_MAT | MSR_MDR), &dev->icmsr);
140 while (!(readl(&dev->icmsr) & MSR_MDR))
143 /* get receive data */
144 ret = (u8)readl(&dev->icrxdtxd);
146 writel(~MSR_MDR, &dev->icmsr);
148 rcar_i2c_raw_rw_finish(dev);
154 * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck])
155 * iicck : I2C internal clock < 20 MHz
156 * ticf : I2C SCL falling time: 35 ns
157 * tr : I2C SCL rising time: 200 ns
158 * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5
159 * F[n] : n rounded up to an integer
161 static u32 rcar_clock_gen(int i2c_no, u32 bus_speed)
163 u32 iicck, f, scl, scgd;
166 int bit = 0, cdf_width = 3;
167 for (bit = 0; bit < (1 << cdf_width); bit++) {
168 iicck = CONFIG_HP_CLK_FREQ / (1 + bit);
169 if (iicck < 20000000)
173 if (bit > (1 << cdf_width)) {
174 puts("rcar-i2c: Can not get CDF\n");
181 f = (35 + 200 + intd) * (iicck / 1000000000);
183 for (scgd = 0; scgd < 0x40; scgd++) {
184 scl = iicck / (20 + (scgd * 8) + f);
185 if (scl <= bus_speed)
190 puts("rcar-i2c: Can not get SDGB\n");
194 debug("%s: scl: %d\n", __func__, scl);
195 debug("%s: bit %x\n", __func__, bit);
196 debug("%s: scgd %x\n", __func__, scgd);
197 debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit));
199 return scgd << (cdf_width) | bit;
203 rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
205 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
208 /* No i2c support prior to relocation */
209 if (!(gd->flags & GD_FLG_RELOC))
214 * slave mode is not used on this driver
216 writel(0, &dev->icsier);
217 writel(0, &dev->icsar);
218 writel(0, &dev->icscr);
219 writel(0, &dev->icssr);
221 /* reset master mode */
222 writel(0, &dev->icmier);
223 writel(0, &dev->icmcr);
224 writel(0, &dev->icmsr);
225 writel(0, &dev->icmar);
227 icccr = rcar_clock_gen(adap->hwadapnr, adap->speed);
229 puts("I2C: Init failed\n");
231 writel(icccr, &dev->icccr);
234 static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip,
235 uint addr, int alen, u8 *data, int len)
237 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
240 for (i = 0; i < len; i++)
241 data[i] = rcar_i2c_raw_read(dev, chip, addr + i);
246 static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
247 int alen, u8 *data, int len)
249 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
250 return rcar_i2c_raw_write(dev, chip, addr, data, len);
254 rcar_i2c_probe(struct i2c_adapter *adap, u8 dev)
256 return rcar_i2c_read(adap, dev, 0, 0, NULL, 0);
259 static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap,
262 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
266 rcar_i2c_raw_rw_finish(dev);
268 icccr = rcar_clock_gen(adap->hwadapnr, speed);
270 puts("I2C: Init failed\n");
273 writel(icccr, &dev->icccr);
279 * Register RCAR i2c adapters
281 U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
282 rcar_i2c_write, rcar_i2c_set_bus_speed,
283 CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0)
284 U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
285 rcar_i2c_write, rcar_i2c_set_bus_speed,
286 CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1)
287 U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
288 rcar_i2c_write, rcar_i2c_set_bus_speed,
289 CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2)
290 U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
291 rcar_i2c_write, rcar_i2c_set_bus_speed,
292 CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3)