drivers/i2c/omap24xx_i2c.c

   1 /*
   2  * Basic I2C functions
   3  *
   4  * Copyright (c) 2004 Texas Instruments
   5  *
   6  * This package is free software;  you can redistribute it and/or
   7  * modify it under the terms of the license found in the file
   8  * named COPYING that should have accompanied this file.
   9  *
  10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  13  *
  14  * Author: Jian Zhang jzhang@ti.com, Texas Instruments
  15  *
  16  * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
  17  * Rewritten to fit into the current U-Boot framework
  18  *
  19  * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
  20  *
  21  * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
  22  * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
  23  * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
  24  * OMAPs and derivatives as well. The only anticipated exception would
  25  * be the OMAP2420, which shall require driver modification.
  26  * - Rewritten i2c_read to operate correctly with all types of chips
  27  *   (old function could not read consistent data from some I2C slaves).
  28  * - Optimized i2c_write.
  29  * - New i2c_probe, performs write access vs read. The old probe could
  30  *   hang the system under certain conditions (e.g. unconfigured pads).
  31  * - The read/write/probe functions try to identify unconfigured bus.
  32  * - Status functions now read irqstatus_raw as per TRM guidelines
  33  *   (except for OMAP243X and OMAP34XX).
  34  * - Driver now supports up to I2C5 (OMAP5).
  35  *
  36  * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
  37  * - Added support for set_speed
  38  *
  39  */
  40
  41 #include <common.h>
  42 #include <dm.h>
  43 #include <i2c.h>
  44
  45 #include <asm/io.h>
  46
  47 /*
  48  * Provide access to architecture-specific I2C header files for platforms
  49  * that are NOT yet solely relying on CONFIG_DM_I2C, CONFIG_OF_CONTROL, and
  50  * the defaults provided in 'omap24xx_i2c.h' for all U-Boot stages where I2C
  51  * access is desired.
  52  */
  53 #ifndef CONFIG_ARCH_K3
  54 #include <asm/arch/i2c.h>
  55 #endif
  56
  57 #include "omap24xx_i2c.h"
  58
  59 #define I2C_TIMEOUT     1000
  60
  61 /* Absolutely safe for status update at 100 kHz I2C: */
  62 #define I2C_WAIT        200
  63
  64 enum {
  65         OMAP_I2C_REV_V1 = 0,
  66         OMAP_I2C_REV_V2 = 1,
  67 };
  68
  69 enum {
  70         OMAP_I2C_REV_REG = 0,           /* Only on IP V1 (OMAP34XX) */
  71         OMAP_I2C_IE_REG,                /* Only on IP V1 (OMAP34XX) */
  72         OMAP_I2C_STAT_REG,
  73         OMAP_I2C_WE_REG,
  74         OMAP_I2C_SYSS_REG,
  75         OMAP_I2C_BUF_REG,
  76         OMAP_I2C_CNT_REG,
  77         OMAP_I2C_DATA_REG,
  78         OMAP_I2C_SYSC_REG,
  79         OMAP_I2C_CON_REG,
  80         OMAP_I2C_OA_REG,
  81         OMAP_I2C_SA_REG,
  82         OMAP_I2C_PSC_REG,
  83         OMAP_I2C_SCLL_REG,
  84         OMAP_I2C_SCLH_REG,
  85         OMAP_I2C_SYSTEST_REG,
  86         OMAP_I2C_BUFSTAT_REG,
  87         /* Only on IP V2 (OMAP4430, etc.) */
  88         OMAP_I2C_IP_V2_REVNB_LO,
  89         OMAP_I2C_IP_V2_REVNB_HI,
  90         OMAP_I2C_IP_V2_IRQSTATUS_RAW,
  91         OMAP_I2C_IP_V2_IRQENABLE_SET,
  92         OMAP_I2C_IP_V2_IRQENABLE_CLR,
  93 };
  94
  95 static const u8 __maybe_unused reg_map_ip_v1[] = {
  96         [OMAP_I2C_REV_REG] = 0x00,
  97         [OMAP_I2C_IE_REG] = 0x04,
  98         [OMAP_I2C_STAT_REG] = 0x08,
  99         [OMAP_I2C_WE_REG] = 0x0c,
 100         [OMAP_I2C_SYSS_REG] = 0x10,
 101         [OMAP_I2C_BUF_REG] = 0x14,
 102         [OMAP_I2C_CNT_REG] = 0x18,
 103         [OMAP_I2C_DATA_REG] = 0x1c,
 104         [OMAP_I2C_SYSC_REG] = 0x20,
 105         [OMAP_I2C_CON_REG] = 0x24,
 106         [OMAP_I2C_OA_REG] = 0x28,
 107         [OMAP_I2C_SA_REG] = 0x2c,
 108         [OMAP_I2C_PSC_REG] = 0x30,
 109         [OMAP_I2C_SCLL_REG] = 0x34,
 110         [OMAP_I2C_SCLH_REG] = 0x38,
 111         [OMAP_I2C_SYSTEST_REG] = 0x3c,
 112         [OMAP_I2C_BUFSTAT_REG] = 0x40,
 113 };
 114
 115 static const u8 __maybe_unused reg_map_ip_v2[] = {
 116         [OMAP_I2C_STAT_REG] = 0x28,
 117         [OMAP_I2C_WE_REG] = 0x34,
 118         [OMAP_I2C_SYSS_REG] = 0x90,
 119         [OMAP_I2C_BUF_REG] = 0x94,
 120         [OMAP_I2C_CNT_REG] = 0x98,
 121         [OMAP_I2C_DATA_REG] = 0x9c,
 122         [OMAP_I2C_SYSC_REG] = 0x10,
 123         [OMAP_I2C_CON_REG] = 0xa4,
 124         [OMAP_I2C_OA_REG] = 0xa8,
 125         [OMAP_I2C_SA_REG] = 0xac,
 126         [OMAP_I2C_PSC_REG] = 0xb0,
 127         [OMAP_I2C_SCLL_REG] = 0xb4,
 128         [OMAP_I2C_SCLH_REG] = 0xb8,
 129         [OMAP_I2C_SYSTEST_REG] = 0xbc,
 130         [OMAP_I2C_BUFSTAT_REG] = 0xc0,
 131         [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
 132         [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
 133         [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
 134         [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
 135         [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
 136 };
 137
 138 struct omap_i2c {
 139         struct udevice *clk;
 140         int ip_rev;
 141         struct i2c *regs;
 142         unsigned int speed;
 143         int waitdelay;
 144         int clk_id;
 145 };
 146
 147 static inline const u8 *omap_i2c_get_ip_reg_map(int ip_rev)
 148 {
 149         switch (ip_rev) {
 150         case OMAP_I2C_REV_V1:
 151                 return reg_map_ip_v1;
 152         case OMAP_I2C_REV_V2:
 153                 /* Fall through... */
 154         default:
 155                 return reg_map_ip_v2;
 156         }
 157 }
 158
 159 static inline void omap_i2c_write_reg(void __iomem *base, int ip_rev,
 160                                       u16 val, int reg)
 161 {
 162         writew(val, base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
 163 }
 164
 165 static inline u16 omap_i2c_read_reg(void __iomem *base, int ip_rev, int reg)
 166 {
 167         return readw(base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
 168 }
 169
 170 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 171 {
 172         unsigned long internal_clk = 0, fclk;
 173         unsigned int prescaler;
 174
 175         /*
 176          * This method is only called for Standard and Fast Mode speeds
 177          *
 178          * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
 179          * page 5685, Table 24-7)
 180          * that the internal I2C clock (after prescaler) should be between
 181          * 7-12 MHz (at least for Fast Mode (FS)).
 182          *
 183          * Such approach is used in v4.9 Linux kernel in:
 184          * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
 185          */
 186
 187         speed /= 1000; /* convert speed to kHz */
 188
 189         if (speed > 100)
 190                 internal_clk = 9600;
 191         else
 192                 internal_clk = 4000;
 193
 194         fclk = I2C_IP_CLK / 1000;
 195         prescaler = fclk / internal_clk;
 196         prescaler = prescaler - 1;
 197
 198         if (speed > 100) {
 199                 unsigned long scl;
 200
 201                 /* Fast mode */
 202                 scl = internal_clk / speed;
 203                 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
 204                 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
 205         } else {
 206                 /* Standard mode */
 207                 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
 208                 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
 209         }
 210
 211         debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
 212               __func__, speed, prescaler, *pscl, *psch);
 213
 214         if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
 215                 return -EINVAL;
 216
 217         return prescaler;
 218 }
 219
 220 /*
 221  * Wait for the bus to be free by checking the Bus Busy (BB)
 222  * bit to become clear
 223  */
 224 static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay)
 225 {
 226         int timeout = I2C_TIMEOUT;
 227         int irq_stat_reg;
 228         u16 stat;
 229
 230         irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
 231                        OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
 232
 233         /* clear current interrupts */
 234         omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
 235
 236         while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) &
 237                 I2C_STAT_BB) && timeout--) {
 238                 omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG);
 239                 udelay(waitdelay);
 240         }
 241
 242         if (timeout <= 0) {
 243                 printf("Timed out in %s: status=%04x\n", __func__, stat);
 244                 return 1;
 245         }
 246
 247         /* clear delayed stuff */
 248         omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
 249         return 0;
 250 }
 251
 252 /*
 253  * Wait for the I2C controller to complete current action
 254  * and update status
 255  */
 256 static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay)
 257 {
 258         u16 status;
 259         int timeout = I2C_TIMEOUT;
 260         int irq_stat_reg;
 261
 262         irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
 263                        OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
 264         do {
 265                 udelay(waitdelay);
 266                 status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg);
 267         } while (!(status &
 268                    (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
 269                     I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
 270                     I2C_STAT_AL)) && timeout--);
 271
 272         if (timeout <= 0) {
 273                 printf("Timed out in %s: status=%04x\n", __func__, status);
 274                 /*
 275                  * If status is still 0 here, probably the bus pads have
 276                  * not been configured for I2C, and/or pull-ups are missing.
 277                  */
 278                 printf("Check if pads/pull-ups of bus are properly configured\n");
 279                 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
 280                 status = 0;
 281         }
 282
 283         return status;
 284 }
 285
 286 static void flush_fifo(void __iomem *i2c_base, int ip_rev)
 287 {
 288         u16 stat;
 289
 290         /*
 291          * note: if you try and read data when its not there or ready
 292          * you get a bus error
 293          */
 294         while (1) {
 295                 stat = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_STAT_REG);
 296                 if (stat == I2C_STAT_RRDY) {
 297                         omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_DATA_REG);
 298                         omap_i2c_write_reg(i2c_base, ip_rev,
 299                                            I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
 300                         udelay(1000);
 301                 } else
 302                         break;
 303         }
 304 }
 305
 306 static int __omap24_i2c_setspeed(void __iomem *i2c_base, int ip_rev, uint speed,
 307                                  int *waitdelay)
 308 {
 309         int psc, fsscll = 0, fssclh = 0;
 310         int hsscll = 0, hssclh = 0;
 311         u32 scll = 0, sclh = 0;
 312
 313         if (speed >= OMAP_I2C_HIGH_SPEED) {
 314                 /* High speed */
 315                 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
 316                 psc -= 1;
 317                 if (psc < I2C_PSC_MIN) {
 318                         printf("Error : I2C unsupported prescaler %d\n", psc);
 319                         return -1;
 320                 }
 321
 322                 /* For first phase of HS mode */
 323                 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
 324
 325                 fssclh = fsscll;
 326
 327                 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
 328                 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
 329                 if (((fsscll < 0) || (fssclh < 0)) ||
 330                     ((fsscll > 255) || (fssclh > 255))) {
 331                         puts("Error : I2C initializing first phase clock\n");
 332                         return -1;
 333                 }
 334
 335                 /* For second phase of HS mode */
 336                 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
 337
 338                 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
 339                 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
 340                 if (((fsscll < 0) || (fssclh < 0)) ||
 341                     ((fsscll > 255) || (fssclh > 255))) {
 342                         puts("Error : I2C initializing second phase clock\n");
 343                         return -1;
 344                 }
 345
 346                 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
 347                 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
 348
 349         } else {
 350                 /* Standard and fast speed */
 351                 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
 352                 if (0 > psc) {
 353                         puts("Error : I2C initializing clock\n");
 354                         return -1;
 355                 }
 356         }
 357
 358         /* wait for 20 clkperiods */
 359         *waitdelay = (10000000 / speed) * 2;
 360
 361         omap_i2c_write_reg(i2c_base, ip_rev, 0,  OMAP_I2C_CON_REG);
 362         omap_i2c_write_reg(i2c_base, ip_rev, psc, OMAP_I2C_PSC_REG);
 363         omap_i2c_write_reg(i2c_base, ip_rev, scll, OMAP_I2C_SCLL_REG);
 364         omap_i2c_write_reg(i2c_base, ip_rev, sclh, OMAP_I2C_SCLH_REG);
 365         omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
 366
 367         /* clear all pending status */
 368         omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
 369
 370         return 0;
 371 }
 372
 373 static void omap24_i2c_deblock(void __iomem *i2c_base, int ip_rev)
 374 {
 375         int i;
 376         u16 systest;
 377         u16 orgsystest;
 378
 379         /* set test mode ST_EN = 1 */
 380         orgsystest = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSTEST_REG);
 381         systest = orgsystest;
 382
 383         /* enable testmode */
 384         systest |= I2C_SYSTEST_ST_EN;
 385         omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
 386         systest &= ~I2C_SYSTEST_TMODE_MASK;
 387         systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
 388         omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
 389
 390         /* set SCL, SDA  = 1 */
 391         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
 392         omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
 393         udelay(10);
 394
 395         /* toggle scl 9 clocks */
 396         for (i = 0; i < 9; i++) {
 397                 /* SCL = 0 */
 398                 systest &= ~I2C_SYSTEST_SCL_O;
 399                 omap_i2c_write_reg(i2c_base, ip_rev,
 400                                    systest, OMAP_I2C_SYSTEST_REG);
 401                 udelay(10);
 402                 /* SCL = 1 */
 403                 systest |= I2C_SYSTEST_SCL_O;
 404                 omap_i2c_write_reg(i2c_base, ip_rev,
 405                                    systest, OMAP_I2C_SYSTEST_REG);
 406                 udelay(10);
 407         }
 408
 409         /* send stop */
 410         systest &= ~I2C_SYSTEST_SDA_O;
 411         omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
 412         udelay(10);
 413         systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
 414         omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
 415         udelay(10);
 416
 417         /* restore original mode */
 418         omap_i2c_write_reg(i2c_base, ip_rev, orgsystest, OMAP_I2C_SYSTEST_REG);
 419 }
 420
 421 static void __omap24_i2c_init(void __iomem *i2c_base, int ip_rev, int speed,
 422                               int slaveadd, int *waitdelay)
 423 {
 424         int timeout = I2C_TIMEOUT;
 425         int deblock = 1;
 426
 427 retry:
 428         if (omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_CON_REG) &
 429             I2C_CON_EN) {
 430                 omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG);
 431                 udelay(50000);
 432         }
 433
 434         /* for ES2 after soft reset */
 435         omap_i2c_write_reg(i2c_base, ip_rev, 0x2, OMAP_I2C_SYSC_REG);
 436         udelay(1000);
 437
 438         omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
 439         while (!(omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSS_REG) &
 440                  I2C_SYSS_RDONE) && timeout--) {
 441                 if (timeout <= 0) {
 442                         puts("ERROR: Timeout in soft-reset\n");
 443                         return;
 444                 }
 445                 udelay(1000);
 446         }
 447
 448         if (__omap24_i2c_setspeed(i2c_base, ip_rev, speed, waitdelay)) {
 449                 printf("ERROR: failed to setup I2C bus-speed!\n");
 450                 return;
 451         }
 452
 453         /* own address */
 454         omap_i2c_write_reg(i2c_base, ip_rev, slaveadd, OMAP_I2C_OA_REG);
 455
 456         if (ip_rev == OMAP_I2C_REV_V1) {
 457                 /*
 458                  * Have to enable interrupts for OMAP2/3, these IPs don't have
 459                  * an 'irqstatus_raw' register and we shall have to poll 'stat'
 460                  */
 461                 omap_i2c_write_reg(i2c_base, ip_rev, I2C_IE_XRDY_IE |
 462                                    I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
 463                                    I2C_IE_NACK_IE | I2C_IE_AL_IE,
 464                                    OMAP_I2C_IE_REG);
 465         }
 466
 467         udelay(1000);
 468         flush_fifo(i2c_base, ip_rev);
 469         omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
 470
 471         /* Handle possible failed I2C state */
 472         if (wait_for_bb(i2c_base, ip_rev, *waitdelay))
 473                 if (deblock == 1) {
 474                         omap24_i2c_deblock(i2c_base, ip_rev);
 475                         deblock = 0;
 476                         goto retry;
 477                 }
 478 }
 479
 480 /*
 481  * i2c_probe: Use write access. Allows to identify addresses that are
 482  *            write-only (like the config register of dual-port EEPROMs)
 483  */
 484 static int __omap24_i2c_probe(void __iomem *i2c_base, int ip_rev, int waitdelay,
 485                               uchar chip)
 486 {
 487         u16 status;
 488         int res = 1; /* default = fail */
 489
 490         if (chip == omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_OA_REG))
 491                 return res;
 492
 493         /* Wait until bus is free */
 494         if (wait_for_bb(i2c_base, ip_rev, waitdelay))
 495                 return res;
 496
 497         /* No data transfer, slave addr only */
 498         omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
 499
 500         /* Stop bit needed here */
 501         omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
 502                            I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
 503                            OMAP_I2C_CON_REG);
 504
 505         status = wait_for_event(i2c_base, ip_rev, waitdelay);
 506
 507         if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
 508                 /*
 509                  * With current high-level command implementation, notifying
 510                  * the user shall flood the console with 127 messages. If
 511                  * silent exit is desired upon unconfigured bus, remove the
 512                  * following 'if' section:
 513                  */
 514                 if (status == I2C_STAT_XRDY)
 515                         printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
 516                                status);
 517
 518                 goto pr_exit;
 519         }
 520
 521         /* Check for ACK (!NAK) */
 522         if (!(status & I2C_STAT_NACK)) {
 523                 res = 0;                                /* Device found */
 524                 udelay(waitdelay);/* Required by AM335X in SPL */
 525                 /* Abort transfer (force idle state) */
 526                 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_MST | I2C_CON_TRX,
 527                                    OMAP_I2C_CON_REG);   /* Reset */
 528                 udelay(1000);
 529                 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
 530                                    I2C_CON_TRX | I2C_CON_STP,
 531                                    OMAP_I2C_CON_REG);   /* STP */
 532         }
 533
 534 pr_exit:
 535         flush_fifo(i2c_base, ip_rev);
 536         omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
 537         return res;
 538 }
 539
 540 /*
 541  * i2c_read: Function now uses a single I2C read transaction with bulk transfer
 542  *           of the requested number of bytes (note that the 'i2c md' command
 543  *           limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
 544  *           defined in the board config header, this transaction shall be with
 545  *           Repeated Start (Sr) between the address and data phases; otherwise
 546  *           Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
 547  *           The address (reg offset) may be 0, 1 or 2 bytes long.
 548  *           Function now reads correctly from chips that return more than one
 549  *           byte of data per addressed register (like TI temperature sensors),
 550  *           or that do not need a register address at all (such as some clock
 551  *           distributors).
 552  */
 553 static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay,
 554                              uchar chip, uint addr, int alen, uchar *buffer,
 555                              int len)
 556 {
 557         int i2c_error = 0;
 558         u16 status;
 559
 560         if (alen < 0) {
 561                 puts("I2C read: addr len < 0\n");
 562                 return 1;
 563         }
 564
 565         if (len < 0) {
 566                 puts("I2C read: data len < 0\n");
 567                 return 1;
 568         }
 569
 570         if (buffer == NULL) {
 571                 puts("I2C read: NULL pointer passed\n");
 572                 return 1;
 573         }
 574
 575         if (alen > 2) {
 576                 printf("I2C read: addr len %d not supported\n", alen);
 577                 return 1;
 578         }
 579
 580         if (addr + len > (1 << 16)) {
 581                 puts("I2C read: address out of range\n");
 582                 return 1;
 583         }
 584
 585 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 586         /*
 587          * EEPROM chips that implement "address overflow" are ones
 588          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 589          * address and the extra bits end up in the "chip address"
 590          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 591          * four 256 byte chips.
 592          *
 593          * Note that we consider the length of the address field to
 594          * still be one byte because the extra address bits are
 595          * hidden in the chip address.
 596          */
 597         if (alen > 0)
 598                 chip |= ((addr >> (alen * 8)) &
 599                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 600 #endif
 601
 602         /* Wait until bus not busy */
 603         if (wait_for_bb(i2c_base, ip_rev, waitdelay))
 604                 return 1;
 605
 606         /* Zero, one or two bytes reg address (offset) */
 607         omap_i2c_write_reg(i2c_base, ip_rev, alen, OMAP_I2C_CNT_REG);
 608         /* Set slave address */
 609         omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
 610
 611         if (alen) {
 612                 /* Must write reg offset first */
 613 #ifdef CONFIG_I2C_REPEATED_START
 614                 /* No stop bit, use Repeated Start (Sr) */
 615                 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
 616                                    I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG);
 617 #else
 618                 /* Stop - Start (P-S) */
 619                 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
 620                                    I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX,
 621                                    OMAP_I2C_CON_REG);
 622 #endif
 623                 /* Send register offset */
 624                 while (1) {
 625                         status = wait_for_event(i2c_base, ip_rev, waitdelay);
 626                         /* Try to identify bus that is not padconf'd for I2C */
 627                         if (status == I2C_STAT_XRDY) {
 628                                 i2c_error = 2;
 629                                 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
 630                                        status);
 631                                 goto rd_exit;
 632                         }
 633                         if (status == 0 || (status & I2C_STAT_NACK)) {
 634                                 i2c_error = 1;
 635                                 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
 636                                        status);
 637                                 goto rd_exit;
 638                         }
 639                         if (alen) {
 640                                 if (status & I2C_STAT_XRDY) {
 641                                         u8 addr_byte;
 642                                         alen--;
 643                                         addr_byte = (addr >> (8 * alen)) & 0xff;
 644                                         omap_i2c_write_reg(i2c_base, ip_rev,
 645                                                            addr_byte,
 646                                                            OMAP_I2C_DATA_REG);
 647                                         omap_i2c_write_reg(i2c_base, ip_rev,
 648                                                            I2C_STAT_XRDY,
 649                                                            OMAP_I2C_STAT_REG);
 650                                 }
 651                         }
 652                         if (status & I2C_STAT_ARDY) {
 653                                 omap_i2c_write_reg(i2c_base, ip_rev,
 654                                                    I2C_STAT_ARDY,
 655                                                    OMAP_I2C_STAT_REG);
 656                                 break;
 657                         }
 658                 }
 659         }
 660
 661         /* Set slave address */
 662         omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
 663         /* Read len bytes from slave */
 664         omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG);
 665         /* Need stop bit here */
 666         omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
 667                            I2C_CON_STT | I2C_CON_STP, OMAP_I2C_CON_REG);
 668
 669         /* Receive data */
 670         while (1) {
 671                 status = wait_for_event(i2c_base, ip_rev, waitdelay);
 672                 /*
 673                  * Try to identify bus that is not padconf'd for I2C. This
 674                  * state could be left over from previous transactions if
 675                  * the address phase is skipped due to alen=0.
 676                  */
 677                 if (status == I2C_STAT_XRDY) {
 678                         i2c_error = 2;
 679                         printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
 680                                status);
 681                         goto rd_exit;
 682                 }
 683                 if (status == 0 || (status & I2C_STAT_NACK)) {
 684                         i2c_error = 1;
 685                         goto rd_exit;
 686                 }
 687                 if (status & I2C_STAT_RRDY) {
 688                         *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev,
 689                                                       OMAP_I2C_DATA_REG);
 690                         omap_i2c_write_reg(i2c_base, ip_rev,
 691                                            I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
 692                 }
 693                 if (status & I2C_STAT_ARDY) {
 694                         omap_i2c_write_reg(i2c_base, ip_rev,
 695                                            I2C_STAT_ARDY, OMAP_I2C_STAT_REG);
 696                         break;
 697                 }
 698         }
 699
 700 rd_exit:
 701         flush_fifo(i2c_base, ip_rev);
 702         omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
 703         return i2c_error;
 704 }
 705
 706 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
 707 static int __omap24_i2c_write(void __iomem *i2c_base, int ip_rev, int waitdelay,
 708                               uchar chip, uint addr, int alen, uchar *buffer,
 709                               int len)
 710 {
 711         int i;
 712         u16 status;
 713         int i2c_error = 0;
 714         int timeout = I2C_TIMEOUT;
 715
 716         if (alen < 0) {
 717                 puts("I2C write: addr len < 0\n");
 718                 return 1;
 719         }
 720
 721         if (len < 0) {
 722                 puts("I2C write: data len < 0\n");
 723                 return 1;
 724         }
 725
 726         if (buffer == NULL) {
 727                 puts("I2C write: NULL pointer passed\n");
 728                 return 1;
 729         }
 730
 731         if (alen > 2) {
 732                 printf("I2C write: addr len %d not supported\n", alen);
 733                 return 1;
 734         }
 735
 736         if (addr + len > (1 << 16)) {
 737                 printf("I2C write: address 0x%x + 0x%x out of range\n",
 738                        addr, len);
 739                 return 1;
 740         }
 741
 742 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 743         /*
 744          * EEPROM chips that implement "address overflow" are ones
 745          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 746          * address and the extra bits end up in the "chip address"
 747          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 748          * four 256 byte chips.
 749          *
 750          * Note that we consider the length of the address field to
 751          * still be one byte because the extra address bits are
 752          * hidden in the chip address.
 753          */
 754         if (alen > 0)
 755                 chip |= ((addr >> (alen * 8)) &
 756                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 757 #endif
 758
 759         /* Wait until bus not busy */
 760         if (wait_for_bb(i2c_base, ip_rev, waitdelay))
 761                 return 1;
 762
 763         /* Start address phase - will write regoffset + len bytes data */
 764         omap_i2c_write_reg(i2c_base, ip_rev, alen + len, OMAP_I2C_CNT_REG);
 765         /* Set slave address */
 766         omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
 767         /* Stop bit needed here */
 768         omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
 769                            I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
 770                            OMAP_I2C_CON_REG);
 771
 772         while (alen) {
 773                 /* Must write reg offset (one or two bytes) */
 774                 status = wait_for_event(i2c_base, ip_rev, waitdelay);
 775                 /* Try to identify bus that is not padconf'd for I2C */
 776                 if (status == I2C_STAT_XRDY) {
 777                         i2c_error = 2;
 778                         printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
 779                                status);
 780                         goto wr_exit;
 781                 }
 782                 if (status == 0 || (status & I2C_STAT_NACK)) {
 783                         i2c_error = 1;
 784                         printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
 785                                status);
 786                         goto wr_exit;
 787                 }
 788                 if (status & I2C_STAT_XRDY) {
 789                         alen--;
 790                         omap_i2c_write_reg(i2c_base, ip_rev,
 791                                            (addr >> (8 * alen)) & 0xff,
 792                                            OMAP_I2C_DATA_REG);
 793                         omap_i2c_write_reg(i2c_base, ip_rev,
 794                                            I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
 795                 } else {
 796                         i2c_error = 1;
 797                         printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
 798                                status);
 799                         goto wr_exit;
 800                 }
 801         }
 802
 803         /* Address phase is over, now write data */
 804         for (i = 0; i < len; i++) {
 805                 status = wait_for_event(i2c_base, ip_rev, waitdelay);
 806                 if (status == 0 || (status & I2C_STAT_NACK)) {
 807                         i2c_error = 1;
 808                         printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
 809                                status);
 810                         goto wr_exit;
 811                 }
 812                 if (status & I2C_STAT_XRDY) {
 813                         omap_i2c_write_reg(i2c_base, ip_rev,
 814                                            buffer[i], OMAP_I2C_DATA_REG);
 815                         omap_i2c_write_reg(i2c_base, ip_rev,
 816                                            I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
 817                 } else {
 818                         i2c_error = 1;
 819                         printf("i2c_write: bus not ready for data Tx (i=%d)\n",
 820                                i);
 821                         goto wr_exit;
 822                 }
 823         }
 824
 825         /*
 826          * poll ARDY bit for making sure that last byte really has been
 827          * transferred on the bus.
 828          */
 829         do {
 830                 status = wait_for_event(i2c_base, ip_rev, waitdelay);
 831         } while (!(status & I2C_STAT_ARDY) && timeout--);
 832         if (timeout <= 0)
 833                 printf("i2c_write: timed out writig last byte!\n");
 834
 835 wr_exit:
 836         flush_fifo(i2c_base, ip_rev);
 837         omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
 838         return i2c_error;
 839 }
 840
 841 #ifndef CONFIG_DM_I2C
 842 /*
 843  * The legacy I2C functions. These need to get removed once
 844  * all users of this driver are converted to DM.
 845  */
 846 static void __iomem *omap24_get_base(struct i2c_adapter *adap)
 847 {
 848         switch (adap->hwadapnr) {
 849         case 0:
 850                 return (void __iomem *)I2C_BASE1;
 851                 break;
 852         case 1:
 853                 return (void __iomem *)I2C_BASE2;
 854                 break;
 855 #if (CONFIG_SYS_I2C_BUS_MAX > 2)
 856         case 2:
 857                 return (void __iomem *)I2C_BASE3;
 858                 break;
 859 #if (CONFIG_SYS_I2C_BUS_MAX > 3)
 860         case 3:
 861                 return (void __iomem *)I2C_BASE4;
 862                 break;
 863 #if (CONFIG_SYS_I2C_BUS_MAX > 4)
 864         case 4:
 865                 return (void __iomem *)I2C_BASE5;
 866                 break;
 867 #endif
 868 #endif
 869 #endif
 870         default:
 871                 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
 872                 break;
 873         }
 874
 875         return NULL;
 876 }
 877
 878 static int omap24_get_ip_rev(void)
 879 {
 880 #ifdef CONFIG_OMAP34XX
 881         return OMAP_I2C_REV_V1;
 882 #else
 883         return OMAP_I2C_REV_V2;
 884 #endif
 885 }
 886
 887 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 888                            int alen, uchar *buffer, int len)
 889 {
 890         void __iomem *i2c_base = omap24_get_base(adap);
 891         int ip_rev = omap24_get_ip_rev();
 892
 893         return __omap24_i2c_read(i2c_base, ip_rev, adap->waitdelay, chip, addr,
 894                                  alen, buffer, len);
 895 }
 896
 897 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 898                             int alen, uchar *buffer, int len)
 899 {
 900         void __iomem *i2c_base = omap24_get_base(adap);
 901         int ip_rev = omap24_get_ip_rev();
 902
 903         return __omap24_i2c_write(i2c_base, ip_rev, adap->waitdelay, chip, addr,
 904                                   alen, buffer, len);
 905 }
 906
 907 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
 908 {
 909         void __iomem *i2c_base = omap24_get_base(adap);
 910         int ip_rev = omap24_get_ip_rev();
 911         int ret;
 912
 913         ret = __omap24_i2c_setspeed(i2c_base, ip_rev, speed, &adap->waitdelay);
 914         if (ret) {
 915                 pr_err("%s: set i2c speed failed\n", __func__);
 916                 return ret;
 917         }
 918
 919         adap->speed = speed;
 920
 921         return 0;
 922 }
 923
 924 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 925 {
 926         void __iomem *i2c_base = omap24_get_base(adap);
 927         int ip_rev = omap24_get_ip_rev();
 928
 929         return __omap24_i2c_init(i2c_base, ip_rev, speed, slaveadd,
 930                                  &adap->waitdelay);
 931 }
 932
 933 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 934 {
 935         void __iomem *i2c_base = omap24_get_base(adap);
 936         int ip_rev = omap24_get_ip_rev();
 937
 938         return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip);
 939 }
 940
 941 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
 942 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
 943 #endif
 944 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
 945 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
 946 #endif
 947
 948 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
 949                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
 950                          CONFIG_SYS_OMAP24_I2C_SPEED,
 951                          CONFIG_SYS_OMAP24_I2C_SLAVE,
 952                          0)
 953 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
 954                          omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
 955                          CONFIG_SYS_OMAP24_I2C_SPEED1,
 956                          CONFIG_SYS_OMAP24_I2C_SLAVE1,
 957                          1)
 958
 959 #if (CONFIG_SYS_I2C_BUS_MAX > 2)
 960 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
 961 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
 962 #endif
 963 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
 964 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
 965 #endif
 966
 967 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
 968                          omap24_i2c_read, omap24_i2c_write, NULL,
 969                          CONFIG_SYS_OMAP24_I2C_SPEED2,
 970                          CONFIG_SYS_OMAP24_I2C_SLAVE2,
 971                          2)
 972 #if (CONFIG_SYS_I2C_BUS_MAX > 3)
 973 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
 974 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
 975 #endif
 976 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
 977 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
 978 #endif
 979
 980 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
 981                          omap24_i2c_read, omap24_i2c_write, NULL,
 982                          CONFIG_SYS_OMAP24_I2C_SPEED3,
 983                          CONFIG_SYS_OMAP24_I2C_SLAVE3,
 984                          3)
 985 #if (CONFIG_SYS_I2C_BUS_MAX > 4)
 986 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
 987 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
 988 #endif
 989 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
 990 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
 991 #endif
 992
 993 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
 994                          omap24_i2c_read, omap24_i2c_write, NULL,
 995                          CONFIG_SYS_OMAP24_I2C_SPEED4,
 996                          CONFIG_SYS_OMAP24_I2C_SLAVE4,
 997                          4)
 998 #endif
 999 #endif
1000 #endif
1001
1002 #else /* CONFIG_DM_I2C */
1003
1004 static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
1005 {
1006         struct omap_i2c *priv = dev_get_priv(bus);
1007         int ret;
1008
1009         debug("i2c_xfer: %d messages\n", nmsgs);
1010         for (; nmsgs > 0; nmsgs--, msg++) {
1011                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
1012                 if (msg->flags & I2C_M_RD) {
1013                         ret = __omap24_i2c_read(priv->regs, priv->ip_rev,
1014                                                 priv->waitdelay,
1015                                                 msg->addr, 0, 0, msg->buf,
1016                                                 msg->len);
1017                 } else {
1018                         ret = __omap24_i2c_write(priv->regs, priv->ip_rev,
1019                                                  priv->waitdelay,
1020                                                  msg->addr, 0, 0, msg->buf,
1021                                                  msg->len);
1022                 }
1023                 if (ret) {
1024                         debug("i2c_write: error sending\n");
1025                         return -EREMOTEIO;
1026                 }
1027         }
1028
1029         return 0;
1030 }
1031
1032 static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
1033 {
1034         struct omap_i2c *priv = dev_get_priv(bus);
1035
1036         priv->speed = speed;
1037
1038         return __omap24_i2c_setspeed(priv->regs, priv->ip_rev, speed,
1039                                      &priv->waitdelay);
1040 }
1041
1042 static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
1043                                      uint chip_flags)
1044 {
1045         struct omap_i2c *priv = dev_get_priv(bus);
1046
1047         return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay,
1048                                   chip_addr);
1049 }
1050
1051 static int omap_i2c_probe(struct udevice *bus)
1052 {
1053         struct omap_i2c *priv = dev_get_priv(bus);
1054
1055         priv->ip_rev = dev_get_driver_data(bus);
1056
1057         __omap24_i2c_init(priv->regs, priv->ip_rev, priv->speed, 0,
1058                           &priv->waitdelay);
1059
1060         return 0;
1061 }
1062
1063 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1064 static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
1065 {
1066         struct omap_i2c *priv = dev_get_priv(bus);
1067
1068         priv->regs = map_physmem(devfdt_get_addr(bus), sizeof(void *),
1069                                  MAP_NOCACHE);
1070         priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
1071
1072         return 0;
1073 }
1074
1075 static const struct udevice_id omap_i2c_ids[] = {
1076         { .compatible = "ti,omap3-i2c", .data = OMAP_I2C_REV_V1 },
1077         { .compatible = "ti,omap4-i2c", .data = OMAP_I2C_REV_V2 },
1078         { }
1079 };
1080 #endif
1081
1082 static const struct dm_i2c_ops omap_i2c_ops = {
1083         .xfer           = omap_i2c_xfer,
1084         .probe_chip     = omap_i2c_probe_chip,
1085         .set_bus_speed  = omap_i2c_set_bus_speed,
1086 };
1087
1088 U_BOOT_DRIVER(i2c_omap) = {
1089         .name   = "i2c_omap",
1090         .id     = UCLASS_I2C,
1091 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1092         .of_match = omap_i2c_ids,
1093         .ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
1094 #endif
1095         .probe  = omap_i2c_probe,
1096         .priv_auto_alloc_size = sizeof(struct omap_i2c),
1097         .ops    = &omap_i2c_ops,
1098 #if !CONFIG_IS_ENABLED(OF_CONTROL)
1099         .flags  = DM_FLAG_PRE_RELOC,
1100 #endif
1101 };
1102
1103 #endif /* CONFIG_DM_I2C */