2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/errno.h>
59 #define I2CR_IIEN (1 << 6)
60 #define I2CR_MSTA (1 << 5)
61 #define I2CR_MTX (1 << 4)
62 #define I2CR_TX_NO_AK (1 << 3)
63 #define I2CR_RSTA (1 << 2)
65 #define I2SR_ICF (1 << 7)
66 #define I2SR_IBB (1 << 5)
67 #define I2SR_IAL (1 << 4)
68 #define I2SR_IIF (1 << 1)
69 #define I2SR_RX_NO_AK (1 << 0)
72 #define I2CR_IEN (0 << 7)
73 #define I2CR_IDIS (1 << 7)
74 #define I2SR_IIF_CLEAR (1 << 1)
76 #define I2CR_IEN (1 << 7)
77 #define I2CR_IDIS (0 << 7)
78 #define I2SR_IIF_CLEAR (0 << 1)
81 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
82 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
86 static u16 i2c_clk_div[60][2] = {
87 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
88 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
89 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
90 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
91 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
92 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
93 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
94 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
95 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
96 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
97 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
98 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
99 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
100 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
101 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
104 static u16 i2c_clk_div[50][2] = {
105 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
106 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
107 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
108 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
109 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
110 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
111 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
112 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
113 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
114 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
115 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
116 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
117 { 3072, 0x1E }, { 3840, 0x1F }
122 * Calculate and set proper clock divider
124 static uint8_t i2c_imx_get_clk(unsigned int rate)
126 unsigned int i2c_clk_rate;
130 #if defined(CONFIG_MX31)
131 struct clock_control_regs *sc_regs =
132 (struct clock_control_regs *)CCM_BASE;
134 /* start the required I2C clock */
135 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
139 /* Divider value calculation */
140 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
141 div = (i2c_clk_rate + rate - 1) / rate;
142 if (div < i2c_clk_div[0][0])
144 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
145 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
147 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
150 /* Store divider value */
157 static int bus_i2c_set_bus_speed(void *base, int speed)
159 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
160 u8 clk_idx = i2c_imx_get_clk(speed);
161 u8 idx = i2c_clk_div[clk_idx][1];
163 /* Store divider value */
164 writeb(idx, &i2c_regs->ifdr);
167 writeb(I2CR_IDIS, &i2c_regs->i2cr);
168 writeb(0, &i2c_regs->i2sr);
175 static unsigned int bus_i2c_get_bus_speed(void *base)
177 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
178 u8 clk_idx = readb(&i2c_regs->ifdr);
181 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
184 return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
187 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
188 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
189 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
191 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
195 ulong start_time = get_timer(0);
197 sr = readb(&i2c_regs->i2sr);
200 writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
202 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
204 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
205 __func__, sr, readb(&i2c_regs->i2cr), state);
208 if ((sr & (state >> 8)) == (unsigned char)state)
211 elapsed = get_timer(start_time);
212 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
215 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
216 sr, readb(&i2c_regs->i2cr), state);
220 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
224 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
225 writeb(byte, &i2c_regs->i2dr);
226 ret = wait_for_sr_state(i2c_regs, ST_IIF);
229 if (ret & I2SR_RX_NO_AK)
235 * Stop I2C transaction
237 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
240 unsigned int temp = readb(&i2c_regs->i2cr);
242 temp &= ~(I2CR_MSTA | I2CR_MTX);
243 writeb(temp, &i2c_regs->i2cr);
244 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
246 printf("%s:trigger stop failed\n", __func__);
250 * Send start signal, chip address and
251 * write register address
253 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
254 uchar chip, uint addr, int alen)
259 /* Enable I2C controller */
261 if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
263 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
265 writeb(I2CR_IEN, &i2c_regs->i2cr);
266 /* Wait for controller to be stable */
269 if (readb(&i2c_regs->iadr) == (chip << 1))
270 writeb((chip << 1) ^ 2, &i2c_regs->iadr);
271 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
272 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
276 /* Start I2C transaction */
277 temp = readb(&i2c_regs->i2cr);
279 writeb(temp, &i2c_regs->i2cr);
281 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
285 temp |= I2CR_MTX | I2CR_TX_NO_AK;
286 writeb(temp, &i2c_regs->i2cr);
288 /* write slave address */
289 ret = tx_byte(i2c_regs, chip << 1);
294 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
301 static int i2c_idle_bus(void *base);
303 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
304 uchar chip, uint addr, int alen)
308 for (retry = 0; retry < 3; retry++) {
309 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
312 i2c_imx_stop(i2c_regs);
316 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
318 if (ret != -ERESTART)
319 /* Disable controller */
320 writeb(I2CR_IDIS, &i2c_regs->i2cr);
322 if (i2c_idle_bus(i2c_regs) < 0)
325 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
330 * Read data from I2C device
332 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
338 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
340 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
344 temp = readb(&i2c_regs->i2cr);
346 writeb(temp, &i2c_regs->i2cr);
348 ret = tx_byte(i2c_regs, (chip << 1) | 1);
350 i2c_imx_stop(i2c_regs);
354 /* setup bus to read data */
355 temp = readb(&i2c_regs->i2cr);
356 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
358 temp |= I2CR_TX_NO_AK;
359 writeb(temp, &i2c_regs->i2cr);
360 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
361 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
364 for (i = 0; i < len; i++) {
365 ret = wait_for_sr_state(i2c_regs, ST_IIF);
367 i2c_imx_stop(i2c_regs);
372 * It must generate STOP before read I2DR to prevent
373 * controller from generating another clock cycle
375 if (i == (len - 1)) {
376 i2c_imx_stop(i2c_regs);
377 } else if (i == (len - 2)) {
378 temp = readb(&i2c_regs->i2cr);
379 temp |= I2CR_TX_NO_AK;
380 writeb(temp, &i2c_regs->i2cr);
382 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
383 buf[i] = readb(&i2c_regs->i2dr);
385 i2c_imx_stop(i2c_regs);
390 * Write data to I2C device
392 int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
393 const uchar *buf, int len)
397 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
399 ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
403 for (i = 0; i < len; i++) {
404 ret = tx_byte(i2c_regs, buf[i]);
408 i2c_imx_stop(i2c_regs);
415 int (*idle_bus_fn)(void *p);
419 unsigned curr_i2c_bus;
420 struct i2c_parms i2c_data[3];
424 * For SPL boot some boards need i2c before SDRAM is initialized so force
425 * variables to live in SRAM
427 static struct sram_data __attribute__((section(".data"))) srdata;
431 #ifdef CONFIG_SYS_I2C_BASE
432 #ifdef CONFIG_I2C_MULTI_BUS
433 void *ret = srdata.i2c_data[srdata.curr_i2c_bus].base;
437 return (void *)CONFIG_SYS_I2C_BASE;
438 #elif defined(CONFIG_I2C_MULTI_BUS)
439 return srdata.i2c_data[srdata.curr_i2c_bus].base;
441 return srdata.i2c_data[0].base;
445 static struct i2c_parms *i2c_get_parms(void *base)
448 struct i2c_parms *p = srdata.i2c_data;
449 while (i < ARRAY_SIZE(srdata.i2c_data)) {
455 printf("Invalid I2C base: %p\n", base);
459 static int i2c_idle_bus(void *base)
461 struct i2c_parms *p = i2c_get_parms(base);
462 if (p && p->idle_bus_fn)
463 return p->idle_bus_fn(p->idle_bus_data);
467 #ifdef CONFIG_I2C_MULTI_BUS
468 unsigned int i2c_get_bus_num(void)
470 return srdata.curr_i2c_bus;
473 int i2c_set_bus_num(unsigned bus_idx)
475 if (bus_idx >= ARRAY_SIZE(srdata.i2c_data))
477 if (!srdata.i2c_data[bus_idx].base)
479 srdata.curr_i2c_bus = bus_idx;
484 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
486 return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
489 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
491 return bus_i2c_write(get_base(), chip, addr, alen, buf, len);
495 * Test if a chip at a given address responds (probe the chip)
497 int i2c_probe(uchar chip)
499 return bus_i2c_write(get_base(), chip, 0, 0, NULL, 0);
502 void bus_i2c_init(void *base, int speed, int unused,
503 int (*idle_bus_fn)(void *p), void *idle_bus_data)
506 struct i2c_parms *p = srdata.i2c_data;
510 if (!p->base || (p->base == base)) {
513 p->idle_bus_fn = idle_bus_fn;
514 p->idle_bus_data = idle_bus_data;
520 if (i >= ARRAY_SIZE(srdata.i2c_data))
523 bus_i2c_set_bus_speed(base, speed);
529 void i2c_init(int speed, int unused)
531 bus_i2c_init(get_base(), speed, unused, NULL, NULL);
537 int i2c_set_bus_speed(unsigned int speed)
539 return bus_i2c_set_bus_speed(get_base(), speed);
545 unsigned int i2c_get_bus_speed(void)
547 return bus_i2c_get_bus_speed(get_base());