1 // SPDX-License-Identifier: GPL-2.0+
3 * i2c driver for Freescale i.MX series
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
8 * Based on i2c-imx.c from linux kernel:
9 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
10 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
11 * Copyright (C) 2007 RightHand Technologies, Inc.
12 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
19 #include <dm/device_compat.h>
20 #include <linux/errno.h>
21 #include <asm/mach-imx/mxc_i2c.h>
26 #include <dm/pinctrl.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define I2C_QUIRK_FLAG (1 << 0)
33 #define IMX_I2C_REGSHIFT 2
34 #define VF610_I2C_REGSHIFT 0
36 #define I2C_EARLY_INIT_INDEX 0
37 #ifdef CONFIG_SYS_I2C_IFDR_DIV
38 #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
40 #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
50 #define I2CR_IIEN (1 << 6)
51 #define I2CR_MSTA (1 << 5)
52 #define I2CR_MTX (1 << 4)
53 #define I2CR_TX_NO_AK (1 << 3)
54 #define I2CR_RSTA (1 << 2)
56 #define I2SR_ICF (1 << 7)
57 #define I2SR_IBB (1 << 5)
58 #define I2SR_IAL (1 << 4)
59 #define I2SR_IIF (1 << 1)
60 #define I2SR_RX_NO_AK (1 << 0)
63 #define I2CR_IEN (0 << 7)
64 #define I2CR_IDIS (1 << 7)
65 #define I2SR_IIF_CLEAR (1 << 1)
67 #define I2CR_IEN (1 << 7)
68 #define I2CR_IDIS (0 << 7)
69 #define I2SR_IIF_CLEAR (0 << 1)
73 static u16 i2c_clk_div[60][2] = {
74 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
75 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
76 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
77 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
78 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
79 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
80 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
81 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
82 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
83 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
84 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
85 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
86 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
87 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
88 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
91 static u16 i2c_clk_div[50][2] = {
92 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
93 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
94 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
95 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
96 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
97 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
98 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
99 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
100 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
101 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
102 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
103 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
104 { 3072, 0x1E }, { 3840, 0x1F }
108 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
109 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
111 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
112 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
114 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
115 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
117 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
118 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
121 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
122 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
124 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
125 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
127 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
128 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
130 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
131 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
135 * Calculate and set proper clock divider
137 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
139 unsigned int i2c_clk_rate;
143 #if defined(CONFIG_MX31)
144 struct clock_control_regs *sc_regs =
145 (struct clock_control_regs *)CCM_BASE;
147 /* start the required I2C clock */
148 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
152 /* Divider value calculation */
153 #if CONFIG_IS_ENABLED(CLK)
154 i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
156 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
159 div = (i2c_clk_rate + rate - 1) / rate;
160 if (div < i2c_clk_div[0][0])
162 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
163 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
165 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
168 /* Store divider value */
175 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
177 ulong base = i2c_bus->base;
178 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
179 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
180 u8 idx = i2c_clk_div[clk_idx][1];
181 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
186 /* Store divider value */
187 writeb(idx, base + (IFDR << reg_shift));
190 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
191 writeb(0, base + (I2SR << reg_shift));
195 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
196 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
197 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
199 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
203 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
204 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
205 ulong base = i2c_bus->base;
206 ulong start_time = get_timer(0);
208 sr = readb(base + (I2SR << reg_shift));
211 writeb(sr | I2SR_IAL, base +
212 (I2SR << reg_shift));
214 writeb(sr & ~I2SR_IAL, base +
215 (I2SR << reg_shift));
216 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
217 __func__, sr, readb(base + (I2CR << reg_shift)),
221 if ((sr & (state >> 8)) == (unsigned char)state)
224 elapsed = get_timer(start_time);
225 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
228 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
229 sr, readb(base + (I2CR << reg_shift)), state);
233 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
236 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
237 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
238 ulong base = i2c_bus->base;
240 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
241 writeb(byte, base + (I2DR << reg_shift));
243 ret = wait_for_sr_state(i2c_bus, ST_IIF);
246 if (ret & I2SR_RX_NO_AK)
252 * Stub implementations for outer i2c slave operations.
254 void __i2c_force_reset_slave(void)
257 void i2c_force_reset_slave(void)
258 __attribute__((weak, alias("__i2c_force_reset_slave")));
261 * Stop I2C transaction
263 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
266 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
267 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
268 ulong base = i2c_bus->base;
269 unsigned int temp = readb(base + (I2CR << reg_shift));
271 temp &= ~(I2CR_MSTA | I2CR_MTX);
272 writeb(temp, base + (I2CR << reg_shift));
273 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
275 printf("%s:trigger stop failed\n", __func__);
279 * Send start signal, chip address and
280 * write register address
282 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
287 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
288 ulong base = i2c_bus->base;
289 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
291 /* Reset i2c slave */
292 i2c_force_reset_slave();
294 /* Enable I2C controller */
296 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
298 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
301 writeb(I2CR_IEN, base + (I2CR << reg_shift));
302 /* Wait for controller to be stable */
306 if (readb(base + (IADR << reg_shift)) == (chip << 1))
307 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
308 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
309 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
313 /* Start I2C transaction */
314 temp = readb(base + (I2CR << reg_shift));
316 writeb(temp, base + (I2CR << reg_shift));
318 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
322 temp |= I2CR_MTX | I2CR_TX_NO_AK;
323 writeb(temp, base + (I2CR << reg_shift));
326 /* write slave address */
327 ret = tx_byte(i2c_bus, chip << 1);
332 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
341 #ifndef CONFIG_DM_I2C
342 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
344 if (i2c_bus && i2c_bus->idle_bus_fn)
345 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
350 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
352 * scl-gpios: specify the gpio related to SCL pin
353 * sda-gpios: specify the gpio related to SDA pin
354 * add pinctrl to configure i2c pins to gpio function for i2c
355 * bus recovery, call it "gpio" state
358 * The i2c_idle_bus is an implementation following Linux Kernel.
360 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
362 struct udevice *bus = i2c_bus->bus;
363 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
364 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
365 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
366 int sda, scl, idle_sclks;
368 ulong elapsed, start_time;
370 if (pinctrl_select_state(bus, "gpio")) {
371 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
373 * GPIO pinctrl for i2c force idle is not a must,
374 * but it is strongly recommended to be used.
375 * Because it can help you to recover from bad
376 * i2c bus state. Do not return failure, because
382 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
383 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
384 scl = dm_gpio_get_value(scl_gpio);
385 sda = dm_gpio_get_value(sda_gpio);
387 if ((sda & scl) == 1)
388 goto exit; /* Bus is idle already */
391 * In most cases it is just enough to generate 8 + 1 SCLK
392 * clocks to recover I2C slave device from 'stuck' state
393 * (when for example SW reset was performed, in the middle of
396 * However, there are devices which send data in packets of
397 * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
402 if (i2c->max_transaction_bytes > 0)
403 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
404 /* Send high and low on the SCL line */
405 for (i = 0; i < idle_sclks; i++) {
406 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
407 dm_gpio_set_value(scl_gpio, 0);
409 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
412 start_time = get_timer(0);
414 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
415 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
416 scl = dm_gpio_get_value(scl_gpio);
417 sda = dm_gpio_get_value(sda_gpio);
418 if ((sda & scl) == 1)
421 elapsed = get_timer(start_time);
422 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
424 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
430 pinctrl_select_state(bus, "default");
435 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
440 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
441 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
446 for (retry = 0; retry < 3; retry++) {
447 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
450 i2c_imx_stop(i2c_bus);
451 if (ret == -EREMOTEIO)
454 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
456 if (ret != -ERESTART)
457 /* Disable controller */
458 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
460 if (i2c_idle_bus(i2c_bus) < 0)
463 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
468 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
473 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
474 debug("write_data: ");
475 /* use rc for counter */
476 for (i = 0; i < len; ++i)
477 debug(" 0x%02x", buf[i]);
480 for (i = 0; i < len; i++) {
481 ret = tx_byte(i2c_bus, buf[i]);
483 debug("i2c_write_data(): rc=%d\n", ret);
491 /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
492 * final message of a transaction. If not, it switches the bus back to TX mode
493 * and does not send a STOP, leaving the bus in a state where a repeated start
494 * and address can be sent for another message.
496 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
502 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
503 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
504 ulong base = i2c_bus->base;
506 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
508 /* setup bus to read data */
509 temp = readb(base + (I2CR << reg_shift));
510 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
512 temp |= I2CR_TX_NO_AK;
513 writeb(temp, base + (I2CR << reg_shift));
514 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
515 /* dummy read to clear ICF */
516 readb(base + (I2DR << reg_shift));
519 for (i = 0; i < len; i++) {
520 ret = wait_for_sr_state(i2c_bus, ST_IIF);
522 debug("i2c_read_data(): ret=%d\n", ret);
523 i2c_imx_stop(i2c_bus);
527 if (i == (len - 1)) {
528 /* Final byte has already been received by master! When
529 * we read it from I2DR, the master will start another
530 * cycle. We must program it first to send a STOP or
531 * switch to TX to avoid this.
534 i2c_imx_stop(i2c_bus);
536 /* Final read, no stop, switch back to tx */
537 temp = readb(base + (I2CR << reg_shift));
538 temp |= I2CR_MTX | I2CR_TX_NO_AK;
539 writeb(temp, base + (I2CR << reg_shift));
541 } else if (i == (len - 2)) {
542 /* Master has already recevied penultimate byte. When
543 * we read it from I2DR, master will start RX of final
544 * byte. We must set TX_NO_AK now so it does not ACK
547 temp = readb(base + (I2CR << reg_shift));
548 temp |= I2CR_TX_NO_AK;
549 writeb(temp, base + (I2CR << reg_shift));
552 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
553 buf[i] = readb(base + (I2DR << reg_shift));
556 /* reuse ret for counter*/
557 for (ret = 0; ret < len; ++ret)
558 debug(" 0x%02x", buf[ret]);
561 /* It is not clear to me that this is necessary */
563 i2c_imx_stop(i2c_bus);
567 int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
572 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
573 __attribute__((weak, alias("__enable_i2c_clk")));
575 #ifndef CONFIG_DM_I2C
577 * Read data from I2C device
579 * The transactions use the syntax defined in the Linux kernel I2C docs.
581 * If alen is > 0, then this function will send a transaction of the form:
582 * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
583 * This is a normal I2C register read: writing the register address, then doing
584 * a repeated start and reading the data.
586 * If alen == 0, then we get this transaction:
587 * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
588 * This is somewhat unusual, though valid, transaction. It addresses the chip
589 * in write mode, but doesn't actually write any register address or data, then
590 * does a repeated start and reads data.
592 * If alen < 0, then we get this transaction:
593 * S Chip Rd [A] [data] A ... NA P
594 * The chip is addressed in read mode and then data is read. No register
595 * address is written first. This is perfectly valid on most devices and
596 * required on some (usually those that don't act like an array of registers).
598 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
599 int alen, u8 *buf, int len)
603 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
604 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
605 ulong base = i2c_bus->base;
607 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
612 temp = readb(base + (I2CR << reg_shift));
614 writeb(temp, base + (I2CR << reg_shift));
617 ret = tx_byte(i2c_bus, (chip << 1) | 1);
619 i2c_imx_stop(i2c_bus);
623 ret = i2c_read_data(i2c_bus, chip, buf, len, true);
625 i2c_imx_stop(i2c_bus);
630 * Write data to I2C device
632 * If alen > 0, we get this transaction:
633 * S Chip Wr [A] addr [A] data [A] ... [A] P
634 * An ordinary write register command.
636 * If alen == 0, then we get this:
637 * S Chip Wr [A] data [A] ... [A] P
638 * This is a simple I2C write.
640 * If alen < 0, then we get this:
641 * S data [A] ... [A] P
642 * This is most likely NOT something that should be used. It doesn't send the
643 * chip address first, so in effect, the first byte of data will be used as the
646 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
647 int alen, const u8 *buf, int len)
651 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
655 ret = i2c_write_data(i2c_bus, chip, buf, len);
657 i2c_imx_stop(i2c_bus);
662 #if !defined(I2C2_BASE_ADDR)
663 #define I2C2_BASE_ADDR 0
666 #if !defined(I2C3_BASE_ADDR)
667 #define I2C3_BASE_ADDR 0
670 #if !defined(I2C4_BASE_ADDR)
671 #define I2C4_BASE_ADDR 0
674 #if !defined(I2C5_BASE_ADDR)
675 #define I2C5_BASE_ADDR 0
678 #if !defined(I2C6_BASE_ADDR)
679 #define I2C6_BASE_ADDR 0
682 #if !defined(I2C7_BASE_ADDR)
683 #define I2C7_BASE_ADDR 0
686 #if !defined(I2C8_BASE_ADDR)
687 #define I2C8_BASE_ADDR 0
690 static struct mxc_i2c_bus mxc_i2c_buses[] = {
691 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
692 defined(CONFIG_FSL_LAYERSCAPE)
693 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
694 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
695 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
696 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
697 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
698 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
699 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
700 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
702 { 0, I2C1_BASE_ADDR, 0 },
703 { 1, I2C2_BASE_ADDR, 0 },
704 { 2, I2C3_BASE_ADDR, 0 },
705 { 3, I2C4_BASE_ADDR, 0 },
706 { 4, I2C5_BASE_ADDR, 0 },
707 { 5, I2C6_BASE_ADDR, 0 },
708 { 6, I2C7_BASE_ADDR, 0 },
709 { 7, I2C8_BASE_ADDR, 0 },
713 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
715 return &mxc_i2c_buses[adap->hwadapnr];
718 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
719 uint addr, int alen, uint8_t *buffer,
722 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
725 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
726 uint addr, int alen, uint8_t *buffer,
729 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
733 * Test if a chip at a given address responds (probe the chip)
735 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
737 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
740 void bus_i2c_init(int index, int speed, int unused,
741 int (*idle_bus_fn)(void *p), void *idle_bus_data)
745 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
746 debug("Error i2c index\n");
751 * Warning: Be careful to allow the assignment to a static
752 * variable here. This function could be called while U-Boot is
753 * still running in flash memory. So such assignment is equal
754 * to write data to flash without erasing.
757 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
759 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
761 ret = enable_i2c_clk(1, index);
763 debug("I2C-%d clk fail to enable.\n", index);
767 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
771 * Early init I2C for prepare read the clk through I2C.
773 void i2c_early_init_f(void)
775 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
776 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
777 & I2C_QUIRK_FLAG ? true : false;
778 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
780 /* Set I2C divider value */
781 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
783 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
784 writeb(0, base + (I2SR << reg_shift));
786 writeb(I2CR_IEN, base + (I2CR << reg_shift));
792 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
794 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
800 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
802 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
806 * Register mxc i2c adapters
808 #ifdef CONFIG_SYS_I2C_MXC_I2C1
809 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
810 mxc_i2c_read, mxc_i2c_write,
811 mxc_i2c_set_bus_speed,
812 CONFIG_SYS_MXC_I2C1_SPEED,
813 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
816 #ifdef CONFIG_SYS_I2C_MXC_I2C2
817 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
818 mxc_i2c_read, mxc_i2c_write,
819 mxc_i2c_set_bus_speed,
820 CONFIG_SYS_MXC_I2C2_SPEED,
821 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
824 #ifdef CONFIG_SYS_I2C_MXC_I2C3
825 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
826 mxc_i2c_read, mxc_i2c_write,
827 mxc_i2c_set_bus_speed,
828 CONFIG_SYS_MXC_I2C3_SPEED,
829 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
832 #ifdef CONFIG_SYS_I2C_MXC_I2C4
833 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
834 mxc_i2c_read, mxc_i2c_write,
835 mxc_i2c_set_bus_speed,
836 CONFIG_SYS_MXC_I2C4_SPEED,
837 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
840 #ifdef CONFIG_SYS_I2C_MXC_I2C5
841 U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
842 mxc_i2c_read, mxc_i2c_write,
843 mxc_i2c_set_bus_speed,
844 CONFIG_SYS_MXC_I2C5_SPEED,
845 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
848 #ifdef CONFIG_SYS_I2C_MXC_I2C6
849 U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
850 mxc_i2c_read, mxc_i2c_write,
851 mxc_i2c_set_bus_speed,
852 CONFIG_SYS_MXC_I2C6_SPEED,
853 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
856 #ifdef CONFIG_SYS_I2C_MXC_I2C7
857 U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
858 mxc_i2c_read, mxc_i2c_write,
859 mxc_i2c_set_bus_speed,
860 CONFIG_SYS_MXC_I2C7_SPEED,
861 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
864 #ifdef CONFIG_SYS_I2C_MXC_I2C8
865 U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
866 mxc_i2c_read, mxc_i2c_write,
867 mxc_i2c_set_bus_speed,
868 CONFIG_SYS_MXC_I2C8_SPEED,
869 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
874 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
876 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
878 return bus_i2c_set_bus_speed(i2c_bus, speed);
881 static int mxc_i2c_probe(struct udevice *bus)
883 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
884 const void *fdt = gd->fdt_blob;
885 int node = dev_of_offset(bus);
889 i2c_bus->driver_data = dev_get_driver_data(bus);
891 addr = devfdt_get_addr(bus);
892 if (addr == FDT_ADDR_T_NONE)
895 i2c_bus->base = addr;
896 i2c_bus->index = bus->seq;
900 #if CONFIG_IS_ENABLED(CLK)
901 ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
903 printf("Failed to get i2c clk\n");
906 ret = clk_enable(&i2c_bus->per_clk);
908 printf("Failed to enable i2c clk\n");
912 ret = enable_i2c_clk(1, bus->seq);
918 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
919 * Use gpio to force bus idle when necessary.
921 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
923 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
925 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
926 "scl-gpios", 0, &i2c_bus->scl_gpio,
928 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
929 "sda-gpios", 0, &i2c_bus->sda_gpio,
931 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
932 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
934 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
940 * Pinmux settings are in board file now, until pinmux is supported,
941 * we can set pinmux here in probe function.
944 debug("i2c : controller bus %d at %lu , speed %d: ",
945 bus->seq, i2c_bus->base,
951 /* Sends: S Addr Wr [A|NA] P */
952 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
956 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
958 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
960 debug("%s failed, ret = %d\n", __func__, ret);
964 i2c_imx_stop(i2c_bus);
969 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
971 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
973 ulong base = i2c_bus->base;
974 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
975 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
978 /* Here address len is set to -1 to not send any address at first.
979 * Otherwise i2c_init_transfer will send the chip address with write
980 * mode set. This is wrong if the 1st message is read.
982 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
984 debug("i2c_init_transfer error: %d\n", ret);
988 read_mode = -1; /* So it's always different on the first message */
989 for (; nmsgs > 0; nmsgs--, msg++) {
990 const int msg_is_read = !!(msg->flags & I2C_M_RD);
992 debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
993 msg->len, msg_is_read ? 'R' : 'W');
995 if (msg_is_read != read_mode) {
996 /* Send repeated start if not 1st message */
997 if (read_mode != -1) {
998 debug("i2c_xfer: [RSTART]\n");
999 ret = readb(base + (I2CR << reg_shift));
1001 writeb(ret, base + (I2CR << reg_shift));
1003 debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1004 msg_is_read ? 'R' : 'W');
1005 ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1007 debug("i2c_xfer: [STOP]\n");
1008 i2c_imx_stop(i2c_bus);
1011 read_mode = msg_is_read;
1014 if (msg->flags & I2C_M_RD)
1015 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1016 msg->len, nmsgs == 1 ||
1017 (msg->flags & I2C_M_STOP));
1019 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1027 debug("i2c_write: error sending\n");
1029 i2c_imx_stop(i2c_bus);
1034 static const struct dm_i2c_ops mxc_i2c_ops = {
1035 .xfer = mxc_i2c_xfer,
1036 .probe_chip = mxc_i2c_probe_chip,
1037 .set_bus_speed = mxc_i2c_set_bus_speed,
1040 static const struct udevice_id mxc_i2c_ids[] = {
1041 { .compatible = "fsl,imx21-i2c", },
1042 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1046 U_BOOT_DRIVER(i2c_mxc) = {
1049 .of_match = mxc_i2c_ids,
1050 .probe = mxc_i2c_probe,
1051 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
1052 .ops = &mxc_i2c_ops,
1053 .flags = DM_FLAG_PRE_RELOC,