drivers/i2c/lpc32xx_i2c.c

   1 /*
   2  * LPC32xx I2C interface driver
   3  *
   4  * (C) Copyright 2014-2015  DENX Software Engineering GmbH
   5  * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <i2c.h>
  13 #include <linux/errno.h>
  14 #include <asm/arch/clk.h>
  15 #include <dm.h>
  16 #include <mapmem.h>
  17
  18 /*
  19  * Provide default speed and slave if target did not
  20  */
  21
  22 #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
  23 #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
  24 #endif
  25
  26 #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
  27 #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
  28 #endif
  29
  30 /* i2c register set */
  31 struct lpc32xx_i2c_base {
  32         union {
  33                 u32 rx;
  34                 u32 tx;
  35         };
  36         u32 stat;
  37         u32 ctrl;
  38         u32 clk_hi;
  39         u32 clk_lo;
  40         u32 adr;
  41         u32 rxfl;
  42         u32 txfl;
  43         u32 rxb;
  44         u32 txb;
  45         u32 stx;
  46         u32 stxfl;
  47 };
  48
  49 #ifdef CONFIG_DM_I2C
  50 struct lpc32xx_i2c_dev {
  51         struct lpc32xx_i2c_base *base;
  52         int index;
  53         uint speed;
  54 };
  55 #endif /* CONFIG_DM_I2C */
  56
  57 /* TX register fields */
  58 #define LPC32XX_I2C_TX_START            0x00000100
  59 #define LPC32XX_I2C_TX_STOP             0x00000200
  60
  61 /* Control register values */
  62 #define LPC32XX_I2C_SOFT_RESET          0x00000100
  63
  64 /* Status register values */
  65 #define LPC32XX_I2C_STAT_TFF            0x00000400
  66 #define LPC32XX_I2C_STAT_RFE            0x00000200
  67 #define LPC32XX_I2C_STAT_DRMI           0x00000008
  68 #define LPC32XX_I2C_STAT_NAI            0x00000004
  69 #define LPC32XX_I2C_STAT_TDI            0x00000001
  70
  71 #ifndef CONFIG_DM_I2C
  72 static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
  73         (struct lpc32xx_i2c_base *)I2C1_BASE,
  74         (struct lpc32xx_i2c_base *)I2C2_BASE,
  75         (struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
  76 };
  77 #endif
  78
  79 /* Set I2C bus speed */
  80 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
  81                                         unsigned int speed, unsigned int chip)
  82 {
  83         int half_period;
  84
  85         if (speed == 0)
  86                 return -EINVAL;
  87
  88         /* OTG I2C clock source and CLK registers are different */
  89         if (chip == 2) {
  90                 half_period = (get_periph_clk_rate() / speed) / 2;
  91                 if (half_period > 0xFF)
  92                         return -EINVAL;
  93         } else {
  94                 half_period = (get_hclk_clk_rate() / speed) / 2;
  95                 if (half_period > 0x3FF)
  96                         return -EINVAL;
  97         }
  98
  99         writel(half_period, &base->clk_hi);
 100         writel(half_period, &base->clk_lo);
 101         return 0;
 102 }
 103
 104 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
 105 static void __i2c_init(struct lpc32xx_i2c_base *base,
 106                        int requested_speed, int slaveadd, unsigned int chip)
 107 {
 108         /* soft reset (auto-clears) */
 109         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 110         /* set HI and LO periods for half of the default speed */
 111         __i2c_set_bus_speed(base, requested_speed, chip);
 112 }
 113
 114 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
 115 static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
 116 {
 117         int stat;
 118
 119         /* Soft-reset the controller */
 120         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 121         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 122                 ;
 123         /* Addre slave for write with start before and stop after */
 124         writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
 125                &base->tx);
 126         /* wait for end of transation */
 127         while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 128                 ;
 129         /* was there no acknowledge? */
 130         return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
 131 }
 132
 133 /*
 134  * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 135  * Begin write, send address byte(s), begin read, receive data bytes, end.
 136  */
 137 static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
 138                       int alen, u8 *data, int length)
 139 {
 140         int stat, wlen;
 141
 142         /* Soft-reset the controller */
 143         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 144         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 145                 ;
 146         /* do we need to write an address at all? */
 147         if (alen) {
 148                 /* Address slave in write mode */
 149                 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 150                 /* write address bytes */
 151                 while (alen--) {
 152                         /* compute address byte + stop for the last one */
 153                         int a = (addr >> (8 * alen)) & 0xff;
 154                         if (!alen)
 155                                 a |= LPC32XX_I2C_TX_STOP;
 156                         /* Send address byte */
 157                         writel(a, &base->tx);
 158                 }
 159                 /* wait for end of transation */
 160                 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 161                         ;
 162                 /* clear end-of-transaction flag */
 163                 writel(1, &base->stat);
 164         }
 165         /* do we have to read data at all? */
 166         if (length) {
 167                 /* Address slave in read mode */
 168                 writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 169                 wlen = length;
 170                 /* get data */
 171                 while (length | wlen) {
 172                         /* read status for TFF and RFE */
 173                         stat = readl(&base->stat);
 174                         /* must we, can we write a trigger byte? */
 175                         if ((wlen > 0)
 176                            & (!(stat & LPC32XX_I2C_STAT_TFF))) {
 177                                 wlen--;
 178                                 /* write trigger byte + stop if last */
 179                                 writel(wlen ? 0 :
 180                                 LPC32XX_I2C_TX_STOP, &base->tx);
 181                         }
 182                         /* must we, can we read a data byte? */
 183                         if ((length > 0)
 184                            & (!(stat & LPC32XX_I2C_STAT_RFE))) {
 185                                 length--;
 186                                 /* read byte */
 187                                 *(data++) = readl(&base->rx);
 188                         }
 189                 }
 190                 /* wait for end of transation */
 191                 while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 192                         ;
 193                 /* clear end-of-transaction flag */
 194                 writel(1, &base->stat);
 195         }
 196         /* success */
 197         return 0;
 198 }
 199
 200 /*
 201  * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 202  * Begin write, send address byte(s), send data bytes, end.
 203  */
 204 static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
 205                        int alen, u8 *data, int length)
 206 {
 207         int stat;
 208
 209         /* Soft-reset the controller */
 210         writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
 211         while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
 212                 ;
 213         /* do we need to write anything at all? */
 214         if (alen | length)
 215                 /* Address slave in write mode */
 216                 writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
 217         else
 218                 return 0;
 219         /* write address bytes */
 220         while (alen) {
 221                 /* wait for transmit fifo not full */
 222                 stat = readl(&base->stat);
 223                 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
 224                         alen--;
 225                         int a = (addr >> (8 * alen)) & 0xff;
 226                         if (!(alen | length))
 227                                 a |= LPC32XX_I2C_TX_STOP;
 228                         /* Send address byte */
 229                         writel(a, &base->tx);
 230                 }
 231         }
 232         while (length) {
 233                 /* wait for transmit fifo not full */
 234                 stat = readl(&base->stat);
 235                 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
 236                         /* compute data byte, add stop if length==0 */
 237                         length--;
 238                         int d = *(data++);
 239                         if (!length)
 240                                 d |= LPC32XX_I2C_TX_STOP;
 241                         /* Send data byte */
 242                         writel(d, &base->tx);
 243                 }
 244         }
 245         /* wait for end of transation */
 246         while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
 247                 ;
 248         /* clear end-of-transaction flag */
 249         writel(1, &base->stat);
 250         return 0;
 251 }
 252
 253 #ifndef CONFIG_DM_I2C
 254 static void lpc32xx_i2c_init(struct i2c_adapter *adap,
 255                              int requested_speed, int slaveadd)
 256 {
 257         __i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
 258                    adap->hwadapnr);
 259 }
 260
 261 static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
 262 {
 263         return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
 264 }
 265
 266 static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 267                             int alen, u8 *data, int length)
 268 {
 269         return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
 270                          alen, data, length);
 271 }
 272
 273 static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 274                              int alen, u8 *data, int length)
 275 {
 276         return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
 277                           alen, data, length);
 278 }
 279
 280 static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
 281                                               unsigned int speed)
 282 {
 283         return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
 284                                   adap->hwadapnr);
 285 }
 286
 287 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
 288                          lpc32xx_i2c_read, lpc32xx_i2c_write,
 289                          lpc32xx_i2c_set_bus_speed,
 290                          CONFIG_SYS_I2C_LPC32XX_SPEED,
 291                          CONFIG_SYS_I2C_LPC32XX_SLAVE,
 292                          0)
 293
 294 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
 295                          lpc32xx_i2c_read, lpc32xx_i2c_write,
 296                          lpc32xx_i2c_set_bus_speed,
 297                          CONFIG_SYS_I2C_LPC32XX_SPEED,
 298                          CONFIG_SYS_I2C_LPC32XX_SLAVE,
 299                          1)
 300
 301 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
 302                          lpc32xx_i2c_read, lpc32xx_i2c_write,
 303                          lpc32xx_i2c_set_bus_speed,
 304                          100000,
 305                          0,
 306                          2)
 307 #else /* CONFIG_DM_I2C */
 308 static int lpc32xx_i2c_probe(struct udevice *bus)
 309 {
 310         struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
 311
 312         __i2c_init(dev->base, dev->speed, 0, dev->index);
 313         return 0;
 314 }
 315
 316 static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 317                                   u32 chip_flags)
 318 {
 319         struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
 320         return __i2c_probe_chip(dev->base, chip_addr);
 321 }
 322
 323 static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 324                 int nmsgs)
 325 {
 326         struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
 327         struct i2c_msg *dmsg, *omsg, dummy;
 328         uint i = 0, address = 0;
 329
 330         memset(&dummy, 0, sizeof(struct i2c_msg));
 331
 332         /* We expect either two messages (one with an offset and one with the
 333          * actual data) or one message (just data)
 334          */
 335         if (nmsgs > 2 || nmsgs == 0) {
 336                 debug("%s: Only one or two messages are supported.", __func__);
 337                 return -1;
 338         }
 339
 340         omsg = nmsgs == 1 ? &dummy : msg;
 341         dmsg = nmsgs == 1 ? msg : msg + 1;
 342
 343         /* the address is expected to be a uint, not a array. */
 344         address = omsg->buf[0];
 345         for (i = 1; i < omsg->len; i++)
 346                 address = (address << 8) + omsg->buf[i];
 347
 348         if (dmsg->flags & I2C_M_RD)
 349                 return __i2c_read(dev->base, dmsg->addr, address,
 350                                   omsg->len, dmsg->buf, dmsg->len);
 351         else
 352                 return __i2c_write(dev->base, dmsg->addr, address,
 353                                    omsg->len, dmsg->buf, dmsg->len);
 354 }
 355
 356 static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 357 {
 358         struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
 359         return __i2c_set_bus_speed(dev->base, speed, dev->index);
 360 }
 361
 362 static int lpc32xx_i2c_reset(struct udevice *bus)
 363 {
 364         struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
 365
 366         __i2c_init(dev->base, dev->speed, 0, dev->index);
 367         return 0;
 368 }
 369
 370 static const struct dm_i2c_ops lpc32xx_i2c_ops = {
 371         .xfer          = lpc32xx_i2c_xfer,
 372         .probe_chip    = lpc32xx_i2c_probe_chip,
 373         .deblock       = lpc32xx_i2c_reset,
 374         .set_bus_speed = lpc32xx_i2c_set_bus_speed,
 375 };
 376
 377 U_BOOT_DRIVER(i2c_lpc32xx) = {
 378         .id                   = UCLASS_I2C,
 379         .name                 = "i2c_lpc32xx",
 380         .probe                = lpc32xx_i2c_probe,
 381         .ops                  = &lpc32xx_i2c_ops,
 382 };
 383 #endif /* CONFIG_DM_I2C */