drivers/i2c/kona_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Broadcom Corporation.
   4  *
   5  * NOTE: This driver should be converted to driver model before June 2017.
   6  * Please see doc/driver-model/i2c-howto.rst for instructions.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <linux/errno.h>
  12 #include <asm/arch/sysmap.h>
  13 #include <asm/kona-common/clk.h>
  14 #include <i2c.h>
  15
  16 /* Hardware register offsets and field defintions */
  17 #define CS_OFFSET                               0x00000020
  18 #define CS_ACK_SHIFT                            3
  19 #define CS_ACK_MASK                             0x00000008
  20 #define CS_ACK_CMD_GEN_START                    0x00000000
  21 #define CS_ACK_CMD_GEN_RESTART                  0x00000001
  22 #define CS_CMD_SHIFT                            1
  23 #define CS_CMD_CMD_NO_ACTION                    0x00000000
  24 #define CS_CMD_CMD_START_RESTART                0x00000001
  25 #define CS_CMD_CMD_STOP                         0x00000002
  26 #define CS_EN_SHIFT                             0
  27 #define CS_EN_CMD_ENABLE_BSC                    0x00000001
  28
  29 #define TIM_OFFSET                              0x00000024
  30 #define TIM_PRESCALE_SHIFT                      6
  31 #define TIM_P_SHIFT                             3
  32 #define TIM_NO_DIV_SHIFT                        2
  33 #define TIM_DIV_SHIFT                           0
  34
  35 #define DAT_OFFSET                              0x00000028
  36
  37 #define TOUT_OFFSET                             0x0000002c
  38
  39 #define TXFCR_OFFSET                            0x0000003c
  40 #define TXFCR_FIFO_FLUSH_MASK                   0x00000080
  41 #define TXFCR_FIFO_EN_MASK                      0x00000040
  42
  43 #define IER_OFFSET                              0x00000044
  44 #define IER_READ_COMPLETE_INT_MASK              0x00000010
  45 #define IER_I2C_INT_EN_MASK                     0x00000008
  46 #define IER_FIFO_INT_EN_MASK                    0x00000002
  47 #define IER_NOACK_EN_MASK                       0x00000001
  48
  49 #define ISR_OFFSET                              0x00000048
  50 #define ISR_RESERVED_MASK                       0xffffff60
  51 #define ISR_CMDBUSY_MASK                        0x00000080
  52 #define ISR_READ_COMPLETE_MASK                  0x00000010
  53 #define ISR_SES_DONE_MASK                       0x00000008
  54 #define ISR_ERR_MASK                            0x00000004
  55 #define ISR_TXFIFOEMPTY_MASK                    0x00000002
  56 #define ISR_NOACK_MASK                          0x00000001
  57
  58 #define CLKEN_OFFSET                            0x0000004c
  59 #define CLKEN_AUTOSENSE_OFF_MASK                0x00000080
  60 #define CLKEN_M_SHIFT                           4
  61 #define CLKEN_N_SHIFT                           1
  62 #define CLKEN_CLKEN_MASK                        0x00000001
  63
  64 #define FIFO_STATUS_OFFSET                      0x00000054
  65 #define FIFO_STATUS_RXFIFO_EMPTY_MASK           0x00000004
  66 #define FIFO_STATUS_TXFIFO_EMPTY_MASK           0x00000010
  67
  68 #define HSTIM_OFFSET                            0x00000058
  69 #define HSTIM_HS_MODE_MASK                      0x00008000
  70 #define HSTIM_HS_HOLD_SHIFT                     10
  71 #define HSTIM_HS_HIGH_PHASE_SHIFT               5
  72 #define HSTIM_HS_SETUP_SHIFT                    0
  73
  74 #define PADCTL_OFFSET                           0x0000005c
  75 #define PADCTL_PAD_OUT_EN_MASK                  0x00000004
  76
  77 #define RXFCR_OFFSET                            0x00000068
  78 #define RXFCR_NACK_EN_SHIFT                     7
  79 #define RXFCR_READ_COUNT_SHIFT                  0
  80 #define RXFIFORDOUT_OFFSET                      0x0000006c
  81
  82 /* Locally used constants */
  83 #define MAX_RX_FIFO_SIZE                64U     /* bytes */
  84 #define MAX_TX_FIFO_SIZE                64U     /* bytes */
  85
  86 #define I2C_TIMEOUT                     100000  /* usecs */
  87
  88 #define WAIT_INT_CHK                    100     /* usecs */
  89 #if I2C_TIMEOUT % WAIT_INT_CHK
  90 #error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
  91 #endif
  92
  93 /* Operations that can be commanded to the controller */
  94 enum bcm_kona_cmd_t {
  95         BCM_CMD_NOACTION = 0,
  96         BCM_CMD_START,
  97         BCM_CMD_RESTART,
  98         BCM_CMD_STOP,
  99 };
 100
 101 /* Internal divider settings for standard mode, fast mode and fast mode plus */
 102 struct bus_speed_cfg {
 103         uint8_t time_m;         /* Number of cycles for setup time */
 104         uint8_t time_n;         /* Number of cycles for hold time */
 105         uint8_t prescale;       /* Prescale divider */
 106         uint8_t time_p;         /* Timing coefficient */
 107         uint8_t no_div;         /* Disable clock divider */
 108         uint8_t time_div;       /* Post-prescale divider */
 109 };
 110
 111 static const struct bus_speed_cfg std_cfg_table[] = {
 112         [IC_SPEED_MODE_STANDARD] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
 113         [IC_SPEED_MODE_FAST] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
 114         [IC_SPEED_MODE_FAST_PLUS] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
 115 };
 116
 117 struct bcm_kona_i2c_dev {
 118         void *base;
 119         uint speed;
 120         const struct bus_speed_cfg *std_cfg;
 121 };
 122
 123 /* Keep these two defines in sync */
 124 #define DEF_SPD I2C_SPEED_STANDARD_RATE
 125 #define DEF_SPD_ENUM IC_SPEED_MODE_STANDARD
 126
 127 #define DEF_DEVICE(num) \
 128 {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
 129
 130 static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
 131 #ifdef CONFIG_SYS_I2C_BASE0
 132         DEF_DEVICE(0),
 133 #endif
 134 #ifdef CONFIG_SYS_I2C_BASE1
 135         DEF_DEVICE(1),
 136 #endif
 137 #ifdef CONFIG_SYS_I2C_BASE2
 138         DEF_DEVICE(2),
 139 #endif
 140 #ifdef CONFIG_SYS_I2C_BASE3
 141         DEF_DEVICE(3),
 142 #endif
 143 #ifdef CONFIG_SYS_I2C_BASE4
 144         DEF_DEVICE(4),
 145 #endif
 146 #ifdef CONFIG_SYS_I2C_BASE5
 147         DEF_DEVICE(5),
 148 #endif
 149 };
 150
 151 #define I2C_M_TEN       0x0010  /* ten bit address */
 152 #define I2C_M_RD        0x0001  /* read data */
 153 #define I2C_M_NOSTART   0x4000  /* no restart between msgs */
 154
 155 struct kona_i2c_msg {
 156         uint16_t addr;
 157         uint16_t flags;
 158         uint16_t len;
 159         uint8_t *buf;
 160 };
 161
 162 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
 163                                           enum bcm_kona_cmd_t cmd)
 164 {
 165         debug("%s, %d\n", __func__, cmd);
 166
 167         switch (cmd) {
 168         case BCM_CMD_NOACTION:
 169                 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
 170                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 171                        dev->base + CS_OFFSET);
 172                 break;
 173
 174         case BCM_CMD_START:
 175                 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
 176                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 177                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 178                        dev->base + CS_OFFSET);
 179                 break;
 180
 181         case BCM_CMD_RESTART:
 182                 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
 183                        (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
 184                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 185                        dev->base + CS_OFFSET);
 186                 break;
 187
 188         case BCM_CMD_STOP:
 189                 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
 190                        (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
 191                        dev->base + CS_OFFSET);
 192                 break;
 193
 194         default:
 195                 printf("Unknown command %d\n", cmd);
 196         }
 197 }
 198
 199 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
 200 {
 201         writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
 202                dev->base + CLKEN_OFFSET);
 203 }
 204
 205 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
 206 {
 207         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
 208                dev->base + CLKEN_OFFSET);
 209 }
 210
 211 /* Wait until at least one of the mask bit(s) are set */
 212 static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
 213                                           unsigned long time_left,
 214                                           uint32_t mask)
 215 {
 216         uint32_t status;
 217
 218         while (time_left) {
 219                 status = readl(dev->base + ISR_OFFSET);
 220
 221                 if ((status & ~ISR_RESERVED_MASK) == 0) {
 222                         debug("Bogus I2C interrupt 0x%x\n", status);
 223                         continue;
 224                 }
 225
 226                 /* Must flush the TX FIFO when NAK detected */
 227                 if (status & ISR_NOACK_MASK)
 228                         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 229                                dev->base + TXFCR_OFFSET);
 230
 231                 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
 232
 233                 if (status & mask) {
 234                         /* We are done since one of the mask bits are set */
 235                         return time_left;
 236                 }
 237                 udelay(WAIT_INT_CHK);
 238                 time_left -= WAIT_INT_CHK;
 239         }
 240         return 0;
 241 }
 242
 243 /* Send command to I2C bus */
 244 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
 245                                  enum bcm_kona_cmd_t cmd)
 246 {
 247         int rc = 0;
 248         unsigned long time_left = I2C_TIMEOUT;
 249
 250         /* Send the command */
 251         bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
 252
 253         /* Wait for transaction to finish or timeout */
 254         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 255
 256         if (!time_left) {
 257                 printf("controller timed out\n");
 258                 rc = -ETIMEDOUT;
 259         }
 260
 261         /* Clear command */
 262         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 263
 264         return rc;
 265 }
 266
 267 /* Read a single RX FIFO worth of data from the i2c bus */
 268 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
 269                                          uint8_t *buf, unsigned int len,
 270                                          unsigned int last_byte_nak)
 271 {
 272         unsigned long time_left = I2C_TIMEOUT;
 273
 274         /* Start the RX FIFO */
 275         writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
 276                (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
 277
 278         /* Wait for FIFO read to complete */
 279         time_left =
 280             wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
 281
 282         if (!time_left) {
 283                 printf("RX FIFO time out\n");
 284                 return -EREMOTEIO;
 285         }
 286
 287         /* Read data from FIFO */
 288         for (; len > 0; len--, buf++)
 289                 *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
 290
 291         return 0;
 292 }
 293
 294 /* Read any amount of data using the RX FIFO from the i2c bus */
 295 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
 296                                   struct kona_i2c_msg *msg)
 297 {
 298         unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
 299         unsigned int last_byte_nak = 0;
 300         unsigned int bytes_read = 0;
 301         int rc;
 302
 303         uint8_t *tmp_buf = msg->buf;
 304
 305         while (bytes_read < msg->len) {
 306                 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
 307                         last_byte_nak = 1;      /* NAK last byte of transfer */
 308                         bytes_to_read = msg->len - bytes_read;
 309                 }
 310
 311                 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
 312                                                    last_byte_nak);
 313                 if (rc < 0)
 314                         return -EREMOTEIO;
 315
 316                 bytes_read += bytes_to_read;
 317                 tmp_buf += bytes_to_read;
 318         }
 319
 320         return 0;
 321 }
 322
 323 /* Write a single byte of data to the i2c bus */
 324 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
 325                                    unsigned int nak_expected)
 326 {
 327         unsigned long time_left = I2C_TIMEOUT;
 328         unsigned int nak_received;
 329
 330         /* Clear pending session done interrupt */
 331         writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
 332
 333         /* Send one byte of data */
 334         writel(data, dev->base + DAT_OFFSET);
 335
 336         time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
 337
 338         if (!time_left) {
 339                 debug("controller timed out\n");
 340                 return -ETIMEDOUT;
 341         }
 342
 343         nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
 344
 345         if (nak_received ^ nak_expected) {
 346                 debug("unexpected NAK/ACK\n");
 347                 return -EREMOTEIO;
 348         }
 349
 350         return 0;
 351 }
 352
 353 /* Write a single TX FIFO worth of data to the i2c bus */
 354 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
 355                                           uint8_t *buf, unsigned int len)
 356 {
 357         int k;
 358         unsigned long time_left = I2C_TIMEOUT;
 359         unsigned int fifo_status;
 360
 361         /* Write data into FIFO */
 362         for (k = 0; k < len; k++)
 363                 writel(buf[k], (dev->base + DAT_OFFSET));
 364
 365         /* Wait for FIFO to empty */
 366         do {
 367                 time_left =
 368                     wait_for_int_timeout(dev, time_left,
 369                                          (IER_FIFO_INT_EN_MASK |
 370                                           IER_NOACK_EN_MASK));
 371                 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
 372         } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
 373
 374         /* Check if there was a NAK */
 375         if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
 376                 printf("unexpected NAK\n");
 377                 return -EREMOTEIO;
 378         }
 379
 380         /* Check if a timeout occurred */
 381         if (!time_left) {
 382                 printf("completion timed out\n");
 383                 return -EREMOTEIO;
 384         }
 385
 386         return 0;
 387 }
 388
 389 /* Write any amount of data using TX FIFO to the i2c bus */
 390 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
 391                                    struct kona_i2c_msg *msg)
 392 {
 393         unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
 394         unsigned int bytes_written = 0;
 395         int rc;
 396
 397         uint8_t *tmp_buf = msg->buf;
 398
 399         while (bytes_written < msg->len) {
 400                 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
 401                         bytes_to_write = msg->len - bytes_written;
 402
 403                 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
 404                                                     bytes_to_write);
 405                 if (rc < 0)
 406                         return -EREMOTEIO;
 407
 408                 bytes_written += bytes_to_write;
 409                 tmp_buf += bytes_to_write;
 410         }
 411
 412         return 0;
 413 }
 414
 415 /* Send i2c address */
 416 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
 417                                 struct kona_i2c_msg *msg)
 418 {
 419         unsigned char addr;
 420
 421         if (msg->flags & I2C_M_TEN) {
 422                 /* First byte is 11110XX0 where XX is upper 2 bits */
 423                 addr = 0xf0 | ((msg->addr & 0x300) >> 7);
 424                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 425                         return -EREMOTEIO;
 426
 427                 /* Second byte is the remaining 8 bits */
 428                 addr = msg->addr & 0xff;
 429                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 430                         return -EREMOTEIO;
 431
 432                 if (msg->flags & I2C_M_RD) {
 433                         /* For read, send restart command */
 434                         if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
 435                                 return -EREMOTEIO;
 436
 437                         /* Then re-send the first byte with the read bit set */
 438                         addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
 439                         if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 440                                 return -EREMOTEIO;
 441                 }
 442         } else {
 443                 addr = msg->addr << 1;
 444
 445                 if (msg->flags & I2C_M_RD)
 446                         addr |= 1;
 447
 448                 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
 449                         return -EREMOTEIO;
 450         }
 451
 452         return 0;
 453 }
 454
 455 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
 456 {
 457         writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
 458                dev->base + CLKEN_OFFSET);
 459 }
 460
 461 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
 462 {
 463         writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
 464                dev->base + HSTIM_OFFSET);
 465
 466         writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
 467                (dev->std_cfg->time_p << TIM_P_SHIFT) |
 468                (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
 469                (dev->std_cfg->time_div << TIM_DIV_SHIFT),
 470                dev->base + TIM_OFFSET);
 471
 472         writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
 473                (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
 474                CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
 475 }
 476
 477 /* Master transfer function */
 478 static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
 479                              struct kona_i2c_msg msgs[], int num)
 480 {
 481         struct kona_i2c_msg *pmsg;
 482         int rc = 0;
 483         int i;
 484
 485         /* Enable pad output */
 486         writel(0, dev->base + PADCTL_OFFSET);
 487
 488         /* Enable internal clocks */
 489         bcm_kona_i2c_enable_clock(dev);
 490
 491         /* Send start command */
 492         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
 493         if (rc < 0) {
 494                 printf("Start command failed rc = %d\n", rc);
 495                 goto xfer_disable_pad;
 496         }
 497
 498         /* Loop through all messages */
 499         for (i = 0; i < num; i++) {
 500                 pmsg = &msgs[i];
 501
 502                 /* Send restart for subsequent messages */
 503                 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
 504                         rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
 505                         if (rc < 0) {
 506                                 printf("restart cmd failed rc = %d\n", rc);
 507                                 goto xfer_send_stop;
 508                         }
 509                 }
 510
 511                 /* Send slave address */
 512                 if (!(pmsg->flags & I2C_M_NOSTART)) {
 513                         rc = bcm_kona_i2c_do_addr(dev, pmsg);
 514                         if (rc < 0) {
 515                                 debug("NAK from addr %2.2x msg#%d rc = %d\n",
 516                                       pmsg->addr, i, rc);
 517                                 goto xfer_send_stop;
 518                         }
 519                 }
 520
 521                 /* Perform data transfer */
 522                 if (pmsg->flags & I2C_M_RD) {
 523                         rc = bcm_kona_i2c_read_fifo(dev, pmsg);
 524                         if (rc < 0) {
 525                                 printf("read failure\n");
 526                                 goto xfer_send_stop;
 527                         }
 528                 } else {
 529                         rc = bcm_kona_i2c_write_fifo(dev, pmsg);
 530                         if (rc < 0) {
 531                                 printf("write failure");
 532                                 goto xfer_send_stop;
 533                         }
 534                 }
 535         }
 536
 537         rc = num;
 538
 539 xfer_send_stop:
 540         /* Send a STOP command */
 541         bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
 542
 543 xfer_disable_pad:
 544         /* Disable pad output */
 545         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 546
 547         /* Stop internal clock */
 548         bcm_kona_i2c_disable_clock(dev);
 549
 550         return rc;
 551 }
 552
 553 static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
 554                                           uint speed)
 555 {
 556         switch (speed) {
 557         case I2C_SPEED_STANDARD_RATE:
 558                 dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_STANDARD];
 559                 break;
 560         case I2C_SPEED_FAST_RATE:
 561                 dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST];
 562                 break;
 563         case I2C_SPEED_FAST_PLUS_RATE:
 564                 dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST_PLUS];
 565                 break;
 566         default:
 567                 printf("%d hz bus speed not supported\n", speed);
 568                 return -EINVAL;
 569         }
 570         dev->speed = speed;
 571         return 0;
 572 }
 573
 574 static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
 575 {
 576         /* Parse bus speed */
 577         bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
 578
 579         /* Enable internal clocks */
 580         bcm_kona_i2c_enable_clock(dev);
 581
 582         /* Configure internal dividers */
 583         bcm_kona_i2c_config_timing(dev);
 584
 585         /* Disable timeout */
 586         writel(0, dev->base + TOUT_OFFSET);
 587
 588         /* Enable autosense */
 589         bcm_kona_i2c_enable_autosense(dev);
 590
 591         /* Enable TX FIFO */
 592         writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
 593                dev->base + TXFCR_OFFSET);
 594
 595         /* Mask all interrupts */
 596         writel(0, dev->base + IER_OFFSET);
 597
 598         /* Clear all pending interrupts */
 599         writel(ISR_CMDBUSY_MASK |
 600                ISR_READ_COMPLETE_MASK |
 601                ISR_SES_DONE_MASK |
 602                ISR_ERR_MASK |
 603                ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
 604
 605         /* Enable the controller but leave it idle */
 606         bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
 607
 608         /* Disable pad output */
 609         writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
 610 }
 611
 612 /*
 613  * uboot layer
 614  */
 615 struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
 616 {
 617         return &g_i2c_devs[adap->hwadapnr];
 618 }
 619
 620 static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 621 {
 622         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 623
 624         if (clk_bsc_enable(dev->base))
 625                 return;
 626
 627         bcm_kona_i2c_init(dev);
 628 }
 629
 630 static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 631                          int alen, uchar *buffer, int len)
 632 {
 633         /* msg[0] writes the addr, msg[1] reads the data */
 634         struct kona_i2c_msg msg[2];
 635         unsigned char msgbuf0[64];
 636         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 637
 638         msg[0].addr = chip;
 639         msg[0].flags = 0;
 640         msg[0].len = 1;
 641         msg[0].buf = msgbuf0;   /* msgbuf0 contains incrementing reg addr */
 642
 643         msg[1].addr = chip;
 644         msg[1].flags = I2C_M_RD;
 645         /* msg[1].buf dest ptr increments each read */
 646
 647         msgbuf0[0] = (unsigned char)addr;
 648         msg[1].buf = buffer;
 649         msg[1].len = len;
 650         if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
 651                 /* Sending 2 i2c messages */
 652                 kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 653                 debug("I2C read: I/O error\n");
 654                 return -EIO;
 655         }
 656         return 0;
 657 }
 658
 659 static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 660                           int alen, uchar *buffer, int len)
 661 {
 662         struct kona_i2c_msg msg[1];
 663         unsigned char msgbuf0[64];
 664         unsigned int i;
 665         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 666
 667         msg[0].addr = chip;
 668         msg[0].flags = 0;
 669         msg[0].len = 2;         /* addr byte plus data */
 670         msg[0].buf = msgbuf0;
 671
 672         for (i = 0; i < len; i++) {
 673                 msgbuf0[0] = addr++;
 674                 msgbuf0[1] = buffer[i];
 675                 if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
 676                         kona_i2c_init(adap, adap->speed, adap->slaveaddr);
 677                         debug("I2C write: I/O error\n");
 678                         return -EIO;
 679                 }
 680         }
 681         return 0;
 682 }
 683
 684 static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
 685 {
 686         uchar tmp;
 687
 688         /*
 689          * read addr 0x0 of the given chip.
 690          */
 691         return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
 692 }
 693
 694 static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 695 {
 696         struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
 697         return bcm_kona_i2c_assign_bus_speed(dev, speed);
 698 }
 699
 700 /*
 701  * Register kona i2c adapters. Keep the order below so
 702  * that the bus number matches the adapter number.
 703  */
 704 #define DEF_ADAPTER(num) \
 705 U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
 706                          kona_i2c_read, kona_i2c_write, \
 707                          kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
 708
 709 #ifdef CONFIG_SYS_I2C_BASE0
 710         DEF_ADAPTER(0)
 711 #endif
 712 #ifdef CONFIG_SYS_I2C_BASE1
 713         DEF_ADAPTER(1)
 714 #endif
 715 #ifdef CONFIG_SYS_I2C_BASE2
 716         DEF_ADAPTER(2)
 717 #endif
 718 #ifdef CONFIG_SYS_I2C_BASE3
 719         DEF_ADAPTER(3)
 720 #endif
 721 #ifdef CONFIG_SYS_I2C_BASE4
 722         DEF_ADAPTER(4)
 723 #endif
 724 #ifdef CONFIG_SYS_I2C_BASE5
 725         DEF_ADAPTER(5)
 726 #endif