drivers/i2c/imx_lpi2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductors, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <imx_lpi2c.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <dm.h>
  14 #include <fdtdec.h>
  15 #include <i2c.h>
  16 #include <dm/device_compat.h>
  17
  18 #define LPI2C_FIFO_SIZE 4
  19 #define LPI2C_NACK_TOUT_MS 1
  20 #define LPI2C_TIMEOUT_MS 100
  21
  22 static int bus_i2c_init(struct udevice *bus, int speed);
  23
  24 /* Weak linked function for overridden by some SoC power function */
  25 int __weak init_i2c_power(unsigned i2c_num)
  26 {
  27         return 0;
  28 }
  29
  30 static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
  31 {
  32         lpi2c_status_t result = LPI2C_SUCESS;
  33         u32 status;
  34
  35         status = readl(&regs->msr);
  36
  37         if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
  38                 result = LPI2C_BUSY;
  39
  40         return result;
  41 }
  42
  43 static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
  44 {
  45         lpi2c_status_t result = LPI2C_SUCESS;
  46         u32 val, status;
  47
  48         status = readl(&regs->msr);
  49         /* errors to check for */
  50         status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
  51                 LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
  52
  53         if (status) {
  54                 if (status & LPI2C_MSR_PLTF_MASK)
  55                         result = LPI2C_PIN_LOW_TIMEOUT_ERR;
  56                 else if (status & LPI2C_MSR_ALF_MASK)
  57                         result = LPI2C_ARB_LOST_ERR;
  58                 else if (status & LPI2C_MSR_NDF_MASK)
  59                         result = LPI2C_NAK_ERR;
  60                 else if (status & LPI2C_MSR_FEF_MASK)
  61                         result = LPI2C_FIFO_ERR;
  62
  63                 /* clear status flags */
  64                 writel(0x7f00, &regs->msr);
  65                 /* reset fifos */
  66                 val = readl(&regs->mcr);
  67                 val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
  68                 writel(val, &regs->mcr);
  69         }
  70
  71         return result;
  72 }
  73
  74 static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
  75 {
  76         lpi2c_status_t result = LPI2C_SUCESS;
  77         u32 txcount = 0;
  78         ulong start_time = get_timer(0);
  79
  80         do {
  81                 txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
  82                 txcount = LPI2C_FIFO_SIZE - txcount;
  83                 result = imx_lpci2c_check_clear_error(regs);
  84                 if (result) {
  85                         debug("i2c: wait for tx ready: result 0x%x\n", result);
  86                         return result;
  87                 }
  88                 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
  89                         debug("i2c: wait for tx ready: timeout\n");
  90                         return -1;
  91                 }
  92         } while (!txcount);
  93
  94         return result;
  95 }
  96
  97 static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
  98 {
  99         struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 100         lpi2c_status_t result = LPI2C_SUCESS;
 101
 102         /* empty tx */
 103         if (!len)
 104                 return result;
 105
 106         while (len--) {
 107                 result = bus_i2c_wait_for_tx_ready(regs);
 108                 if (result) {
 109                         debug("i2c: send wait for tx ready: %d\n", result);
 110                         return result;
 111                 }
 112                 writel(*txbuf++, &regs->mtdr);
 113         }
 114
 115         return result;
 116 }
 117
 118 static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
 119 {
 120         struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 121         lpi2c_status_t result = LPI2C_SUCESS;
 122         u32 val;
 123         ulong start_time = get_timer(0);
 124
 125         /* empty read */
 126         if (!len)
 127                 return result;
 128
 129         result = bus_i2c_wait_for_tx_ready(regs);
 130         if (result) {
 131                 debug("i2c: receive wait fot tx ready: %d\n", result);
 132                 return result;
 133         }
 134
 135         /* clear all status flags */
 136         writel(0x7f00, &regs->msr);
 137         /* send receive command */
 138         val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
 139         writel(val, &regs->mtdr);
 140
 141         while (len--) {
 142                 do {
 143                         result = imx_lpci2c_check_clear_error(regs);
 144                         if (result) {
 145                                 debug("i2c: receive check clear error: %d\n",
 146                                       result);
 147                                 return result;
 148                         }
 149                         if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
 150                                 debug("i2c: receive mrdr: timeout\n");
 151                                 return -1;
 152                         }
 153                         val = readl(&regs->mrdr);
 154                 } while (val & LPI2C_MRDR_RXEMPTY_MASK);
 155                 *rxbuf++ = LPI2C_MRDR_DATA(val);
 156         }
 157
 158         return result;
 159 }
 160
 161 static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
 162 {
 163         lpi2c_status_t result;
 164         struct imx_lpi2c_reg *regs =
 165                 (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 166         u32 val;
 167
 168         result = imx_lpci2c_check_busy_bus(regs);
 169         if (result) {
 170                 debug("i2c: start check busy bus: 0x%x\n", result);
 171
 172                 /* Try to init the lpi2c then check the bus busy again */
 173                 bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
 174                 result = imx_lpci2c_check_busy_bus(regs);
 175                 if (result) {
 176                         printf("i2c: Error check busy bus: 0x%x\n", result);
 177                         return result;
 178                 }
 179         }
 180         /* clear all status flags */
 181         writel(0x7f00, &regs->msr);
 182         /* turn off auto-stop condition */
 183         val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
 184         writel(val, &regs->mcfgr1);
 185         /* wait tx fifo ready */
 186         result = bus_i2c_wait_for_tx_ready(regs);
 187         if (result) {
 188                 debug("i2c: start wait for tx ready: 0x%x\n", result);
 189                 return result;
 190         }
 191         /* issue start command */
 192         val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
 193         writel(val, &regs->mtdr);
 194
 195         return result;
 196 }
 197
 198 static int bus_i2c_stop(struct udevice *bus)
 199 {
 200         lpi2c_status_t result;
 201         struct imx_lpi2c_reg *regs =
 202                 (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 203         u32 status;
 204         ulong start_time;
 205
 206         result = bus_i2c_wait_for_tx_ready(regs);
 207         if (result) {
 208                 debug("i2c: stop wait for tx ready: 0x%x\n", result);
 209                 return result;
 210         }
 211
 212         /* send stop command */
 213         writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);
 214
 215         start_time = get_timer(0);
 216         while (1) {
 217                 status = readl(&regs->msr);
 218                 result = imx_lpci2c_check_clear_error(regs);
 219                 /* stop detect flag */
 220                 if (status & LPI2C_MSR_SDF_MASK) {
 221                         /* clear stop flag */
 222                         status &= LPI2C_MSR_SDF_MASK;
 223                         writel(status, &regs->msr);
 224                         break;
 225                 }
 226
 227                 if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
 228                         debug("stop timeout\n");
 229                         return -ETIMEDOUT;
 230                 }
 231         }
 232
 233         return result;
 234 }
 235
 236 static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
 237 {
 238         lpi2c_status_t result;
 239
 240         result = bus_i2c_start(bus, chip, 1);
 241         if (result)
 242                 return result;
 243         result = bus_i2c_receive(bus, buf, len);
 244         if (result)
 245                 return result;
 246
 247         return result;
 248 }
 249
 250 static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
 251 {
 252         lpi2c_status_t result;
 253
 254         result = bus_i2c_start(bus, chip, 0);
 255         if (result)
 256                 return result;
 257         result = bus_i2c_send(bus, buf, len);
 258         if (result)
 259                 return result;
 260
 261         return result;
 262 }
 263
 264
 265 u32 __weak imx_get_i2cclk(u32 i2c_num)
 266 {
 267         return 0;
 268 }
 269
 270 static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
 271 {
 272         struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
 273         struct imx_lpi2c_reg *regs;
 274         u32 val;
 275         u32 preescale = 0, best_pre = 0, clkhi = 0;
 276         u32 best_clkhi = 0, abs_error = 0, rate;
 277         u32 error = 0xffffffff;
 278         u32 clock_rate;
 279         bool mode;
 280         int i;
 281
 282         regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 283
 284         if (IS_ENABLED(CONFIG_CLK)) {
 285                 clock_rate = clk_get_rate(&i2c_bus->per_clk);
 286                 if (clock_rate <= 0) {
 287                         dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
 288                         return clock_rate;
 289                 }
 290         } else {
 291                 clock_rate = imx_get_i2cclk(bus->seq);
 292                 if (!clock_rate)
 293                         return -EPERM;
 294         }
 295
 296         mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
 297         /* disable master mode */
 298         val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
 299         writel(val | LPI2C_MCR_MEN(0), &regs->mcr);
 300
 301         for (preescale = 1; (preescale <= 128) &&
 302                 (error != 0); preescale = 2 * preescale) {
 303                 for (clkhi = 1; clkhi < 32; clkhi++) {
 304                         if (clkhi == 1)
 305                                 rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
 306                         else
 307                                 rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
 308
 309                         abs_error = speed > rate ? speed - rate : rate - speed;
 310
 311                         if (abs_error < error) {
 312                                 best_pre = preescale;
 313                                 best_clkhi = clkhi;
 314                                 error = abs_error;
 315                                 if (abs_error == 0)
 316                                         break;
 317                         }
 318                 }
 319         }
 320
 321         /* Standard, fast, fast mode plus and ultra-fast transfers. */
 322         val = LPI2C_MCCR0_CLKHI(best_clkhi);
 323         if (best_clkhi < 2)
 324                 val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
 325         else
 326                 val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
 327                         LPI2C_MCCR0_DATAVD(best_clkhi / 2);
 328         writel(val, &regs->mccr0);
 329
 330         for (i = 0; i < 8; i++) {
 331                 if (best_pre == (1 << i)) {
 332                         best_pre = i;
 333                         break;
 334                 }
 335         }
 336
 337         val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
 338         writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);
 339
 340         if (mode) {
 341                 val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
 342                 writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
 343         }
 344
 345         return 0;
 346 }
 347
 348 static int bus_i2c_init(struct udevice *bus, int speed)
 349 {
 350         struct imx_lpi2c_reg *regs;
 351         u32 val;
 352         int ret;
 353
 354         regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 355         /* reset peripheral */
 356         writel(LPI2C_MCR_RST_MASK, &regs->mcr);
 357         writel(0x0, &regs->mcr);
 358         /* Disable Dozen mode */
 359         writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);
 360         /* host request disable, active high, external pin */
 361         val = readl(&regs->mcfgr0);
 362         val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
 363                                 LPI2C_MCFGR0_HRSEL_MASK));
 364         val |= LPI2C_MCFGR0_HRPOL(0x1);
 365         writel(val, &regs->mcfgr0);
 366         /* pincfg and ignore ack */
 367         val = readl(&regs->mcfgr1);
 368         val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
 369         val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
 370         val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
 371         writel(val, &regs->mcfgr1);
 372
 373         ret = bus_i2c_set_bus_speed(bus, speed);
 374
 375         /* enable lpi2c in master mode */
 376         val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
 377         writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
 378
 379         debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
 380
 381         return ret;
 382 }
 383
 384 static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
 385                                 u32 chip_flags)
 386 {
 387         lpi2c_status_t result;
 388
 389         result = bus_i2c_start(bus, chip, 0);
 390         if (result) {
 391                 bus_i2c_stop(bus);
 392                 bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
 393                 return result;
 394         }
 395
 396         result = bus_i2c_stop(bus);
 397         if (result)
 398                 bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
 399
 400         return result;
 401 }
 402
 403 static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 404 {
 405         int ret = 0, ret_stop;
 406
 407         for (; nmsgs > 0; nmsgs--, msg++) {
 408                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 409                 if (msg->flags & I2C_M_RD)
 410                         ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
 411                 else {
 412                         ret = bus_i2c_write(bus, msg->addr, msg->buf,
 413                                             msg->len);
 414                         if (ret)
 415                                 break;
 416                 }
 417         }
 418
 419         if (ret)
 420                 debug("i2c_write: error sending\n");
 421
 422         ret_stop = bus_i2c_stop(bus);
 423         if (ret_stop)
 424                 debug("i2c_xfer: stop bus error\n");
 425
 426         ret |= ret_stop;
 427
 428         return ret;
 429 }
 430
 431 static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 432 {
 433         return bus_i2c_set_bus_speed(bus, speed);
 434 }
 435
 436 __weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
 437 {
 438         return 0;
 439 }
 440
 441 static int imx_lpi2c_probe(struct udevice *bus)
 442 {
 443         struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
 444         fdt_addr_t addr;
 445         int ret;
 446
 447         i2c_bus->driver_data = dev_get_driver_data(bus);
 448
 449         addr = devfdt_get_addr(bus);
 450         if (addr == FDT_ADDR_T_NONE)
 451                 return -EINVAL;
 452
 453         i2c_bus->base = addr;
 454         i2c_bus->index = bus->seq;
 455         i2c_bus->bus = bus;
 456
 457         /* power up i2c resource */
 458         ret = init_i2c_power(bus->seq);
 459         if (ret) {
 460                 debug("init_i2c_power err = %d\n", ret);
 461                 return ret;
 462         }
 463
 464         if (IS_ENABLED(CONFIG_CLK)) {
 465                 ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
 466                 if (ret) {
 467                         dev_err(bus, "Failed to get per clk\n");
 468                         return ret;
 469                 }
 470                 ret = clk_enable(&i2c_bus->per_clk);
 471                 if (ret) {
 472                         dev_err(bus, "Failed to enable per clk\n");
 473                         return ret;
 474                 }
 475
 476                 ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
 477                 if (ret) {
 478                         dev_err(bus, "Failed to get ipg clk\n");
 479                         return ret;
 480                 }
 481                 ret = clk_enable(&i2c_bus->ipg_clk);
 482                 if (ret) {
 483                         dev_err(bus, "Failed to enable ipg clk\n");
 484                         return ret;
 485                 }
 486         } else {
 487                 /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
 488                 ret = enable_i2c_clk(1, bus->seq);
 489                 if (ret < 0)
 490                         return ret;
 491         }
 492
 493         ret = bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
 494         if (ret < 0)
 495                 return ret;
 496
 497         debug("i2c : controller bus %d at 0x%lx , speed %d: ",
 498               bus->seq, i2c_bus->base,
 499               i2c_bus->speed);
 500
 501         return 0;
 502 }
 503
 504 static const struct dm_i2c_ops imx_lpi2c_ops = {
 505         .xfer           = imx_lpi2c_xfer,
 506         .probe_chip     = imx_lpi2c_probe_chip,
 507         .set_bus_speed  = imx_lpi2c_set_bus_speed,
 508 };
 509
 510 static const struct udevice_id imx_lpi2c_ids[] = {
 511         { .compatible = "fsl,imx7ulp-lpi2c", },
 512         { .compatible = "fsl,imx8qm-lpi2c", },
 513         {}
 514 };
 515
 516 U_BOOT_DRIVER(imx_lpi2c) = {
 517         .name = "imx_lpi2c",
 518         .id = UCLASS_I2C,
 519         .of_match = imx_lpi2c_ids,
 520         .probe = imx_lpi2c_probe,
 521         .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
 522         .ops = &imx_lpi2c_ops,
 523 };