1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductors, Inc.
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <imx_lpi2c.h>
12 #include <asm/arch/sys_proto.h>
16 #include <dm/device_compat.h>
18 #define LPI2C_FIFO_SIZE 4
19 #define LPI2C_NACK_TOUT_MS 1
20 #define LPI2C_TIMEOUT_MS 100
22 static int bus_i2c_init(struct udevice *bus, int speed);
24 /* Weak linked function for overridden by some SoC power function */
25 int __weak init_i2c_power(unsigned i2c_num)
30 static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
32 lpi2c_status_t result = LPI2C_SUCESS;
35 status = readl(®s->msr);
37 if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
43 static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
45 lpi2c_status_t result = LPI2C_SUCESS;
48 status = readl(®s->msr);
49 /* errors to check for */
50 status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
51 LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
54 if (status & LPI2C_MSR_PLTF_MASK)
55 result = LPI2C_PIN_LOW_TIMEOUT_ERR;
56 else if (status & LPI2C_MSR_ALF_MASK)
57 result = LPI2C_ARB_LOST_ERR;
58 else if (status & LPI2C_MSR_NDF_MASK)
59 result = LPI2C_NAK_ERR;
60 else if (status & LPI2C_MSR_FEF_MASK)
61 result = LPI2C_FIFO_ERR;
63 /* clear status flags */
64 writel(0x7f00, ®s->msr);
66 val = readl(®s->mcr);
67 val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
68 writel(val, ®s->mcr);
74 static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
76 lpi2c_status_t result = LPI2C_SUCESS;
78 ulong start_time = get_timer(0);
81 txcount = LPI2C_MFSR_TXCOUNT(readl(®s->mfsr));
82 txcount = LPI2C_FIFO_SIZE - txcount;
83 result = imx_lpci2c_check_clear_error(regs);
85 debug("i2c: wait for tx ready: result 0x%x\n", result);
88 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
89 debug("i2c: wait for tx ready: timeout\n");
97 static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
99 struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
100 lpi2c_status_t result = LPI2C_SUCESS;
107 result = bus_i2c_wait_for_tx_ready(regs);
109 debug("i2c: send wait for tx ready: %d\n", result);
112 writel(*txbuf++, ®s->mtdr);
118 static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
120 struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
121 lpi2c_status_t result = LPI2C_SUCESS;
123 ulong start_time = get_timer(0);
129 result = bus_i2c_wait_for_tx_ready(regs);
131 debug("i2c: receive wait fot tx ready: %d\n", result);
135 /* clear all status flags */
136 writel(0x7f00, ®s->msr);
137 /* send receive command */
138 val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
139 writel(val, ®s->mtdr);
143 result = imx_lpci2c_check_clear_error(regs);
145 debug("i2c: receive check clear error: %d\n",
149 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
150 debug("i2c: receive mrdr: timeout\n");
153 val = readl(®s->mrdr);
154 } while (val & LPI2C_MRDR_RXEMPTY_MASK);
155 *rxbuf++ = LPI2C_MRDR_DATA(val);
161 static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
163 lpi2c_status_t result;
164 struct imx_lpi2c_reg *regs =
165 (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
168 result = imx_lpci2c_check_busy_bus(regs);
170 debug("i2c: start check busy bus: 0x%x\n", result);
172 /* Try to init the lpi2c then check the bus busy again */
173 bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
174 result = imx_lpci2c_check_busy_bus(regs);
176 printf("i2c: Error check busy bus: 0x%x\n", result);
180 /* clear all status flags */
181 writel(0x7f00, ®s->msr);
182 /* turn off auto-stop condition */
183 val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
184 writel(val, ®s->mcfgr1);
185 /* wait tx fifo ready */
186 result = bus_i2c_wait_for_tx_ready(regs);
188 debug("i2c: start wait for tx ready: 0x%x\n", result);
191 /* issue start command */
192 val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
193 writel(val, ®s->mtdr);
198 static int bus_i2c_stop(struct udevice *bus)
200 lpi2c_status_t result;
201 struct imx_lpi2c_reg *regs =
202 (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
206 result = bus_i2c_wait_for_tx_ready(regs);
208 debug("i2c: stop wait for tx ready: 0x%x\n", result);
212 /* send stop command */
213 writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr);
215 start_time = get_timer(0);
217 status = readl(®s->msr);
218 result = imx_lpci2c_check_clear_error(regs);
219 /* stop detect flag */
220 if (status & LPI2C_MSR_SDF_MASK) {
221 /* clear stop flag */
222 status &= LPI2C_MSR_SDF_MASK;
223 writel(status, ®s->msr);
227 if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
228 debug("stop timeout\n");
236 static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
238 lpi2c_status_t result;
240 result = bus_i2c_start(bus, chip, 1);
243 result = bus_i2c_receive(bus, buf, len);
250 static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
252 lpi2c_status_t result;
254 result = bus_i2c_start(bus, chip, 0);
257 result = bus_i2c_send(bus, buf, len);
265 u32 __weak imx_get_i2cclk(u32 i2c_num)
270 static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
272 struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
273 struct imx_lpi2c_reg *regs;
275 u32 preescale = 0, best_pre = 0, clkhi = 0;
276 u32 best_clkhi = 0, abs_error = 0, rate;
277 u32 error = 0xffffffff;
282 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
284 if (IS_ENABLED(CONFIG_CLK)) {
285 clock_rate = clk_get_rate(&i2c_bus->per_clk);
286 if (clock_rate <= 0) {
287 dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
291 clock_rate = imx_get_i2cclk(bus->seq);
296 mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
297 /* disable master mode */
298 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
299 writel(val | LPI2C_MCR_MEN(0), ®s->mcr);
301 for (preescale = 1; (preescale <= 128) &&
302 (error != 0); preescale = 2 * preescale) {
303 for (clkhi = 1; clkhi < 32; clkhi++) {
305 rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
307 rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
309 abs_error = speed > rate ? speed - rate : rate - speed;
311 if (abs_error < error) {
312 best_pre = preescale;
321 /* Standard, fast, fast mode plus and ultra-fast transfers. */
322 val = LPI2C_MCCR0_CLKHI(best_clkhi);
324 val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
326 val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
327 LPI2C_MCCR0_DATAVD(best_clkhi / 2);
328 writel(val, ®s->mccr0);
330 for (i = 0; i < 8; i++) {
331 if (best_pre == (1 << i)) {
337 val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
338 writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), ®s->mcfgr1);
341 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
342 writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
348 static int bus_i2c_init(struct udevice *bus, int speed)
350 struct imx_lpi2c_reg *regs;
354 regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
355 /* reset peripheral */
356 writel(LPI2C_MCR_RST_MASK, ®s->mcr);
357 writel(0x0, ®s->mcr);
358 /* Disable Dozen mode */
359 writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s->mcr);
360 /* host request disable, active high, external pin */
361 val = readl(®s->mcfgr0);
362 val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
363 LPI2C_MCFGR0_HRSEL_MASK));
364 val |= LPI2C_MCFGR0_HRPOL(0x1);
365 writel(val, ®s->mcfgr0);
366 /* pincfg and ignore ack */
367 val = readl(®s->mcfgr1);
368 val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
369 val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
370 val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
371 writel(val, ®s->mcfgr1);
373 ret = bus_i2c_set_bus_speed(bus, speed);
375 /* enable lpi2c in master mode */
376 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK;
377 writel(val | LPI2C_MCR_MEN(1), ®s->mcr);
379 debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
384 static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
387 lpi2c_status_t result;
389 result = bus_i2c_start(bus, chip, 0);
392 bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
396 result = bus_i2c_stop(bus);
398 bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
403 static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
405 int ret = 0, ret_stop;
407 for (; nmsgs > 0; nmsgs--, msg++) {
408 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
409 if (msg->flags & I2C_M_RD)
410 ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
412 ret = bus_i2c_write(bus, msg->addr, msg->buf,
420 debug("i2c_write: error sending\n");
422 ret_stop = bus_i2c_stop(bus);
424 debug("i2c_xfer: stop bus error\n");
431 static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
433 return bus_i2c_set_bus_speed(bus, speed);
436 __weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
441 static int imx_lpi2c_probe(struct udevice *bus)
443 struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
447 i2c_bus->driver_data = dev_get_driver_data(bus);
449 addr = devfdt_get_addr(bus);
450 if (addr == FDT_ADDR_T_NONE)
453 i2c_bus->base = addr;
454 i2c_bus->index = bus->seq;
457 /* power up i2c resource */
458 ret = init_i2c_power(bus->seq);
460 debug("init_i2c_power err = %d\n", ret);
464 if (IS_ENABLED(CONFIG_CLK)) {
465 ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
467 dev_err(bus, "Failed to get per clk\n");
470 ret = clk_enable(&i2c_bus->per_clk);
472 dev_err(bus, "Failed to enable per clk\n");
476 ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
478 dev_err(bus, "Failed to get ipg clk\n");
481 ret = clk_enable(&i2c_bus->ipg_clk);
483 dev_err(bus, "Failed to enable ipg clk\n");
487 /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
488 ret = enable_i2c_clk(1, bus->seq);
493 ret = bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE);
497 debug("i2c : controller bus %d at 0x%lx , speed %d: ",
498 bus->seq, i2c_bus->base,
504 static const struct dm_i2c_ops imx_lpi2c_ops = {
505 .xfer = imx_lpi2c_xfer,
506 .probe_chip = imx_lpi2c_probe_chip,
507 .set_bus_speed = imx_lpi2c_set_bus_speed,
510 static const struct udevice_id imx_lpi2c_ids[] = {
511 { .compatible = "fsl,imx7ulp-lpi2c", },
512 { .compatible = "fsl,imx8qm-lpi2c", },
516 U_BOOT_DRIVER(imx_lpi2c) = {
519 .of_match = imx_lpi2c_ids,
520 .probe = imx_lpi2c_probe,
521 .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
522 .ops = &imx_lpi2c_ops,