drivers/i2c/ihs_i2c.c

   1 /*
   2  * (C) Copyright 2013
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <i2c.h>
  10 #include <gdsys_fpga.h>
  11
  12 DECLARE_GLOBAL_DATA_PTR;
  13
  14 enum {
  15         I2CINT_ERROR_EV = 1 << 13,
  16         I2CINT_TRANSMIT_EV = 1 << 14,
  17         I2CINT_RECEIVE_EV = 1 << 15,
  18 };
  19
  20 enum {
  21         I2CMB_WRITE = 1 << 10,
  22         I2CMB_2BYTE = 1 << 11,
  23         I2CMB_HOLD_BUS = 1 << 13,
  24         I2CMB_NATIVE = 2 << 14,
  25 };
  26
  27 static int wait_for_int(bool read)
  28 {
  29         u16 val;
  30         unsigned int ctr = 0;
  31
  32         FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
  33         while (!(val & (I2CINT_ERROR_EV
  34                | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
  35                 udelay(10);
  36                 if (ctr++ > 5000) {
  37                         printf("I2C timeout\n");
  38                         return 1;
  39                 }
  40                 FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
  41         }
  42
  43         return (val & I2CINT_ERROR_EV) ? 1 : 0;
  44 }
  45
  46 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
  47                             bool is_last)
  48 {
  49         u16 val;
  50
  51         FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
  52                      | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
  53         FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
  54
  55         if (!read && len) {
  56                 val = buffer[0];
  57
  58                 if (len > 1)
  59                         val |= buffer[1] << 8;
  60                 FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
  61         }
  62
  63         FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
  64                      I2CMB_NATIVE
  65                      | (read ? 0 : I2CMB_WRITE)
  66                      | (chip << 1)
  67                      | ((len > 1) ? I2CMB_2BYTE : 0)
  68                      | (is_last ? 0 : I2CMB_HOLD_BUS));
  69
  70         if (wait_for_int(read))
  71                 return 1;
  72
  73         if (read) {
  74                 FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val);
  75                 buffer[0] = val & 0xff;
  76                 if (len > 1)
  77                         buffer[1] = val >> 8;
  78         }
  79
  80         return 0;
  81 }
  82
  83 static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus)
  84 {
  85         int shift = (alen-1) * 8;
  86
  87         while (alen) {
  88                 int transfer = MIN(alen, 2);
  89                 uchar buf[2];
  90                 bool is_last = alen <= transfer;
  91
  92                 buf[0] = addr >> shift;
  93                 if (alen > 1)
  94                         buf[1] = addr >> (shift - 8);
  95
  96                 if (ihs_i2c_transfer(chip, buf, transfer, false,
  97                                      hold_bus ? false : is_last))
  98                         return 1;
  99
 100                 shift -= 16;
 101                 alen -= transfer;
 102         }
 103
 104         return 0;
 105 }
 106
 107 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr,
 108                           int alen, uchar *buffer, int len, bool read)
 109 {
 110         if (len <= 0)
 111                 return 1;
 112
 113         if (ihs_i2c_address(chip, addr, alen, !read))
 114                 return 1;
 115
 116         while (len) {
 117                 int transfer = MIN(len, 2);
 118
 119                 if (ihs_i2c_transfer(chip, buffer, transfer, read,
 120                                      len <= transfer))
 121                         return 1;
 122
 123                 buffer += transfer;
 124                 addr += transfer;
 125                 len -= transfer;
 126         }
 127
 128         return 0;
 129 }
 130
 131
 132 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 133 {
 134 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 135         /*
 136          * Call board specific i2c bus reset routine before accessing the
 137          * environment, which might be in a chip on that bus. For details
 138          * about this problem see doc/I2C_Edge_Conditions.
 139          */
 140         i2c_init_board();
 141 #endif
 142 }
 143
 144 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
 145 {
 146         uchar buffer[2];
 147
 148         if (ihs_i2c_transfer(chip, buffer, 0, true, true))
 149                 return 1;
 150
 151         return 0;
 152 }
 153
 154 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 155                         int alen, uchar *buffer, int len)
 156 {
 157         return ihs_i2c_access(adap, chip, addr, alen, buffer, len, true);
 158 }
 159
 160 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 161                          int alen, uchar *buffer, int len)
 162 {
 163         return ihs_i2c_access(adap, chip, addr, alen, buffer, len, false);
 164 }
 165
 166 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
 167                                              unsigned int speed)
 168 {
 169         if (speed != adap->speed)
 170                 return 1;
 171         return speed;
 172 }
 173
 174 /*
 175  * Register IHS i2c adapters
 176  */
 177 #ifdef CONFIG_SYS_I2C_IHS_CH0
 178 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
 179                          ihs_i2c_read, ihs_i2c_write,
 180                          ihs_i2c_set_bus_speed,
 181                          CONFIG_SYS_I2C_IHS_SPEED_0,
 182                          CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
 183 #endif
 184 #ifdef CONFIG_SYS_I2C_IHS_CH1
 185 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
 186                          ihs_i2c_read, ihs_i2c_write,
 187                          ihs_i2c_set_bus_speed,
 188                          CONFIG_SYS_I2C_IHS_SPEED_1,
 189                          CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
 190 #endif
 191 #ifdef CONFIG_SYS_I2C_IHS_CH2
 192 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
 193                          ihs_i2c_read, ihs_i2c_write,
 194                          ihs_i2c_set_bus_speed,
 195                          CONFIG_SYS_I2C_IHS_SPEED_2,
 196                          CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
 197 #endif
 198 #ifdef CONFIG_SYS_I2C_IHS_CH3
 199 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
 200                          ihs_i2c_read, ihs_i2c_write,
 201                          ihs_i2c_set_bus_speed,
 202                          CONFIG_SYS_I2C_IHS_SPEED_3,
 203                          CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
 204 #endif