drivers/i2c/ihs_i2c.c

   1 /*
   2  * (C) Copyright 2013
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * NOTE: This driver should be converted to driver model before June 2017.
   8  * Please see doc/driver-model/i2c-howto.txt for instructions.
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <gdsys_fpga.h>
  14 #include <asm/unaligned.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #ifdef CONFIG_SYS_I2C_IHS_DUAL
  19 #define I2C_SET_REG(fld, val) \
  20         do { \
  21                 if (I2C_ADAP_HWNR & 0x10) \
  22                         FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  23                 else \
  24                         FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  25         } while (0)
  26 #else
  27 #define I2C_SET_REG(fld, val) \
  28                 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  29 #endif
  30
  31 #ifdef CONFIG_SYS_I2C_IHS_DUAL
  32 #define I2C_GET_REG(fld, val) \
  33         do {                                    \
  34                 if (I2C_ADAP_HWNR & 0x10) \
  35                         FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
  36                 else \
  37                         FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
  38         } while (0)
  39 #else
  40 #define I2C_GET_REG(fld, val) \
  41                 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
  42 #endif
  43
  44 enum {
  45         I2CINT_ERROR_EV = BIT(13),
  46         I2CINT_TRANSMIT_EV = BIT(14),
  47         I2CINT_RECEIVE_EV = BIT(15),
  48 };
  49
  50 enum {
  51         I2CMB_READ = 0 << 10,
  52         I2CMB_WRITE = 1 << 10,
  53         I2CMB_1BYTE = 0 << 11,
  54         I2CMB_2BYTE = 1 << 11,
  55         I2CMB_DONT_HOLD_BUS = 0 << 13,
  56         I2CMB_HOLD_BUS = 1 << 13,
  57         I2CMB_NATIVE = 2 << 14,
  58 };
  59
  60 enum {
  61         I2COP_WRITE = 0,
  62         I2COP_READ = 1,
  63 };
  64
  65 static int wait_for_int(bool read)
  66 {
  67         u16 val;
  68         uint ctr = 0;
  69
  70         I2C_GET_REG(interrupt_status, &val);
  71         /* Wait until error or receive/transmit interrupt was raised */
  72         while (!(val & (I2CINT_ERROR_EV
  73                | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
  74                 udelay(10);
  75                 if (ctr++ > 5000)
  76                         return 1;
  77                 I2C_GET_REG(interrupt_status, &val);
  78         }
  79
  80         return (val & I2CINT_ERROR_EV) ? 1 : 0;
  81 }
  82
  83 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
  84                             bool is_last)
  85 {
  86         u16 val;
  87
  88         /* Clear interrupt status */
  89         I2C_SET_REG(interrupt_status, I2CINT_ERROR_EV
  90                      | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
  91         I2C_GET_REG(interrupt_status, &val);
  92
  93         /* If we want to write and have data, write the bytes to the mailbox */
  94         if (!read && len) {
  95                 val = buffer[0];
  96
  97                 if (len > 1)
  98                         val |= buffer[1] << 8;
  99                 I2C_SET_REG(write_mailbox_ext, val);
 100         }
 101
 102         I2C_SET_REG(write_mailbox,
 103                     I2CMB_NATIVE
 104                     | (read ? 0 : I2CMB_WRITE)
 105                     | (chip << 1)
 106                     | ((len > 1) ? I2CMB_2BYTE : 0)
 107                     | (is_last ? 0 : I2CMB_HOLD_BUS));
 108
 109         if (wait_for_int(read))
 110                 return 1;
 111
 112         /* If we want to read, get the bytes from the mailbox */
 113         if (read) {
 114                 I2C_GET_REG(read_mailbox_ext, &val);
 115                 buffer[0] = val & 0xff;
 116                 if (len > 1)
 117                         buffer[1] = val >> 8;
 118         }
 119
 120         return 0;
 121 }
 122
 123 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
 124 {
 125         while (alen) {
 126                 int transfer = min(alen, 2);
 127                 bool is_last = alen <= transfer;
 128
 129                 if (ihs_i2c_transfer(chip, addr, transfer, I2COP_WRITE,
 130                                      hold_bus ? false : is_last))
 131                         return 1;
 132
 133                 alen -= transfer;
 134         }
 135
 136         return 0;
 137 }
 138
 139 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
 140                           int alen, uchar *buffer, int len, int read)
 141 {
 142         /* Don't hold the bus if length of data to send/receive is zero */
 143         if (len <= 0 || ihs_i2c_address(chip, addr, alen, len))
 144                 return 1;
 145
 146         while (len) {
 147                 int transfer = min(len, 2);
 148                 bool is_last = len <= transfer;
 149
 150                 if (ihs_i2c_transfer(chip, buffer, transfer, read,
 151                                      is_last))
 152                         return 2;
 153
 154                 buffer += transfer;
 155                 len -= transfer;
 156         }
 157
 158         return 0;
 159 }
 160
 161 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 162 {
 163 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 164         /*
 165          * Call board specific i2c bus reset routine before accessing the
 166          * environment, which might be in a chip on that bus. For details
 167          * about this problem see doc/I2C_Edge_Conditions.
 168          */
 169         i2c_init_board();
 170 #endif
 171 }
 172
 173 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
 174 {
 175         uchar buffer[2];
 176
 177         if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true))
 178                 return 1;
 179
 180         return 0;
 181 }
 182
 183 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 184                         int alen, uchar *buffer, int len)
 185 {
 186         u8 addr_bytes[4];
 187
 188         put_unaligned_le32(addr, addr_bytes);
 189
 190         return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
 191                               I2COP_READ);
 192 }
 193
 194 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 195                          int alen, uchar *buffer, int len)
 196 {
 197         u8 addr_bytes[4];
 198
 199         put_unaligned_le32(addr, addr_bytes);
 200
 201         return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
 202                               I2COP_WRITE);
 203 }
 204
 205 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
 206                                           unsigned int speed)
 207 {
 208         if (speed != adap->speed)
 209                 return 1;
 210         return speed;
 211 }
 212
 213 /*
 214  * Register IHS i2c adapters
 215  */
 216 #ifdef CONFIG_SYS_I2C_IHS_CH0
 217 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
 218                          ihs_i2c_read, ihs_i2c_write,
 219                          ihs_i2c_set_bus_speed,
 220                          CONFIG_SYS_I2C_IHS_SPEED_0,
 221                          CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
 222 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 223 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
 224                          ihs_i2c_read, ihs_i2c_write,
 225                          ihs_i2c_set_bus_speed,
 226                          CONFIG_SYS_I2C_IHS_SPEED_0_1,
 227                          CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
 228 #endif
 229 #endif
 230 #ifdef CONFIG_SYS_I2C_IHS_CH1
 231 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
 232                          ihs_i2c_read, ihs_i2c_write,
 233                          ihs_i2c_set_bus_speed,
 234                          CONFIG_SYS_I2C_IHS_SPEED_1,
 235                          CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
 236 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 237 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
 238                          ihs_i2c_read, ihs_i2c_write,
 239                          ihs_i2c_set_bus_speed,
 240                          CONFIG_SYS_I2C_IHS_SPEED_1_1,
 241                          CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
 242 #endif
 243 #endif
 244 #ifdef CONFIG_SYS_I2C_IHS_CH2
 245 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
 246                          ihs_i2c_read, ihs_i2c_write,
 247                          ihs_i2c_set_bus_speed,
 248                          CONFIG_SYS_I2C_IHS_SPEED_2,
 249                          CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
 250 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 251 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
 252                          ihs_i2c_read, ihs_i2c_write,
 253                          ihs_i2c_set_bus_speed,
 254                          CONFIG_SYS_I2C_IHS_SPEED_2_1,
 255                          CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
 256 #endif
 257 #endif
 258 #ifdef CONFIG_SYS_I2C_IHS_CH3
 259 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
 260                          ihs_i2c_read, ihs_i2c_write,
 261                          ihs_i2c_set_bus_speed,
 262                          CONFIG_SYS_I2C_IHS_SPEED_3,
 263                          CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
 264 #ifdef CONFIG_SYS_I2C_IHS_DUAL
 265 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
 266                          ihs_i2c_read, ihs_i2c_write,
 267                          ihs_i2c_set_bus_speed,
 268                          CONFIG_SYS_I2C_IHS_SPEED_3_1,
 269                          CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
 270 #endif
 271 #endif