3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
5 * SPDX-License-Identifier: GPL-2.0+
13 #include "../misc/gdsys_soc.h"
15 #include <gdsys_fpga.h>
17 #include <asm/unaligned.h>
26 REG_INTERRUPT_STATUS = 0x00,
27 REG_INTERRUPT_ENABLE_CONTROL = 0x02,
28 REG_WRITE_MAILBOX_EXT = 0x04,
29 REG_WRITE_MAILBOX = 0x06,
30 REG_READ_MAILBOX_EXT = 0x08,
31 REG_READ_MAILBOX = 0x0A,
34 #else /* !CONFIG_DM_I2C */
35 DECLARE_GLOBAL_DATA_PTR;
37 #ifdef CONFIG_SYS_I2C_IHS_DUAL
39 #define I2C_SET_REG(fld, val) \
41 if (I2C_ADAP_HWNR & 0x10) \
42 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
44 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
47 #define I2C_SET_REG(fld, val) \
48 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
51 #ifdef CONFIG_SYS_I2C_IHS_DUAL
52 #define I2C_GET_REG(fld, val) \
54 if (I2C_ADAP_HWNR & 0x10) \
55 FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
57 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
60 #define I2C_GET_REG(fld, val) \
61 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
63 #endif /* CONFIG_DM_I2C */
66 I2CINT_ERROR_EV = BIT(13),
67 I2CINT_TRANSMIT_EV = BIT(14),
68 I2CINT_RECEIVE_EV = BIT(15),
73 I2CMB_WRITE = 1 << 10,
74 I2CMB_1BYTE = 0 << 11,
75 I2CMB_2BYTE = 1 << 11,
76 I2CMB_DONT_HOLD_BUS = 0 << 13,
77 I2CMB_HOLD_BUS = 1 << 13,
78 I2CMB_NATIVE = 2 << 14,
87 static int wait_for_int(struct udevice *dev, int read)
89 static int wait_for_int(bool read)
95 struct ihs_i2c_priv *priv = dev_get_priv(dev);
98 gdsys_soc_get_fpga(dev, &fpga);
102 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
105 I2C_GET_REG(interrupt_status, &val);
107 /* Wait until error or receive/transmit interrupt was raised */
108 while (!(val & (I2CINT_ERROR_EV
109 | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
114 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
117 I2C_GET_REG(interrupt_status, &val);
121 return (val & I2CINT_ERROR_EV) ? 1 : 0;
125 static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
126 uchar *buffer, int len, int read, bool is_last)
128 static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
135 struct ihs_i2c_priv *priv = dev_get_priv(dev);
136 struct udevice *fpga;
138 gdsys_soc_get_fpga(dev, &fpga);
141 /* Clear interrupt status */
142 data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
144 fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data,
146 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
149 I2C_SET_REG(interrupt_status, data);
150 I2C_GET_REG(interrupt_status, &val);
153 /* If we want to write and have data, write the bytes to the mailbox */
158 val |= buffer[1] << 8;
160 fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val,
163 I2C_SET_REG(write_mailbox_ext, val);
168 | (read ? 0 : I2CMB_WRITE)
170 | ((len > 1) ? I2CMB_2BYTE : 0)
171 | (is_last ? 0 : I2CMB_HOLD_BUS);
174 fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data,
177 I2C_SET_REG(write_mailbox, data);
181 if (wait_for_int(dev, read))
183 if (wait_for_int(read))
187 /* If we want to read, get the bytes from the mailbox */
190 fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val,
193 I2C_GET_REG(read_mailbox_ext, &val);
195 buffer[0] = val & 0xff;
197 buffer[1] = val >> 8;
204 static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
206 static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
211 int transfer = min(len, 2);
212 bool is_last = len <= transfer;
215 if (ihs_i2c_transfer(dev, chip, data, transfer, read,
216 hold_bus ? false : is_last))
219 if (ihs_i2c_transfer(chip, data, transfer, read,
220 hold_bus ? false : is_last))
232 static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
235 static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
239 return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
241 return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
246 static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
247 int alen, uchar *buffer, int len, int read)
249 static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
250 int alen, uchar *buffer, int len, int read)
253 /* Don't hold the bus if length of data to send/receive is zero */
255 if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len))
258 if (len <= 0 || ihs_i2c_address(chip, addr, alen, len))
263 return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
265 return ihs_i2c_send_buffer(chip, buffer, len, false, read);
271 int ihs_i2c_probe(struct udevice *bus)
273 struct ihs_i2c_priv *priv = dev_get_priv(bus);
276 addr = dev_read_u32_default(bus, "reg", -1);
283 static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
285 struct ihs_i2c_priv *priv = dev_get_priv(bus);
287 if (speed != priv->speed && priv->speed != 0)
295 static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
297 struct i2c_msg *dmsg, *omsg, dummy;
299 memset(&dummy, 0, sizeof(struct i2c_msg));
301 /* We expect either two messages (one with an offset and one with the
302 * actucal data) or one message (just data)
304 if (nmsgs > 2 || nmsgs == 0) {
305 debug("%s: Only one or two messages are supported.", __func__);
309 omsg = nmsgs == 1 ? &dummy : msg;
310 dmsg = nmsgs == 1 ? msg : msg + 1;
312 if (dmsg->flags & I2C_M_RD)
313 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
314 omsg->len, dmsg->buf, dmsg->len,
317 return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
318 omsg->len, dmsg->buf, dmsg->len,
322 static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
327 if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true))
333 static const struct dm_i2c_ops ihs_i2c_ops = {
334 .xfer = ihs_i2c_xfer,
335 .probe_chip = ihs_i2c_probe_chip,
336 .set_bus_speed = ihs_i2c_set_bus_speed,
339 static const struct udevice_id ihs_i2c_ids[] = {
340 { .compatible = "gdsys,ihs_i2cmaster", },
344 U_BOOT_DRIVER(i2c_ihs) = {
347 .of_match = ihs_i2c_ids,
348 .probe = ihs_i2c_probe,
349 .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
353 #else /* CONFIG_DM_I2C */
355 static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
357 #ifdef CONFIG_SYS_I2C_INIT_BOARD
359 * Call board specific i2c bus reset routine before accessing the
360 * environment, which might be in a chip on that bus. For details
361 * about this problem see doc/I2C_Edge_Conditions.
367 static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
371 if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true))
377 static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
378 int alen, uchar *buffer, int len)
382 put_unaligned_le32(addr, addr_bytes);
384 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
388 static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
389 int alen, uchar *buffer, int len)
393 put_unaligned_le32(addr, addr_bytes);
395 return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
399 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
402 if (speed != adap->speed)
408 * Register IHS i2c adapters
410 #ifdef CONFIG_SYS_I2C_IHS_CH0
411 U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
412 ihs_i2c_read, ihs_i2c_write,
413 ihs_i2c_set_bus_speed,
414 CONFIG_SYS_I2C_IHS_SPEED_0,
415 CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
416 #ifdef CONFIG_SYS_I2C_IHS_DUAL
417 U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
418 ihs_i2c_read, ihs_i2c_write,
419 ihs_i2c_set_bus_speed,
420 CONFIG_SYS_I2C_IHS_SPEED_0_1,
421 CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
424 #ifdef CONFIG_SYS_I2C_IHS_CH1
425 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
426 ihs_i2c_read, ihs_i2c_write,
427 ihs_i2c_set_bus_speed,
428 CONFIG_SYS_I2C_IHS_SPEED_1,
429 CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
430 #ifdef CONFIG_SYS_I2C_IHS_DUAL
431 U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
432 ihs_i2c_read, ihs_i2c_write,
433 ihs_i2c_set_bus_speed,
434 CONFIG_SYS_I2C_IHS_SPEED_1_1,
435 CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
438 #ifdef CONFIG_SYS_I2C_IHS_CH2
439 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
440 ihs_i2c_read, ihs_i2c_write,
441 ihs_i2c_set_bus_speed,
442 CONFIG_SYS_I2C_IHS_SPEED_2,
443 CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
444 #ifdef CONFIG_SYS_I2C_IHS_DUAL
445 U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
446 ihs_i2c_read, ihs_i2c_write,
447 ihs_i2c_set_bus_speed,
448 CONFIG_SYS_I2C_IHS_SPEED_2_1,
449 CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
452 #ifdef CONFIG_SYS_I2C_IHS_CH3
453 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
454 ihs_i2c_read, ihs_i2c_write,
455 ihs_i2c_set_bus_speed,
456 CONFIG_SYS_I2C_IHS_SPEED_3,
457 CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
458 #ifdef CONFIG_SYS_I2C_IHS_DUAL
459 U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
460 ihs_i2c_read, ihs_i2c_write,
461 ihs_i2c_set_bus_speed,
462 CONFIG_SYS_I2C_IHS_SPEED_3_1,
463 CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
466 #endif /* CONFIG_DM_I2C */