2 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 * This file is based on: drivers/i2c/zynq_i2c.c,
6 * with added driver-model support and code cleanup.
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/types.h>
14 #include <asm/errno.h>
15 #include <dm/device.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 /* i2c register set */
24 struct cdns_i2c_regs {
35 u32 interrupt_disable;
38 /* Control register fields */
39 #define CDNS_I2C_CONTROL_RW 0x00000001
40 #define CDNS_I2C_CONTROL_MS 0x00000002
41 #define CDNS_I2C_CONTROL_NEA 0x00000004
42 #define CDNS_I2C_CONTROL_ACKEN 0x00000008
43 #define CDNS_I2C_CONTROL_HOLD 0x00000010
44 #define CDNS_I2C_CONTROL_SLVMON 0x00000020
45 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
46 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
47 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
48 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
49 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
51 /* Status register values */
52 #define CDNS_I2C_STATUS_RXDV 0x00000020
53 #define CDNS_I2C_STATUS_TXDV 0x00000040
54 #define CDNS_I2C_STATUS_RXOVF 0x00000080
55 #define CDNS_I2C_STATUS_BA 0x00000100
57 /* Interrupt register fields */
58 #define CDNS_I2C_INTERRUPT_COMP 0x00000001
59 #define CDNS_I2C_INTERRUPT_DATA 0x00000002
60 #define CDNS_I2C_INTERRUPT_NACK 0x00000004
61 #define CDNS_I2C_INTERRUPT_TO 0x00000008
62 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
63 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
64 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
65 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
66 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
68 #define CDNS_I2C_FIFO_DEPTH 16
69 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
72 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
76 int_status = readl(&cdns_i2c->interrupt_status);
78 status = readl(&cdns_i2c->status);
79 if (int_status || status) {
81 if (int_status & CDNS_I2C_INTERRUPT_COMP)
83 if (int_status & CDNS_I2C_INTERRUPT_DATA)
85 if (int_status & CDNS_I2C_INTERRUPT_NACK)
87 if (int_status & CDNS_I2C_INTERRUPT_TO)
89 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
91 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
93 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
95 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
97 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
99 if (status & CDNS_I2C_STATUS_RXDV)
101 if (status & CDNS_I2C_STATUS_TXDV)
103 if (status & CDNS_I2C_STATUS_RXOVF)
105 if (status & CDNS_I2C_STATUS_BA)
107 debug("TS%d ", readl(&cdns_i2c->transfer_size));
113 struct i2c_cdns_bus {
115 struct cdns_i2c_regs __iomem *regs; /* register base */
119 /** cdns_i2c_probe() - Probe method
120 * @dev: udevice pointer
122 * DM callback called when device is probed
124 static int cdns_i2c_probe(struct udevice *dev)
126 struct i2c_cdns_bus *bus = dev_get_priv(dev);
128 /* TODO: Calculate dividers based on CPU_CLK_1X */
129 /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
130 writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
131 (2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
133 /* Enable master mode, ack, and 7-bit addressing */
134 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
135 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
137 debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
142 static int cdns_i2c_remove(struct udevice *dev)
144 struct i2c_cdns_bus *bus = dev_get_priv(dev);
146 debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
148 unmap_sysmem(bus->regs);
153 /* Wait for an interrupt */
154 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
156 int timeout, int_status;
158 for (timeout = 0; timeout < 100; timeout++) {
160 int_status = readl(&cdns_i2c->interrupt_status);
161 if (int_status & mask)
165 /* Clear interrupt status flags */
166 writel(int_status & mask, &cdns_i2c->interrupt_status);
168 return int_status & mask;
171 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
173 if (speed != 100000) {
174 printf("%s, failed to set clock speed to %u\n", __func__,
182 /* Probe to see if a chip is present. */
183 static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
186 struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
187 struct cdns_i2c_regs *regs = i2c_bus->regs;
189 /* Attempt to read a byte */
190 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
191 CDNS_I2C_CONTROL_RW);
192 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
193 writel(0xFF, ®s->interrupt_status);
194 writel(chip_addr, ®s->address);
195 writel(1, ®s->transfer_size);
197 return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
198 CDNS_I2C_INTERRUPT_NACK) &
199 CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
202 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
203 u32 len, bool next_is_read)
207 struct cdns_i2c_regs *regs = i2c_bus->regs;
209 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
210 CDNS_I2C_CONTROL_HOLD);
212 /* if next is a read, we need to clear HOLD, doesn't work */
214 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
216 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
218 writel(0xFF, ®s->interrupt_status);
219 writel(addr, ®s->address);
222 writel(*(cur_data++), ®s->data);
223 if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
224 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
225 /* Release the bus */
226 clrbits_le32(®s->control,
227 CDNS_I2C_CONTROL_HOLD);
233 /* All done... release the bus */
234 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
235 /* Wait for the address and data to be sent */
236 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
241 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
249 struct cdns_i2c_regs *regs = i2c_bus->regs;
251 /* Check the hardware can handle the requested bytes */
252 if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
255 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
256 CDNS_I2C_CONTROL_RW);
258 /* Start reading data */
259 writel(addr, ®s->address);
260 writel(len, ®s->transfer_size);
264 status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
265 CDNS_I2C_INTERRUPT_DATA);
267 /* Release the bus */
268 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
271 debug("Read %d bytes\n",
272 len - readl(®s->transfer_size));
273 for (; i < len - readl(®s->transfer_size); i++)
274 *(cur_data++) = readl(®s->data);
275 } while (readl(®s->transfer_size) != 0);
276 /* All done... release the bus */
277 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
280 cdns_i2c_debug_status(regs);
285 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
288 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
291 debug("i2c_xfer: %d messages\n", nmsgs);
292 for (; nmsgs > 0; nmsgs--, msg++) {
293 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
295 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
296 if (msg->flags & I2C_M_RD) {
297 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
300 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
301 msg->len, next_is_read);
304 debug("i2c_write: error sending\n");
312 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
314 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
316 i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
323 static const struct dm_i2c_ops cdns_i2c_ops = {
324 .xfer = cdns_i2c_xfer,
325 .probe_chip = cdns_i2c_probe_chip,
326 .set_bus_speed = cdns_i2c_set_bus_speed,
329 static const struct udevice_id cdns_i2c_of_match[] = {
330 { .compatible = "cdns,i2c-r1p10" },
331 { /* end of table */ }
334 U_BOOT_DRIVER(cdns_i2c) = {
337 .of_match = cdns_i2c_of_match,
338 .probe = cdns_i2c_probe,
339 .remove = cdns_i2c_remove,
340 .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
341 .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
342 .ops = &cdns_i2c_ops,