1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2006,2009 Freescale Semiconductor, Inc.
5 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Changes for multibus/multiadapter I2C support.
11 #include <i2c.h> /* Functional interface */
15 #include <asm/fsl_i2c.h> /* HW definitions */
20 /* The maximum number of microseconds we will wait until another master has
21 * released the bus. If not defined in the board header file, then use a
24 #ifndef CONFIG_I2C_MBB_TIMEOUT
25 #define CONFIG_I2C_MBB_TIMEOUT 100000
28 /* The maximum number of microseconds we will wait for a read or write
29 * operation to complete. If not defined in the board header file, then use a
32 #ifndef CONFIG_I2C_TIMEOUT
33 #define CONFIG_I2C_TIMEOUT 100000
36 #define I2C_READ_BIT 1
37 #define I2C_WRITE_BIT 0
39 DECLARE_GLOBAL_DATA_PTR;
42 static const struct fsl_i2c_base *i2c_base[4] = {
43 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
44 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
45 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
47 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
48 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
50 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
51 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
56 /* I2C speed map for a DFSR value of 1 */
60 * Map I2C frequency dividers to FDR and DFSR values
62 * This structure is used to define the elements of a table that maps I2C
63 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
64 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
65 * Sampling Rate (DFSR) registers.
67 * The actual table should be defined in the board file, and it must be called
68 * fsl_i2c_speed_map[].
70 * The last entry of the table must have a value of {-1, X}, where X is same
71 * FDR/DFSR values as the second-to-last entry. This guarantees that any
72 * search through the array will always find a match.
74 * The values of the divider must be in increasing numerical order, i.e.
75 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
77 * For this table, the values are based on a value of 1 for the DFSR
78 * register. See the application note AN2919 "Determining the I2C Frequency
79 * Divider Ratio for SCL"
81 * ColdFire I2C frequency dividers for FDR values are different from
82 * PowerPC. The protocol to use the I2C module is still the same.
83 * A different table is defined and are based on MCF5xxx user manual.
87 unsigned short divider;
89 } fsl_i2c_speed_map[] = {
90 {20, 32}, {22, 33}, {24, 34}, {26, 35},
91 {28, 0}, {28, 36}, {30, 1}, {32, 37},
92 {34, 2}, {36, 38}, {40, 3}, {40, 39},
93 {44, 4}, {48, 5}, {48, 40}, {56, 6},
94 {56, 41}, {64, 42}, {68, 7}, {72, 43},
95 {80, 8}, {80, 44}, {88, 9}, {96, 41},
96 {104, 10}, {112, 42}, {128, 11}, {128, 43},
97 {144, 12}, {160, 13}, {160, 48}, {192, 14},
98 {192, 49}, {224, 50}, {240, 15}, {256, 51},
99 {288, 16}, {320, 17}, {320, 52}, {384, 18},
100 {384, 53}, {448, 54}, {480, 19}, {512, 55},
101 {576, 20}, {640, 21}, {640, 56}, {768, 22},
102 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
103 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
104 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
105 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
111 * Set the I2C bus speed for a given I2C device
113 * @param base: the I2C device registers
114 * @i2c_clk: I2C bus clock frequency
115 * @speed: the desired speed of the bus
117 * The I2C device must be stopped before calling this function.
119 * The return value is the actual bus speed that is set.
121 static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
122 uint i2c_clk, uint speed)
124 ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
127 * We want to choose an FDR/DFSR that generates an I2C bus speed that
128 * is equal to or lower than the requested speed. That means that we
129 * want the first divider that is equal to or greater than the
130 * calculated divider.
133 u8 dfsr, fdr = 0x31; /* Default if no FDR found */
134 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
136 ulong c_div, est_div;
138 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
139 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
141 /* Condition 1: dfsr <= 50/T */
142 dfsr = (5 * (i2c_clk / 1000)) / 100000;
144 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
145 fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
146 speed = i2c_clk / divider; /* Fake something */
148 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
153 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
154 for (gb = 0; gb < 8; gb++) {
156 c_div = b * (a + ((3 * dfsr) / b) * 2);
157 if (c_div > divider && c_div < est_div) {
158 ushort bin_gb, bin_ga;
162 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
163 fdr = bin_gb | bin_ga;
164 speed = i2c_clk / est_div;
166 debug("FDR: 0x%.2x, ", fdr);
167 debug("div: %ld, ", est_div);
168 debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
169 debug("a: %d, b: %d, speed: %d\n", a, b, speed);
171 /* Condition 2 not accounted for */
172 debug("Tr <= %d ns\n",
173 (b - 3 * dfsr) * 1000000 /
182 debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
183 debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
185 writeb(dfsr, &base->dfsrr); /* set default filter */
186 writeb(fdr, &base->fdr); /* set bus speed */
190 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
191 if (fsl_i2c_speed_map[i].divider >= divider) {
194 fdr = fsl_i2c_speed_map[i].fdr;
195 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
196 writeb(fdr, &base->fdr); /* set bus speed */
204 #ifndef CONFIG_DM_I2C
205 static uint get_i2c_clock(int bus)
208 return gd->arch.i2c2_clk; /* I2C2 clock */
210 return gd->arch.i2c1_clk; /* I2C1 clock */
214 static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
216 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
217 unsigned long long timeval = 0;
221 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
222 uint svr = get_svr();
224 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
225 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
229 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
231 timeval = get_ticks();
232 while (!(readb(&base->sr) & I2C_SR_MBB)) {
233 if ((get_ticks() - timeval) > timeout)
237 if (readb(&base->sr) & I2C_SR_MAL) {
238 /* SDA is stuck low */
239 writeb(0, &base->cr);
241 writeb(I2C_CR_MSTA | flags, &base->cr);
242 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
247 timeval = get_ticks();
248 while (!(readb(&base->sr) & I2C_SR_MIF)) {
249 if ((get_ticks() - timeval) > timeout)
255 writeb(I2C_CR_MEN | flags, &base->cr);
256 writeb(0, &base->sr);
262 static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
263 slaveadd, int i2c_clk, int busnum)
265 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
266 unsigned long long timeval;
268 #ifdef CONFIG_SYS_I2C_INIT_BOARD
269 /* Call board specific i2c bus reset routine before accessing the
270 * environment, which might be in a chip on that bus. For details
271 * about this problem see doc/I2C_Edge_Conditions.
275 writeb(0, &base->cr); /* stop I2C controller */
276 udelay(5); /* let it shutdown in peace */
277 set_i2c_bus_speed(base, i2c_clk, speed);
278 writeb(slaveadd << 1, &base->adr);/* write slave address */
279 writeb(0x0, &base->sr); /* clear status register */
280 writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
282 timeval = get_ticks();
283 while (readb(&base->sr) & I2C_SR_MBB) {
284 if ((get_ticks() - timeval) < timeout)
287 if (fsl_i2c_fixup(base))
288 debug("i2c_init: BUS#%d failed to init\n",
295 static int i2c_wait4bus(const struct fsl_i2c_base *base)
297 unsigned long long timeval = get_ticks();
298 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
300 while (readb(&base->sr) & I2C_SR_MBB) {
301 if ((get_ticks() - timeval) > timeout)
308 static int i2c_wait(const struct fsl_i2c_base *base, int write)
311 unsigned long long timeval = get_ticks();
312 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
315 csr = readb(&base->sr);
316 if (!(csr & I2C_SR_MIF))
318 /* Read again to allow register to stabilise */
319 csr = readb(&base->sr);
321 writeb(0x0, &base->sr);
323 if (csr & I2C_SR_MAL) {
324 debug("%s: MAL\n", __func__);
328 if (!(csr & I2C_SR_MCF)) {
329 debug("%s: unfinished\n", __func__);
333 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
334 debug("%s: No RXACK\n", __func__);
339 } while ((get_ticks() - timeval) < timeout);
341 debug("%s: timed out\n", __func__);
345 static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
348 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
349 | (rsta ? I2C_CR_RSTA : 0),
352 writeb((dev << 1) | dir, &base->dr);
354 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
360 static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
365 for (i = 0; i < length; i++) {
366 writeb(data[i], &base->dr);
368 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
375 static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
380 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
386 for (i = 0; i < length; i++) {
387 if (i2c_wait(base, I2C_READ_BIT) < 0)
390 /* Generate ack on last next to last byte */
392 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
395 /* Do not generate stop on last byte */
397 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
400 data[i] = readb(&base->dr);
406 static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
407 int olen, u8 *data, int dlen)
409 int ret = -1; /* signal error */
411 if (i2c_wait4bus(base) < 0)
414 /* Some drivers use offset lengths in excess of 4 bytes. These drivers
415 * adhere to the following convention:
416 * - the offset length is passed as negative (that is, the absolute
417 * value of olen is the actual offset length)
418 * - the offset itself is passed in data, which is overwritten by the
419 * subsequent read operation
422 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
423 ret = __i2c_write_data(base, data, -olen);
428 if (dlen && i2c_write_addr(base, chip_addr,
429 I2C_READ_BIT, 1) != 0)
430 ret = __i2c_read_data(base, data, dlen);
432 if ((!dlen || olen > 0) &&
433 i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
434 __i2c_write_data(base, offset, olen) == olen)
435 ret = 0; /* No error so far */
437 if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
439 ret = __i2c_read_data(base, data, dlen);
442 writeb(I2C_CR_MEN, &base->cr);
444 if (i2c_wait4bus(base)) /* Wait until STOP */
445 debug("i2c_read: wait4bus timed out\n");
453 static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
454 u8 *offset, int olen, u8 *data, int dlen)
456 int ret = -1; /* signal error */
458 if (i2c_wait4bus(base) < 0)
461 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
462 __i2c_write_data(base, offset, olen) == olen) {
463 ret = __i2c_write_data(base, data, dlen);
466 writeb(I2C_CR_MEN, &base->cr);
467 if (i2c_wait4bus(base)) /* Wait until STOP */
468 debug("i2c_write: wait4bus timed out\n");
476 static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
478 /* For unknown reason the controller will ACK when
479 * probing for a slave with the same address, so skip
482 if (chip == (readb(&base->adr) >> 1))
485 return __i2c_read(base, chip, 0, 0, NULL, 0);
488 static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
489 uint speed, int i2c_clk)
491 writeb(0, &base->cr); /* stop controller */
492 set_i2c_bus_speed(base, i2c_clk, speed);
493 writeb(I2C_CR_MEN, &base->cr); /* start controller */
498 #ifndef CONFIG_DM_I2C
499 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
501 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
502 get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
505 static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
507 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
510 static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
511 int olen, u8 *data, int dlen)
513 u8 *o = (u8 *)&offset;
515 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
519 static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
520 int olen, u8 *data, int dlen)
522 u8 *o = (u8 *)&offset;
524 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
528 static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
530 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
531 get_i2c_clock(adap->hwadapnr));
535 * Register fsl i2c adapters
537 U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
538 fsl_i2c_write, fsl_i2c_set_bus_speed,
539 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
541 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
542 U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
543 fsl_i2c_write, fsl_i2c_set_bus_speed,
544 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
547 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
548 U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
549 fsl_i2c_write, fsl_i2c_set_bus_speed,
550 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
553 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
554 U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
555 fsl_i2c_write, fsl_i2c_set_bus_speed,
556 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
559 #else /* CONFIG_DM_I2C */
560 static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
563 struct fsl_i2c_dev *dev = dev_get_priv(bus);
565 return __i2c_probe_chip(dev->base, chip_addr);
568 static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
570 struct fsl_i2c_dev *dev = dev_get_priv(bus);
572 return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
575 static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
577 struct fsl_i2c_dev *dev = dev_get_priv(bus);
580 dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
585 dev->index = dev_read_u32_default(bus, "cell-index", -1);
586 dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
588 dev->speed = dev_read_u32_default(bus, "clock-frequency",
589 I2C_SPEED_FAST_RATE);
591 if (!clk_get_by_index(bus, 0, &clock))
592 dev->i2c_clk = clk_get_rate(&clock);
594 dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
600 static int fsl_i2c_probe(struct udevice *bus)
602 struct fsl_i2c_dev *dev = dev_get_priv(bus);
604 __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
609 static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
611 struct fsl_i2c_dev *dev = dev_get_priv(bus);
612 struct i2c_msg *dmsg, *omsg, dummy;
614 memset(&dummy, 0, sizeof(struct i2c_msg));
616 /* We expect either two messages (one with an offset and one with the
617 * actual data) or one message (just data)
619 if (nmsgs > 2 || nmsgs == 0) {
620 debug("%s: Only one or two messages are supported.", __func__);
624 omsg = nmsgs == 1 ? &dummy : msg;
625 dmsg = nmsgs == 1 ? msg : msg + 1;
627 if (dmsg->flags & I2C_M_RD)
628 return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
629 dmsg->buf, dmsg->len);
631 return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
632 dmsg->buf, dmsg->len);
635 static const struct dm_i2c_ops fsl_i2c_ops = {
636 .xfer = fsl_i2c_xfer,
637 .probe_chip = fsl_i2c_probe_chip,
638 .set_bus_speed = fsl_i2c_set_bus_speed,
641 static const struct udevice_id fsl_i2c_ids[] = {
642 { .compatible = "fsl-i2c", },
646 U_BOOT_DRIVER(i2c_fsl) = {
649 .of_match = fsl_i2c_ids,
650 .probe = fsl_i2c_probe,
651 .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
652 .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
656 #endif /* CONFIG_DM_I2C */