2 * Copyright 2006 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifdef CONFIG_HARD_I2C
24 #include <i2c.h> /* Functional interface */
27 #include <asm/fsl_i2c.h> /* HW definitions */
29 #define I2C_TIMEOUT (CONFIG_SYS_HZ / 4)
31 #define I2C_READ_BIT 1
32 #define I2C_WRITE_BIT 0
34 DECLARE_GLOBAL_DATA_PTR;
36 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
37 * Default is bus 0. This is necessary because the DDR initialization
38 * runs from ROM, and we can't switch buses because we can't modify
39 * the global variables.
41 #ifndef CONFIG_SYS_SPD_BUS_NUM
42 #define CONFIG_SYS_SPD_BUS_NUM 0
44 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
45 #if defined(CONFIG_I2C_MUX)
46 static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
49 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};
51 static const struct fsl_i2c *i2c_dev[2] = {
52 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET),
53 #ifdef CONFIG_SYS_I2C2_OFFSET
54 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET)
58 /* I2C speed map for a DFSR value of 1 */
61 * Map I2C frequency dividers to FDR and DFSR values
63 * This structure is used to define the elements of a table that maps I2C
64 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
65 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
66 * Sampling Rate (DFSR) registers.
68 * The actual table should be defined in the board file, and it must be called
69 * fsl_i2c_speed_map[].
71 * The last entry of the table must have a value of {-1, X}, where X is same
72 * FDR/DFSR values as the second-to-last entry. This guarantees that any
73 * search through the array will always find a match.
75 * The values of the divider must be in increasing numerical order, i.e.
76 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
78 * For this table, the values are based on a value of 1 for the DFSR
79 * register. See the application note AN2919 "Determining the I2C Frequency
80 * Divider Ratio for SCL"
82 * ColdFire I2C frequency dividers for FDR values are different from
83 * PowerPC. The protocol to use the I2C module is still the same.
84 * A different table is defined and are based on MCF5xxx user manual.
88 unsigned short divider;
93 } fsl_i2c_speed_map[] = {
95 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35},
96 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2},
97 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4},
98 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3},
99 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7},
100 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9},
101 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46},
102 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12},
103 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14},
104 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16},
105 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19},
106 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22},
107 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24},
108 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27},
109 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30},
110 {61440, 1, 31}, {-1, 1, 31}
111 #elif defined(__M68K__)
112 {20, 32}, {22, 33}, {24, 34}, {26, 35},
113 {28, 0}, {28, 36}, {30, 1}, {32, 37},
114 {34, 2}, {36, 38}, {40, 3}, {40, 39},
115 {44, 4}, {48, 5}, {48, 40}, {56, 6},
116 {56, 41}, {64, 42}, {68, 7}, {72, 43},
117 {80, 8}, {80, 44}, {88, 9}, {96, 41},
118 {104, 10}, {112, 42}, {128, 11}, {128, 43},
119 {144, 12}, {160, 13}, {160, 48}, {192, 14},
120 {192, 49}, {224, 50}, {240, 15}, {256, 51},
121 {288, 16}, {320, 17}, {320, 52}, {384, 18},
122 {384, 53}, {448, 54}, {480, 19}, {512, 55},
123 {576, 20}, {640, 21}, {640, 56}, {768, 22},
124 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
125 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
126 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
127 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
133 * Set the I2C bus speed for a given I2C device
135 * @param dev: the I2C device
136 * @i2c_clk: I2C bus clock frequency
137 * @speed: the desired speed of the bus
139 * The I2C device must be stopped before calling this function.
141 * The return value is the actual bus speed that is set.
143 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
144 unsigned int i2c_clk, unsigned int speed)
146 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
150 * We want to choose an FDR/DFSR that generates an I2C bus speed that
151 * is equal to or lower than the requested speed. That means that we
152 * want the first divider that is equal to or greater than the
153 * calculated divider.
156 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
157 if (fsl_i2c_speed_map[i].divider >= divider) {
161 dfsr = fsl_i2c_speed_map[i].dfsr;
163 fdr = fsl_i2c_speed_map[i].fdr;
164 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
165 writeb(fdr, &dev->fdr); /* set bus speed */
167 writeb(dfsr, &dev->dfsrr); /* set default filter */
176 i2c_init(int speed, int slaveadd)
181 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
183 writeb(0, &dev->cr); /* stop I2C controller */
184 udelay(5); /* let it shutdown in peace */
185 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
186 if (gd->flags & GD_FLG_RELOC)
187 i2c_bus_speed[0] = temp;
188 writeb(slaveadd << 1, &dev->adr); /* write slave address */
189 writeb(0x0, &dev->sr); /* clear status register */
190 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
192 #ifdef CONFIG_SYS_I2C2_OFFSET
193 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET);
195 writeb(0, &dev->cr); /* stop I2C controller */
196 udelay(5); /* let it shutdown in peace */
197 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
198 if (gd->flags & GD_FLG_RELOC)
199 i2c_bus_speed[1] = temp;
200 writeb(slaveadd << 1, &dev->adr); /* write slave address */
201 writeb(0x0, &dev->sr); /* clear status register */
202 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
206 static __inline__ int
209 unsigned long long timeval = get_ticks();
211 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
212 if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT))
219 static __inline__ int
223 unsigned long long timeval = get_ticks();
226 csr = readb(&i2c_dev[i2c_bus_num]->sr);
227 if (!(csr & I2C_SR_MIF))
230 writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
232 if (csr & I2C_SR_MAL) {
233 debug("i2c_wait: MAL\n");
237 if (!(csr & I2C_SR_MCF)) {
238 debug("i2c_wait: unfinished\n");
242 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
243 debug("i2c_wait: No RXACK\n");
248 } while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT));
250 debug("i2c_wait: timed out\n");
254 static __inline__ int
255 i2c_write_addr (u8 dev, u8 dir, int rsta)
257 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
258 | (rsta ? I2C_CR_RSTA : 0),
259 &i2c_dev[i2c_bus_num]->cr);
261 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
263 if (i2c_wait(I2C_WRITE_BIT) < 0)
269 static __inline__ int
270 __i2c_write(u8 *data, int length)
274 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
275 &i2c_dev[i2c_bus_num]->cr);
277 for (i = 0; i < length; i++) {
278 writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
280 if (i2c_wait(I2C_WRITE_BIT) < 0)
287 static __inline__ int
288 __i2c_read(u8 *data, int length)
292 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
293 &i2c_dev[i2c_bus_num]->cr);
296 readb(&i2c_dev[i2c_bus_num]->dr);
298 for (i = 0; i < length; i++) {
299 if (i2c_wait(I2C_READ_BIT) < 0)
302 /* Generate ack on last next to last byte */
304 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
305 &i2c_dev[i2c_bus_num]->cr);
307 /* Generate stop on last byte */
309 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
311 data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
318 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
320 int i = -1; /* signal error */
323 if (i2c_wait4bus() >= 0
324 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
325 && __i2c_write(&a[4 - alen], alen) == alen)
326 i = 0; /* No error so far */
329 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
330 i = __i2c_read(data, length);
332 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
341 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
343 int i = -1; /* signal error */
346 if (i2c_wait4bus() >= 0
347 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
348 && __i2c_write(&a[4 - alen], alen) == alen) {
349 i = __i2c_write(data, length);
352 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
361 i2c_probe(uchar chip)
363 /* For unknow reason the controller will ACK when
364 * probing for a slave with the same address, so skip
367 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
370 return i2c_read(chip, 0, 0, NULL, 0);
373 int i2c_set_bus_num(unsigned int bus)
375 #if defined(CONFIG_I2C_MUX)
376 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
381 ret = i2x_mux_select_mux(bus);
386 i2c_bus_num_mux = bus;
388 #ifdef CONFIG_SYS_I2C2_OFFSET
401 int i2c_set_bus_speed(unsigned int speed)
403 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
405 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
406 i2c_bus_speed[i2c_bus_num] =
407 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
408 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
413 unsigned int i2c_get_bus_num(void)
415 #if defined(CONFIG_I2C_MUX)
416 return i2c_bus_num_mux;
422 unsigned int i2c_get_bus_speed(void)
424 return i2c_bus_speed[i2c_bus_num];
427 #endif /* CONFIG_HARD_I2C */