1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2006,2009 Freescale Semiconductor, Inc.
5 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Changes for multibus/multiadapter I2C support.
11 #include <i2c.h> /* Functional interface */
14 #include <asm/fsl_i2c.h> /* HW definitions */
19 /* The maximum number of microseconds we will wait until another master has
20 * released the bus. If not defined in the board header file, then use a
23 #ifndef CONFIG_I2C_MBB_TIMEOUT
24 #define CONFIG_I2C_MBB_TIMEOUT 100000
27 /* The maximum number of microseconds we will wait for a read or write
28 * operation to complete. If not defined in the board header file, then use a
31 #ifndef CONFIG_I2C_TIMEOUT
32 #define CONFIG_I2C_TIMEOUT 100000
35 #define I2C_READ_BIT 1
36 #define I2C_WRITE_BIT 0
38 DECLARE_GLOBAL_DATA_PTR;
41 static const struct fsl_i2c_base *i2c_base[4] = {
42 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
43 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
44 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
46 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
47 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
49 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
50 (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
55 /* I2C speed map for a DFSR value of 1 */
59 * Map I2C frequency dividers to FDR and DFSR values
61 * This structure is used to define the elements of a table that maps I2C
62 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
63 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
64 * Sampling Rate (DFSR) registers.
66 * The actual table should be defined in the board file, and it must be called
67 * fsl_i2c_speed_map[].
69 * The last entry of the table must have a value of {-1, X}, where X is same
70 * FDR/DFSR values as the second-to-last entry. This guarantees that any
71 * search through the array will always find a match.
73 * The values of the divider must be in increasing numerical order, i.e.
74 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
76 * For this table, the values are based on a value of 1 for the DFSR
77 * register. See the application note AN2919 "Determining the I2C Frequency
78 * Divider Ratio for SCL"
80 * ColdFire I2C frequency dividers for FDR values are different from
81 * PowerPC. The protocol to use the I2C module is still the same.
82 * A different table is defined and are based on MCF5xxx user manual.
86 unsigned short divider;
88 } fsl_i2c_speed_map[] = {
89 {20, 32}, {22, 33}, {24, 34}, {26, 35},
90 {28, 0}, {28, 36}, {30, 1}, {32, 37},
91 {34, 2}, {36, 38}, {40, 3}, {40, 39},
92 {44, 4}, {48, 5}, {48, 40}, {56, 6},
93 {56, 41}, {64, 42}, {68, 7}, {72, 43},
94 {80, 8}, {80, 44}, {88, 9}, {96, 41},
95 {104, 10}, {112, 42}, {128, 11}, {128, 43},
96 {144, 12}, {160, 13}, {160, 48}, {192, 14},
97 {192, 49}, {224, 50}, {240, 15}, {256, 51},
98 {288, 16}, {320, 17}, {320, 52}, {384, 18},
99 {384, 53}, {448, 54}, {480, 19}, {512, 55},
100 {576, 20}, {640, 21}, {640, 56}, {768, 22},
101 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
102 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
103 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
104 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
110 * Set the I2C bus speed for a given I2C device
112 * @param base: the I2C device registers
113 * @i2c_clk: I2C bus clock frequency
114 * @speed: the desired speed of the bus
116 * The I2C device must be stopped before calling this function.
118 * The return value is the actual bus speed that is set.
120 static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
121 uint i2c_clk, uint speed)
123 ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
126 * We want to choose an FDR/DFSR that generates an I2C bus speed that
127 * is equal to or lower than the requested speed. That means that we
128 * want the first divider that is equal to or greater than the
129 * calculated divider.
132 u8 dfsr, fdr = 0x31; /* Default if no FDR found */
133 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
135 ulong c_div, est_div;
137 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
138 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
140 /* Condition 1: dfsr <= 50/T */
141 dfsr = (5 * (i2c_clk / 1000)) / 100000;
143 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
144 fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
145 speed = i2c_clk / divider; /* Fake something */
147 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
152 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
153 for (gb = 0; gb < 8; gb++) {
155 c_div = b * (a + ((3 * dfsr) / b) * 2);
156 if (c_div > divider && c_div < est_div) {
157 ushort bin_gb, bin_ga;
161 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
162 fdr = bin_gb | bin_ga;
163 speed = i2c_clk / est_div;
165 debug("FDR: 0x%.2x, ", fdr);
166 debug("div: %ld, ", est_div);
167 debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
168 debug("a: %d, b: %d, speed: %d\n", a, b, speed);
170 /* Condition 2 not accounted for */
171 debug("Tr <= %d ns\n",
172 (b - 3 * dfsr) * 1000000 /
181 debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
182 debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
184 writeb(dfsr, &base->dfsrr); /* set default filter */
185 writeb(fdr, &base->fdr); /* set bus speed */
189 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
190 if (fsl_i2c_speed_map[i].divider >= divider) {
193 fdr = fsl_i2c_speed_map[i].fdr;
194 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
195 writeb(fdr, &base->fdr); /* set bus speed */
203 #ifndef CONFIG_DM_I2C
204 static uint get_i2c_clock(int bus)
207 return gd->arch.i2c2_clk; /* I2C2 clock */
209 return gd->arch.i2c1_clk; /* I2C1 clock */
213 static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
215 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
216 unsigned long long timeval = 0;
220 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
221 uint svr = get_svr();
223 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
224 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
228 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
230 timeval = get_ticks();
231 while (!(readb(&base->sr) & I2C_SR_MBB)) {
232 if ((get_ticks() - timeval) > timeout)
236 if (readb(&base->sr) & I2C_SR_MAL) {
237 /* SDA is stuck low */
238 writeb(0, &base->cr);
240 writeb(I2C_CR_MSTA | flags, &base->cr);
241 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
246 timeval = get_ticks();
247 while (!(readb(&base->sr) & I2C_SR_MIF)) {
248 if ((get_ticks() - timeval) > timeout)
254 writeb(I2C_CR_MEN | flags, &base->cr);
255 writeb(0, &base->sr);
261 static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
262 slaveadd, int i2c_clk, int busnum)
264 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
265 unsigned long long timeval;
267 #ifdef CONFIG_SYS_I2C_INIT_BOARD
268 /* Call board specific i2c bus reset routine before accessing the
269 * environment, which might be in a chip on that bus. For details
270 * about this problem see doc/I2C_Edge_Conditions.
274 writeb(0, &base->cr); /* stop I2C controller */
275 udelay(5); /* let it shutdown in peace */
276 set_i2c_bus_speed(base, i2c_clk, speed);
277 writeb(slaveadd << 1, &base->adr);/* write slave address */
278 writeb(0x0, &base->sr); /* clear status register */
279 writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
281 timeval = get_ticks();
282 while (readb(&base->sr) & I2C_SR_MBB) {
283 if ((get_ticks() - timeval) < timeout)
286 if (fsl_i2c_fixup(base))
287 debug("i2c_init: BUS#%d failed to init\n",
294 static int i2c_wait4bus(const struct fsl_i2c_base *base)
296 unsigned long long timeval = get_ticks();
297 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
299 while (readb(&base->sr) & I2C_SR_MBB) {
300 if ((get_ticks() - timeval) > timeout)
307 static int i2c_wait(const struct fsl_i2c_base *base, int write)
310 unsigned long long timeval = get_ticks();
311 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
314 csr = readb(&base->sr);
315 if (!(csr & I2C_SR_MIF))
317 /* Read again to allow register to stabilise */
318 csr = readb(&base->sr);
320 writeb(0x0, &base->sr);
322 if (csr & I2C_SR_MAL) {
323 debug("%s: MAL\n", __func__);
327 if (!(csr & I2C_SR_MCF)) {
328 debug("%s: unfinished\n", __func__);
332 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
333 debug("%s: No RXACK\n", __func__);
338 } while ((get_ticks() - timeval) < timeout);
340 debug("%s: timed out\n", __func__);
344 static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
347 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
348 | (rsta ? I2C_CR_RSTA : 0),
351 writeb((dev << 1) | dir, &base->dr);
353 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
359 static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
364 for (i = 0; i < length; i++) {
365 writeb(data[i], &base->dr);
367 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
374 static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
379 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
385 for (i = 0; i < length; i++) {
386 if (i2c_wait(base, I2C_READ_BIT) < 0)
389 /* Generate ack on last next to last byte */
391 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
394 /* Do not generate stop on last byte */
396 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
399 data[i] = readb(&base->dr);
405 static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
406 int olen, u8 *data, int dlen)
408 int ret = -1; /* signal error */
410 if (i2c_wait4bus(base) < 0)
413 /* Some drivers use offset lengths in excess of 4 bytes. These drivers
414 * adhere to the following convention:
415 * - the offset length is passed as negative (that is, the absolute
416 * value of olen is the actual offset length)
417 * - the offset itself is passed in data, which is overwritten by the
418 * subsequent read operation
421 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
422 ret = __i2c_write_data(base, data, -olen);
427 if (dlen && i2c_write_addr(base, chip_addr,
428 I2C_READ_BIT, 1) != 0)
429 ret = __i2c_read_data(base, data, dlen);
431 if ((!dlen || olen > 0) &&
432 i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
433 __i2c_write_data(base, offset, olen) == olen)
434 ret = 0; /* No error so far */
436 if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
438 ret = __i2c_read_data(base, data, dlen);
441 writeb(I2C_CR_MEN, &base->cr);
443 if (i2c_wait4bus(base)) /* Wait until STOP */
444 debug("i2c_read: wait4bus timed out\n");
452 static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
453 u8 *offset, int olen, u8 *data, int dlen)
455 int ret = -1; /* signal error */
457 if (i2c_wait4bus(base) < 0)
460 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
461 __i2c_write_data(base, offset, olen) == olen) {
462 ret = __i2c_write_data(base, data, dlen);
465 writeb(I2C_CR_MEN, &base->cr);
466 if (i2c_wait4bus(base)) /* Wait until STOP */
467 debug("i2c_write: wait4bus timed out\n");
475 static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
477 /* For unknown reason the controller will ACK when
478 * probing for a slave with the same address, so skip
481 if (chip == (readb(&base->adr) >> 1))
484 return __i2c_read(base, chip, 0, 0, NULL, 0);
487 static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
488 uint speed, int i2c_clk)
490 writeb(0, &base->cr); /* stop controller */
491 set_i2c_bus_speed(base, i2c_clk, speed);
492 writeb(I2C_CR_MEN, &base->cr); /* start controller */
497 #ifndef CONFIG_DM_I2C
498 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
500 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
501 get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
504 static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
506 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
509 static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
510 int olen, u8 *data, int dlen)
512 u8 *o = (u8 *)&offset;
514 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
518 static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
519 int olen, u8 *data, int dlen)
521 u8 *o = (u8 *)&offset;
523 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
527 static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
529 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
530 get_i2c_clock(adap->hwadapnr));
534 * Register fsl i2c adapters
536 U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
537 fsl_i2c_write, fsl_i2c_set_bus_speed,
538 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
540 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
541 U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
542 fsl_i2c_write, fsl_i2c_set_bus_speed,
543 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
546 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
547 U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
548 fsl_i2c_write, fsl_i2c_set_bus_speed,
549 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
552 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
553 U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
554 fsl_i2c_write, fsl_i2c_set_bus_speed,
555 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
558 #else /* CONFIG_DM_I2C */
559 static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
562 struct fsl_i2c_dev *dev = dev_get_priv(bus);
564 return __i2c_probe_chip(dev->base, chip_addr);
567 static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
569 struct fsl_i2c_dev *dev = dev_get_priv(bus);
571 return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
574 static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
576 struct fsl_i2c_dev *dev = dev_get_priv(bus);
579 dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
584 dev->index = dev_read_u32_default(bus, "cell-index", -1);
585 dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
587 dev->speed = dev_read_u32_default(bus, "clock-frequency",
588 I2C_SPEED_FAST_RATE);
590 if (!clk_get_by_index(bus, 0, &clock))
591 dev->i2c_clk = clk_get_rate(&clock);
593 dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
599 static int fsl_i2c_probe(struct udevice *bus)
601 struct fsl_i2c_dev *dev = dev_get_priv(bus);
603 __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
608 static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
610 struct fsl_i2c_dev *dev = dev_get_priv(bus);
611 struct i2c_msg *dmsg, *omsg, dummy;
613 memset(&dummy, 0, sizeof(struct i2c_msg));
615 /* We expect either two messages (one with an offset and one with the
616 * actual data) or one message (just data)
618 if (nmsgs > 2 || nmsgs == 0) {
619 debug("%s: Only one or two messages are supported.", __func__);
623 omsg = nmsgs == 1 ? &dummy : msg;
624 dmsg = nmsgs == 1 ? msg : msg + 1;
626 if (dmsg->flags & I2C_M_RD)
627 return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
628 dmsg->buf, dmsg->len);
630 return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
631 dmsg->buf, dmsg->len);
634 static const struct dm_i2c_ops fsl_i2c_ops = {
635 .xfer = fsl_i2c_xfer,
636 .probe_chip = fsl_i2c_probe_chip,
637 .set_bus_speed = fsl_i2c_set_bus_speed,
640 static const struct udevice_id fsl_i2c_ids[] = {
641 { .compatible = "fsl-i2c", },
645 U_BOOT_DRIVER(i2c_fsl) = {
648 .of_match = fsl_i2c_ids,
649 .probe = fsl_i2c_probe,
650 .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
651 .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
655 #endif /* CONFIG_DM_I2C */