drivers/i2c/designware_i2c_pci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  * Copyright 2019 Google Inc
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <spl.h>
  11 #include <asm/lpss.h>
  12 #include "designware_i2c.h"
  13
  14 enum {
  15         VANILLA         = 0,    /* standard I2C with no tweaks */
  16         INTEL_APL,              /* Apollo Lake I2C */
  17 };
  18
  19 /* BayTrail HCNT/LCNT/SDA hold time */
  20 static struct dw_scl_sda_cfg byt_config = {
  21         .ss_hcnt = 0x200,
  22         .fs_hcnt = 0x55,
  23         .ss_lcnt = 0x200,
  24         .fs_lcnt = 0x99,
  25         .sda_hold = 0x6,
  26 };
  27
  28 /* Have a weak function for now - possibly should be a new uclass */
  29 __weak void lpss_reset_release(void *regs);
  30
  31 static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
  32 {
  33         struct dw_i2c *priv = dev_get_priv(dev);
  34
  35         if (spl_phase() < PHASE_SPL) {
  36                 u32 base;
  37                 int ret;
  38
  39                 ret = dev_read_u32(dev, "early-regs", &base);
  40                 if (ret)
  41                         return log_msg_ret("early-regs", ret);
  42
  43                 /* Set i2c base address */
  44                 dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
  45
  46                 /* Enable memory access and bus master */
  47                 dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
  48                                       PCI_COMMAND_MASTER);
  49         }
  50
  51         if (spl_phase() < PHASE_BOARD_F) {
  52                 /* Handle early, fixed mapping into a different address space */
  53                 priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
  54         } else {
  55                 priv->regs = (struct i2c_regs *)
  56                         dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
  57         }
  58         if (!priv->regs)
  59                 return -EINVAL;
  60
  61         /* Save base address from PCI BAR */
  62         if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
  63                 /* Use BayTrail specific timing values */
  64                 priv->scl_sda_cfg = &byt_config;
  65         if (dev_get_driver_data(dev) == INTEL_APL)
  66                 priv->has_spk_cnt = true;
  67
  68         return designware_i2c_ofdata_to_platdata(dev);
  69 }
  70
  71 static int designware_i2c_pci_probe(struct udevice *dev)
  72 {
  73         struct dw_i2c *priv = dev_get_priv(dev);
  74
  75         if (dev_get_driver_data(dev) == INTEL_APL) {
  76                 /* Ensure controller is in D0 state */
  77                 lpss_set_power_state(dev, STATE_D0);
  78
  79                 lpss_reset_release(priv->regs);
  80         }
  81
  82         return designware_i2c_probe(dev);
  83 }
  84
  85 static int designware_i2c_pci_bind(struct udevice *dev)
  86 {
  87         char name[20];
  88
  89         /*
  90          * Create a unique device name for PCI type devices
  91          * ToDo:
  92          * Setting req_seq in the driver is probably not recommended.
  93          * But without a DT alias the number is not configured. And
  94          * using this driver is impossible for PCIe I2C devices.
  95          * This can be removed, once a better (correct) way for this
  96          * is found and implemented.
  97          *
  98          * TODO(sjg@chromium.org): Perhaps if uclasses had platdata this would
  99          * be possible. We cannot use static data in drivers since they may be
 100          * used in SPL or before relocation.
 101          */
 102         dev->req_seq = gd->arch.dw_i2c_num_cards++;
 103         sprintf(name, "i2c_designware#%u", dev->req_seq);
 104         device_set_name(dev, name);
 105
 106         return 0;
 107 }
 108
 109 static const struct udevice_id designware_i2c_pci_ids[] = {
 110         { .compatible = "snps,designware-i2c-pci" },
 111         { .compatible = "intel,apl-i2c", .data = INTEL_APL },
 112         { }
 113 };
 114
 115 U_BOOT_DRIVER(i2c_designware_pci) = {
 116         .name   = "i2c_designware_pci",
 117         .id     = UCLASS_I2C,
 118         .of_match = designware_i2c_pci_ids,
 119         .bind   = designware_i2c_pci_bind,
 120         .ofdata_to_platdata     = designware_i2c_pci_ofdata_to_platdata,
 121         .probe  = designware_i2c_pci_probe,
 122         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 123         .remove = designware_i2c_remove,
 124         .flags = DM_FLAG_OS_PREPARE,
 125         .ops    = &designware_i2c_ops,
 126 };
 127
 128 static struct pci_device_id designware_pci_supported[] = {
 129         /* Intel BayTrail has 7 I2C controller located on the PCI bus */
 130         { PCI_VDEVICE(INTEL, 0x0f41) },
 131         { PCI_VDEVICE(INTEL, 0x0f42) },
 132         { PCI_VDEVICE(INTEL, 0x0f43) },
 133         { PCI_VDEVICE(INTEL, 0x0f44) },
 134         { PCI_VDEVICE(INTEL, 0x0f45) },
 135         { PCI_VDEVICE(INTEL, 0x0f46) },
 136         { PCI_VDEVICE(INTEL, 0x0f47) },
 137         { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
 138         { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
 139         { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
 140         { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
 141         { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
 142         { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
 143         {},
 144 };
 145
 146 U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);