drivers/i2c/designware_i2c.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #ifndef __DW_I2C_H_
   8 #define __DW_I2C_H_
   9
  10 #include <reset.h>
  11
  12 struct i2c_regs {
  13         u32 ic_con;             /* 0x00 */
  14         u32 ic_tar;             /* 0x04 */
  15         u32 ic_sar;             /* 0x08 */
  16         u32 ic_hs_maddr;        /* 0x0c */
  17         u32 ic_cmd_data;        /* 0x10 */
  18         u32 ic_ss_scl_hcnt;     /* 0x14 */
  19         u32 ic_ss_scl_lcnt;     /* 0x18 */
  20         u32 ic_fs_scl_hcnt;     /* 0x1c */
  21         u32 ic_fs_scl_lcnt;     /* 0x20 */
  22         u32 ic_hs_scl_hcnt;     /* 0x24 */
  23         u32 ic_hs_scl_lcnt;     /* 0x28 */
  24         u32 ic_intr_stat;       /* 0x2c */
  25         u32 ic_intr_mask;       /* 0x30 */
  26         u32 ic_raw_intr_stat;   /* 0x34 */
  27         u32 ic_rx_tl;           /* 0x38 */
  28         u32 ic_tx_tl;           /* 0x3c */
  29         u32 ic_clr_intr;        /* 0x40 */
  30         u32 ic_clr_rx_under;    /* 0x44 */
  31         u32 ic_clr_rx_over;     /* 0x48 */
  32         u32 ic_clr_tx_over;     /* 0x4c */
  33         u32 ic_clr_rd_req;      /* 0x50 */
  34         u32 ic_clr_tx_abrt;     /* 0x54 */
  35         u32 ic_clr_rx_done;     /* 0x58 */
  36         u32 ic_clr_activity;    /* 0x5c */
  37         u32 ic_clr_stop_det;    /* 0x60 */
  38         u32 ic_clr_start_det;   /* 0x64 */
  39         u32 ic_clr_gen_call;    /* 0x68 */
  40         u32 ic_enable;          /* 0x6c */
  41         u32 ic_status;          /* 0x70 */
  42         u32 ic_txflr;           /* 0x74 */
  43         u32 ic_rxflr;           /* 0x78 */
  44         u32 ic_sda_hold;        /* 0x7c */
  45         u32 ic_tx_abrt_source;  /* 0x80 */
  46         u8 res1[0x18];          /* 0x84 */
  47         u32 ic_enable_status;   /* 0x9c */
  48 };
  49
  50 #if !defined(IC_CLK)
  51 #define IC_CLK                  166
  52 #endif
  53 #define NANO_TO_MICRO           1000
  54
  55 /* High and low times in different speed modes (in ns) */
  56 #define MIN_SS_SCL_HIGHTIME     4000
  57 #define MIN_SS_SCL_LOWTIME      4700
  58 #define MIN_FS_SCL_HIGHTIME     600
  59 #define MIN_FS_SCL_LOWTIME      1300
  60 #define MIN_HS_SCL_HIGHTIME     60
  61 #define MIN_HS_SCL_LOWTIME      160
  62
  63 /* Worst case timeout for 1 byte is kept as 2ms */
  64 #define I2C_BYTE_TO             (CONFIG_SYS_HZ/500)
  65 #define I2C_STOPDET_TO          (CONFIG_SYS_HZ/500)
  66 #define I2C_BYTE_TO_BB          (I2C_BYTE_TO * 16)
  67
  68 /* i2c control register definitions */
  69 #define IC_CON_SD               0x0040
  70 #define IC_CON_RE               0x0020
  71 #define IC_CON_10BITADDRMASTER  0x0010
  72 #define IC_CON_10BITADDR_SLAVE  0x0008
  73 #define IC_CON_SPD_MSK          0x0006
  74 #define IC_CON_SPD_SS           0x0002
  75 #define IC_CON_SPD_FS           0x0004
  76 #define IC_CON_SPD_HS           0x0006
  77 #define IC_CON_MM               0x0001
  78
  79 /* i2c target address register definitions */
  80 #define TAR_ADDR                0x0050
  81
  82 /* i2c slave address register definitions */
  83 #define IC_SLAVE_ADDR           0x0002
  84
  85 /* i2c data buffer and command register definitions */
  86 #define IC_CMD                  0x0100
  87 #define IC_STOP                 0x0200
  88
  89 /* i2c interrupt status register definitions */
  90 #define IC_GEN_CALL             0x0800
  91 #define IC_START_DET            0x0400
  92 #define IC_STOP_DET             0x0200
  93 #define IC_ACTIVITY             0x0100
  94 #define IC_RX_DONE              0x0080
  95 #define IC_TX_ABRT              0x0040
  96 #define IC_RD_REQ               0x0020
  97 #define IC_TX_EMPTY             0x0010
  98 #define IC_TX_OVER              0x0008
  99 #define IC_RX_FULL              0x0004
 100 #define IC_RX_OVER              0x0002
 101 #define IC_RX_UNDER             0x0001
 102
 103 /* fifo threshold register definitions */
 104 #define IC_TL0                  0x00
 105 #define IC_TL1                  0x01
 106 #define IC_TL2                  0x02
 107 #define IC_TL3                  0x03
 108 #define IC_TL4                  0x04
 109 #define IC_TL5                  0x05
 110 #define IC_TL6                  0x06
 111 #define IC_TL7                  0x07
 112 #define IC_RX_TL                IC_TL0
 113 #define IC_TX_TL                IC_TL0
 114
 115 /* i2c enable register definitions */
 116 #define IC_ENABLE_0B            0x0001
 117
 118 /* i2c status register  definitions */
 119 #define IC_STATUS_SA            0x0040
 120 #define IC_STATUS_MA            0x0020
 121 #define IC_STATUS_RFF           0x0010
 122 #define IC_STATUS_RFNE          0x0008
 123 #define IC_STATUS_TFE           0x0004
 124 #define IC_STATUS_TFNF          0x0002
 125 #define IC_STATUS_ACT           0x0001
 126
 127 /* Speed Selection */
 128 #define IC_SPEED_MODE_STANDARD  1
 129 #define IC_SPEED_MODE_FAST      2
 130 #define IC_SPEED_MODE_MAX       3
 131
 132 #define I2C_MAX_SPEED           3400000
 133 #define I2C_FAST_SPEED          400000
 134 #define I2C_STANDARD_SPEED      100000
 135
 136 /**
 137  * struct dw_scl_sda_cfg - I2C timing configuration
 138  *
 139  * @has_max_speed: Support maximum speed (1Mbps)
 140  * @ss_hcnt: Standard speed high time in ns
 141  * @fs_hcnt: Fast speed high time in ns
 142  * @ss_lcnt: Standard speed low time in ns
 143  * @fs_lcnt: Fast speed low time in ns
 144  * @sda_hold: SDA hold time
 145  */
 146 struct dw_scl_sda_cfg {
 147         bool has_max_speed;
 148         u32 ss_hcnt;
 149         u32 fs_hcnt;
 150         u32 ss_lcnt;
 151         u32 fs_lcnt;
 152         u32 sda_hold;
 153 };
 154
 155 struct dw_i2c {
 156         struct i2c_regs *regs;
 157         struct dw_scl_sda_cfg *scl_sda_cfg;
 158         struct reset_ctl_bulk resets;
 159 #if CONFIG_IS_ENABLED(CLK)
 160         struct clk clk;
 161 #endif
 162 };
 163
 164 extern const struct dm_i2c_ops designware_i2c_ops;
 165
 166 int designware_i2c_probe(struct udevice *bus);
 167 int designware_i2c_remove(struct udevice *dev);
 168
 169 #endif /* __DW_I2C_H_ */