1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
14 u32 ic_con; /* 0x00 */
15 u32 ic_tar; /* 0x04 */
16 u32 ic_sar; /* 0x08 */
17 u32 ic_hs_maddr; /* 0x0c */
18 u32 ic_cmd_data; /* 0x10 */
19 u32 ic_ss_scl_hcnt; /* 0x14 */
20 u32 ic_ss_scl_lcnt; /* 0x18 */
21 u32 ic_fs_scl_hcnt; /* 0x1c */
22 u32 ic_fs_scl_lcnt; /* 0x20 */
23 u32 ic_hs_scl_hcnt; /* 0x24 */
24 u32 ic_hs_scl_lcnt; /* 0x28 */
25 u32 ic_intr_stat; /* 0x2c */
26 u32 ic_intr_mask; /* 0x30 */
27 u32 ic_raw_intr_stat; /* 0x34 */
28 u32 ic_rx_tl; /* 0x38 */
29 u32 ic_tx_tl; /* 0x3c */
30 u32 ic_clr_intr; /* 0x40 */
31 u32 ic_clr_rx_under; /* 0x44 */
32 u32 ic_clr_rx_over; /* 0x48 */
33 u32 ic_clr_tx_over; /* 0x4c */
34 u32 ic_clr_rd_req; /* 0x50 */
35 u32 ic_clr_tx_abrt; /* 0x54 */
36 u32 ic_clr_rx_done; /* 0x58 */
37 u32 ic_clr_activity; /* 0x5c */
38 u32 ic_clr_stop_det; /* 0x60 */
39 u32 ic_clr_start_det; /* 0x64 */
40 u32 ic_clr_gen_call; /* 0x68 */
41 u32 ic_enable; /* 0x6c */
42 u32 ic_status; /* 0x70 */
43 u32 ic_txflr; /* 0x74 */
44 u32 ic_rxflr; /* 0x78 */
45 u32 ic_sda_hold; /* 0x7c */
46 u32 ic_tx_abrt_source; /* 0x80 */
47 u32 slv_data_nak_only;
53 u32 ic_enable_status; /* 0x9c */
57 u8 reserved[0xf4 - 0xac];
58 u32 comp_param1; /* 0xf4 */
63 #define IC_CLK 166666666
64 #define NANO_TO_KILO 1000000
66 /* High and low times in different speed modes (in ns) */
67 #define MIN_SS_SCL_HIGHTIME 4000
68 #define MIN_SS_SCL_LOWTIME 4700
69 #define MIN_FS_SCL_HIGHTIME 600
70 #define MIN_FS_SCL_LOWTIME 1300
71 #define MIN_FP_SCL_HIGHTIME 260
72 #define MIN_FP_SCL_LOWTIME 500
73 #define MIN_HS_SCL_HIGHTIME 60
74 #define MIN_HS_SCL_LOWTIME 160
76 /* Worst case timeout for 1 byte is kept as 2ms */
77 #define I2C_BYTE_TO (CONFIG_SYS_HZ/500)
78 #define I2C_STOPDET_TO (CONFIG_SYS_HZ/500)
79 #define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16)
81 /* i2c control register definitions */
82 #define IC_CON_SD 0x0040
83 #define IC_CON_RE 0x0020
84 #define IC_CON_10BITADDRMASTER 0x0010
85 #define IC_CON_10BITADDR_SLAVE 0x0008
86 #define IC_CON_SPD_MSK 0x0006
87 #define IC_CON_SPD_SS 0x0002
88 #define IC_CON_SPD_FS 0x0004
89 #define IC_CON_SPD_HS 0x0006
90 #define IC_CON_MM 0x0001
92 /* i2c target address register definitions */
93 #define TAR_ADDR 0x0050
95 /* i2c slave address register definitions */
96 #define IC_SLAVE_ADDR 0x0002
98 /* i2c data buffer and command register definitions */
100 #define IC_STOP 0x0200
102 /* i2c interrupt status register definitions */
103 #define IC_GEN_CALL 0x0800
104 #define IC_START_DET 0x0400
105 #define IC_STOP_DET 0x0200
106 #define IC_ACTIVITY 0x0100
107 #define IC_RX_DONE 0x0080
108 #define IC_TX_ABRT 0x0040
109 #define IC_RD_REQ 0x0020
110 #define IC_TX_EMPTY 0x0010
111 #define IC_TX_OVER 0x0008
112 #define IC_RX_FULL 0x0004
113 #define IC_RX_OVER 0x0002
114 #define IC_RX_UNDER 0x0001
116 /* fifo threshold register definitions */
125 #define IC_RX_TL IC_TL0
126 #define IC_TX_TL IC_TL0
128 /* i2c enable register definitions */
129 #define IC_ENABLE_0B 0x0001
131 /* i2c status register definitions */
132 #define IC_STATUS_SA 0x0040
133 #define IC_STATUS_MA 0x0020
134 #define IC_STATUS_RFF 0x0010
135 #define IC_STATUS_RFNE 0x0008
136 #define IC_STATUS_TFE 0x0004
137 #define IC_STATUS_TFNF 0x0002
138 #define IC_STATUS_ACT 0x0001
141 * struct dw_scl_sda_cfg - I2C timing configuration
143 * @has_high_speed: Support high speed (3.4Mbps)
144 * @ss_hcnt: Standard speed high time in ns
145 * @fs_hcnt: Fast speed high time in ns
146 * @ss_lcnt: Standard speed low time in ns
147 * @fs_lcnt: Fast speed low time in ns
148 * @sda_hold: SDA hold time
150 struct dw_scl_sda_cfg {
160 * struct dw_i2c_speed_config - timings to use for a particular speed
162 * This holds calculated values to be written to the I2C controller. Each value
163 * is represented as a number of IC clock cycles.
165 * @scl_lcnt: Low count value for SCL
166 * @scl_hcnt: High count value for SCL
167 * @sda_hold: Data hold count
169 struct dw_i2c_speed_config {
170 /* SCL high and low period count */
177 * struct dw_i2c - private information for the bus
179 * @regs: Registers pointer
180 * @scl_sda_cfg: Deprecated information for x86 (should move to device tree)
181 * @resets: Resets for the I2C controller
182 * @scl_rise_time_ns: Configured SCL rise time in nanoseconds
183 * @scl_fall_time_ns: Configured SCL fall time in nanoseconds
184 * @sda_hold_time_ns: Configured SDA hold time in nanoseconds
185 * @has_spk_cnt: true if the spike-count register is present
186 * @clk: Clock input to the I2C controller
189 struct i2c_regs *regs;
190 struct dw_scl_sda_cfg *scl_sda_cfg;
191 struct reset_ctl_bulk resets;
192 u32 scl_rise_time_ns;
193 u32 scl_fall_time_ns;
194 u32 sda_hold_time_ns;
196 #if CONFIG_IS_ENABLED(CLK)
201 extern const struct dm_i2c_ops designware_i2c_ops;
203 int designware_i2c_probe(struct udevice *bus);
204 int designware_i2c_remove(struct udevice *dev);
205 int designware_i2c_ofdata_to_platdata(struct udevice *bus);
207 #endif /* __DW_I2C_H_ */