1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
13 #include "designware_i2c.h"
15 struct dw_scl_sda_cfg {
24 /* BayTrail HCNT/LCNT/SDA hold time */
25 static struct dw_scl_sda_cfg byt_config = {
35 struct i2c_regs *regs;
36 struct dw_scl_sda_cfg *scl_sda_cfg;
37 struct reset_ctl reset_ctl;
40 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
41 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
43 u32 ena = enable ? IC_ENABLE_0B : 0;
45 writel(ena, &i2c_base->ic_enable);
48 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
50 u32 ena = enable ? IC_ENABLE_0B : 0;
54 writel(ena, &i2c_base->ic_enable);
55 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
59 * Wait 10 times the signaling period of the highest I2C
60 * transfer supported by the driver (for 400KHz this is
61 * 25us) as described in the DesignWare I2C databook.
66 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
71 * i2c_set_bus_speed - Set the i2c speed
72 * @speed: required i2c speed
76 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
77 struct dw_scl_sda_cfg *scl_sda_cfg,
81 unsigned int hcnt, lcnt;
84 if (speed >= I2C_MAX_SPEED)
85 i2c_spd = IC_SPEED_MODE_MAX;
86 else if (speed >= I2C_FAST_SPEED)
87 i2c_spd = IC_SPEED_MODE_FAST;
89 i2c_spd = IC_SPEED_MODE_STANDARD;
91 /* to set speed cltr must be disabled */
92 dw_i2c_enable(i2c_base, false);
94 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
97 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
98 case IC_SPEED_MODE_MAX:
99 cntl |= IC_CON_SPD_SS;
101 hcnt = scl_sda_cfg->fs_hcnt;
102 lcnt = scl_sda_cfg->fs_lcnt;
104 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
105 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
107 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
108 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
112 case IC_SPEED_MODE_STANDARD:
113 cntl |= IC_CON_SPD_SS;
115 hcnt = scl_sda_cfg->ss_hcnt;
116 lcnt = scl_sda_cfg->ss_lcnt;
118 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
119 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
121 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
122 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
125 case IC_SPEED_MODE_FAST:
127 cntl |= IC_CON_SPD_FS;
129 hcnt = scl_sda_cfg->fs_hcnt;
130 lcnt = scl_sda_cfg->fs_lcnt;
132 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
133 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
135 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
136 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
140 writel(cntl, &i2c_base->ic_con);
142 /* Configure SDA Hold Time if required */
144 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
146 /* Enable back i2c now speed set */
147 dw_i2c_enable(i2c_base, true);
153 * i2c_setaddress - Sets the target slave address
154 * @i2c_addr: target i2c address
156 * Sets the target slave address.
158 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
161 dw_i2c_enable(i2c_base, false);
163 writel(i2c_addr, &i2c_base->ic_tar);
166 dw_i2c_enable(i2c_base, true);
170 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
172 * Flushes the i2c RX FIFO
174 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
176 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
177 readl(&i2c_base->ic_cmd_data);
181 * i2c_wait_for_bb - Waits for bus busy
185 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
187 unsigned long start_time_bb = get_timer(0);
189 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
190 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
192 /* Evaluate timeout */
193 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
200 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
203 if (i2c_wait_for_bb(i2c_base))
206 i2c_setaddress(i2c_base, chip);
209 /* high byte address going out first */
210 writel((addr >> (alen * 8)) & 0xff,
211 &i2c_base->ic_cmd_data);
216 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
218 ulong start_stop_det = get_timer(0);
221 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
222 readl(&i2c_base->ic_clr_stop_det);
224 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
229 if (i2c_wait_for_bb(i2c_base)) {
230 printf("Timed out waiting for bus\n");
234 i2c_flush_rxfifo(i2c_base);
240 * i2c_read - Read from i2c memory
241 * @chip: target i2c address
242 * @addr: address to read from
244 * @buffer: buffer for read data
245 * @len: no of bytes to be read
247 * Read from i2c memory.
249 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
250 int alen, u8 *buffer, int len)
252 unsigned long start_time_rx;
253 unsigned int active = 0;
255 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
257 * EEPROM chips that implement "address overflow" are ones
258 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
259 * address and the extra bits end up in the "chip address"
260 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
261 * four 256 byte chips.
263 * Note that we consider the length of the address field to
264 * still be one byte because the extra address bits are
265 * hidden in the chip address.
267 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
268 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
270 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
274 if (i2c_xfer_init(i2c_base, dev, addr, alen))
277 start_time_rx = get_timer(0);
281 * Avoid writing to ic_cmd_data multiple times
282 * in case this loop spins too quickly and the
283 * ic_status RFNE bit isn't set after the first
284 * write. Subsequent writes to ic_cmd_data can
285 * trigger spurious i2c transfer.
288 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
290 writel(IC_CMD, &i2c_base->ic_cmd_data);
294 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
295 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
297 start_time_rx = get_timer(0);
299 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
304 return i2c_xfer_finish(i2c_base);
308 * i2c_write - Write to i2c memory
309 * @chip: target i2c address
310 * @addr: address to read from
312 * @buffer: buffer for read data
313 * @len: no of bytes to be read
315 * Write to i2c memory.
317 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
318 int alen, u8 *buffer, int len)
321 unsigned long start_time_tx;
323 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
325 * EEPROM chips that implement "address overflow" are ones
326 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
327 * address and the extra bits end up in the "chip address"
328 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
329 * four 256 byte chips.
331 * Note that we consider the length of the address field to
332 * still be one byte because the extra address bits are
333 * hidden in the chip address.
335 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
336 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
338 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
342 if (i2c_xfer_init(i2c_base, dev, addr, alen))
345 start_time_tx = get_timer(0);
347 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
349 writel(*buffer | IC_STOP,
350 &i2c_base->ic_cmd_data);
352 writel(*buffer, &i2c_base->ic_cmd_data);
355 start_time_tx = get_timer(0);
357 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
358 printf("Timed out. i2c write Failed\n");
363 return i2c_xfer_finish(i2c_base);
367 * __dw_i2c_init - Init function
368 * @speed: required i2c speed
369 * @slaveaddr: slave address for the device
371 * Initialization function.
373 static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
376 dw_i2c_enable(i2c_base, false);
378 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
380 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
381 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
382 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
383 #ifndef CONFIG_DM_I2C
384 __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
385 writel(slaveaddr, &i2c_base->ic_sar);
389 dw_i2c_enable(i2c_base, true);
392 #ifndef CONFIG_DM_I2C
394 * The legacy I2C functions. These need to get removed once
395 * all users of this driver are converted to DM.
397 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
399 switch (adap->hwadapnr) {
400 #if CONFIG_SYS_I2C_BUS_MAX >= 4
402 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
404 #if CONFIG_SYS_I2C_BUS_MAX >= 3
406 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
408 #if CONFIG_SYS_I2C_BUS_MAX >= 2
410 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
413 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
415 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
421 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
425 return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
428 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
430 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
433 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
434 int alen, u8 *buffer, int len)
436 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
439 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
440 int alen, u8 *buffer, int len)
442 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
445 /* dw_i2c_probe - Probe the i2c chip */
446 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
448 struct i2c_regs *i2c_base = i2c_get_base(adap);
453 * Try to read the first location of the chip.
455 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
457 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
462 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
463 dw_i2c_write, dw_i2c_set_bus_speed,
464 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
466 #if CONFIG_SYS_I2C_BUS_MAX >= 2
467 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
468 dw_i2c_write, dw_i2c_set_bus_speed,
469 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
472 #if CONFIG_SYS_I2C_BUS_MAX >= 3
473 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
474 dw_i2c_write, dw_i2c_set_bus_speed,
475 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
478 #if CONFIG_SYS_I2C_BUS_MAX >= 4
479 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
480 dw_i2c_write, dw_i2c_set_bus_speed,
481 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
484 #else /* CONFIG_DM_I2C */
485 /* The DM I2C functions */
487 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
490 struct dw_i2c *i2c = dev_get_priv(bus);
493 debug("i2c_xfer: %d messages\n", nmsgs);
494 for (; nmsgs > 0; nmsgs--, msg++) {
495 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
496 if (msg->flags & I2C_M_RD) {
497 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
500 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
504 debug("i2c_write: error sending\n");
512 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
514 struct dw_i2c *i2c = dev_get_priv(bus);
516 return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
519 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
522 struct dw_i2c *i2c = dev_get_priv(bus);
523 struct i2c_regs *i2c_base = i2c->regs;
527 /* Try to read the first location of the chip */
528 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
530 __dw_i2c_init(i2c_base, 0, 0);
535 static int designware_i2c_probe(struct udevice *bus)
537 struct dw_i2c *priv = dev_get_priv(bus);
540 if (device_is_on_pci_bus(bus)) {
542 /* Save base address from PCI BAR */
543 priv->regs = (struct i2c_regs *)
544 dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
546 /* Use BayTrail specific timing values */
547 priv->scl_sda_cfg = &byt_config;
551 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
554 ret = reset_get_by_name(bus, "i2c", &priv->reset_ctl);
556 pr_info("reset_get_by_name() failed: %d\n", ret);
558 if (&priv->reset_ctl)
559 reset_deassert(&priv->reset_ctl);
561 __dw_i2c_init(priv->regs, 0, 0);
566 static int designware_i2c_bind(struct udevice *dev)
568 static int num_cards;
571 /* Create a unique device name for PCI type devices */
572 if (device_is_on_pci_bus(dev)) {
575 * Setting req_seq in the driver is probably not recommended.
576 * But without a DT alias the number is not configured. And
577 * using this driver is impossible for PCIe I2C devices.
578 * This can be removed, once a better (correct) way for this
579 * is found and implemented.
581 dev->req_seq = num_cards;
582 sprintf(name, "i2c_designware#%u", num_cards++);
583 device_set_name(dev, name);
589 static const struct dm_i2c_ops designware_i2c_ops = {
590 .xfer = designware_i2c_xfer,
591 .probe_chip = designware_i2c_probe_chip,
592 .set_bus_speed = designware_i2c_set_bus_speed,
595 static const struct udevice_id designware_i2c_ids[] = {
596 { .compatible = "snps,designware-i2c" },
600 U_BOOT_DRIVER(i2c_designware) = {
601 .name = "i2c_designware",
603 .of_match = designware_i2c_ids,
604 .bind = designware_i2c_bind,
605 .probe = designware_i2c_probe,
606 .priv_auto_alloc_size = sizeof(struct dw_i2c),
607 .ops = &designware_i2c_ops,
611 static struct pci_device_id designware_pci_supported[] = {
612 /* Intel BayTrail has 7 I2C controller located on the PCI bus */
613 { PCI_VDEVICE(INTEL, 0x0f41) },
614 { PCI_VDEVICE(INTEL, 0x0f42) },
615 { PCI_VDEVICE(INTEL, 0x0f43) },
616 { PCI_VDEVICE(INTEL, 0x0f44) },
617 { PCI_VDEVICE(INTEL, 0x0f45) },
618 { PCI_VDEVICE(INTEL, 0x0f46) },
619 { PCI_VDEVICE(INTEL, 0x0f47) },
623 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
626 #endif /* CONFIG_DM_I2C */