1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
14 #include "designware_i2c.h"
16 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
17 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
19 u32 ena = enable ? IC_ENABLE_0B : 0;
21 writel(ena, &i2c_base->ic_enable);
26 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
28 u32 ena = enable ? IC_ENABLE_0B : 0;
32 writel(ena, &i2c_base->ic_enable);
33 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
37 * Wait 10 times the signaling period of the highest I2C
38 * transfer supported by the driver (for 400KHz this is
39 * 25us) as described in the DesignWare I2C databook.
43 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
49 /* High and low times in different speed modes (in ns) */
52 DEFAULT_SDA_HOLD_TIME = 300,
56 * calc_counts() - Convert a period to a number of IC clk cycles
58 * @ic_clk: Input clock in Hz
59 * @period_ns: Period to represent, in ns
60 * @return calculated count
62 static uint calc_counts(uint ic_clk, uint period_ns)
64 return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
68 * struct i2c_mode_info - Information about an I2C speed mode
70 * Each speed mode has its own characteristics. This struct holds these to aid
71 * calculations in dw_i2c_calc_timing().
74 * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
75 * @min_scl_hightime_ns: Minimum value for SCL high period in ns
76 * @def_rise_time_ns: Default rise time in ns
77 * @def_fall_time_ns: Default fall time in ns
79 struct i2c_mode_info {
81 int min_scl_hightime_ns;
82 int min_scl_lowtime_ns;
87 static const struct i2c_mode_info info_for_mode[] = {
88 [IC_SPEED_MODE_STANDARD] = {
89 I2C_SPEED_STANDARD_RATE,
95 [IC_SPEED_MODE_FAST] = {
102 [IC_SPEED_MODE_FAST_PLUS] = {
103 I2C_SPEED_FAST_PLUS_RATE,
109 [IC_SPEED_MODE_HIGH] = {
119 * dw_i2c_calc_timing() - Calculate the timings to use for a bus
121 * @priv: Bus private information (NULL if not using driver model)
122 * @mode: Speed mode to use
123 * @ic_clk: IC clock speed in Hz
124 * @spk_cnt: Spike-suppression count
125 * @config: Returns value to use
126 * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
128 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
129 int ic_clk, int spk_cnt,
130 struct dw_i2c_speed_config *config)
132 int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
133 int hcnt, lcnt, period_cnt, diff, tot;
134 int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
135 const struct i2c_mode_info *info;
138 * Find the period, rise, fall, min tlow, and min thigh in terms of
139 * counts of the IC clock
141 info = &info_for_mode[mode];
142 period_cnt = ic_clk / info->speed;
143 scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
144 priv->scl_rise_time_ns : info->def_rise_time_ns;
145 scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
146 priv->scl_fall_time_ns : info->def_fall_time_ns;
147 rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
148 fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
149 min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
150 min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
152 debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
153 period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
157 * Back-solve for hcnt and lcnt according to the following equations:
158 * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
159 * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
161 hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
162 lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
164 if (hcnt < 0 || lcnt < 0) {
165 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
170 * Now add things back up to ensure the period is hit. If it is off,
171 * split the difference and bias to lcnt for remainder
173 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
175 if (tot < period_cnt) {
176 diff = (period_cnt - tot) / 2;
179 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
180 lcnt += period_cnt - tot;
183 config->scl_lcnt = lcnt;
184 config->scl_hcnt = hcnt;
186 /* Use internal default unless other value is specified */
187 sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
188 priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
189 config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
191 debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
197 static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
198 struct dw_i2c_speed_config *config)
200 const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
201 struct i2c_regs *regs = priv->regs;
202 enum i2c_speed_mode i2c_spd;
207 scl_sda_cfg = priv->scl_sda_cfg;
208 /* Allow high speed if there is no config, or the config allows it */
209 if (speed >= I2C_SPEED_HIGH_RATE &&
210 (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
211 i2c_spd = IC_SPEED_MODE_HIGH;
212 else if (speed >= I2C_SPEED_FAST_RATE)
213 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
214 else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
215 i2c_spd = IC_SPEED_MODE_FAST;
217 i2c_spd = IC_SPEED_MODE_STANDARD;
219 /* Get the proper spike-suppression count based on target speed */
220 if (!priv || !priv->has_spk_cnt)
222 else if (i2c_spd >= IC_SPEED_MODE_HIGH)
223 spk_cnt = readl(®s->hs_spklen);
225 spk_cnt = readl(®s->fs_spklen);
227 config->sda_hold = scl_sda_cfg->sda_hold;
228 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
229 config->scl_hcnt = scl_sda_cfg->ss_hcnt;
230 config->scl_lcnt = scl_sda_cfg->ss_lcnt;
232 config->scl_hcnt = scl_sda_cfg->fs_hcnt;
233 config->scl_lcnt = scl_sda_cfg->fs_lcnt;
236 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
239 return log_msg_ret("gen_confg", ret);
241 config->speed_mode = i2c_spd;
247 * _dw_i2c_set_bus_speed - Set the i2c speed
248 * @speed: required i2c speed
252 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
253 unsigned int speed, unsigned int bus_clk)
255 struct dw_i2c_speed_config config;
260 ret = calc_bus_speed(priv, speed, bus_clk, &config);
264 /* Get enable setting for restore later */
265 ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
267 /* to set speed cltr must be disabled */
268 dw_i2c_enable(i2c_base, false);
270 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
272 switch (config.speed_mode) {
273 case IC_SPEED_MODE_HIGH:
274 cntl |= IC_CON_SPD_SS;
275 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
276 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
278 case IC_SPEED_MODE_STANDARD:
279 cntl |= IC_CON_SPD_SS;
280 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
281 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
283 case IC_SPEED_MODE_FAST_PLUS:
284 case IC_SPEED_MODE_FAST:
286 cntl |= IC_CON_SPD_FS;
287 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
288 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
292 writel(cntl, &i2c_base->ic_con);
294 /* Configure SDA Hold Time if required */
296 writel(config.sda_hold, &i2c_base->ic_sda_hold);
298 /* Restore back i2c now speed set */
299 if (ena == IC_ENABLE_0B)
300 dw_i2c_enable(i2c_base, true);
306 * i2c_setaddress - Sets the target slave address
307 * @i2c_addr: target i2c address
309 * Sets the target slave address.
311 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
314 dw_i2c_enable(i2c_base, false);
316 writel(i2c_addr, &i2c_base->ic_tar);
319 dw_i2c_enable(i2c_base, true);
323 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
325 * Flushes the i2c RX FIFO
327 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
329 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
330 readl(&i2c_base->ic_cmd_data);
334 * i2c_wait_for_bb - Waits for bus busy
338 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
340 unsigned long start_time_bb = get_timer(0);
342 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
343 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
345 /* Evaluate timeout */
346 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
353 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
356 if (i2c_wait_for_bb(i2c_base))
359 i2c_setaddress(i2c_base, chip);
362 /* high byte address going out first */
363 writel((addr >> (alen * 8)) & 0xff,
364 &i2c_base->ic_cmd_data);
369 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
371 ulong start_stop_det = get_timer(0);
374 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
375 readl(&i2c_base->ic_clr_stop_det);
377 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
382 if (i2c_wait_for_bb(i2c_base)) {
383 printf("Timed out waiting for bus\n");
387 i2c_flush_rxfifo(i2c_base);
393 * i2c_read - Read from i2c memory
394 * @chip: target i2c address
395 * @addr: address to read from
397 * @buffer: buffer for read data
398 * @len: no of bytes to be read
400 * Read from i2c memory.
402 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
403 int alen, u8 *buffer, int len)
405 unsigned long start_time_rx;
406 unsigned int active = 0;
408 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
410 * EEPROM chips that implement "address overflow" are ones
411 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
412 * address and the extra bits end up in the "chip address"
413 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
414 * four 256 byte chips.
416 * Note that we consider the length of the address field to
417 * still be one byte because the extra address bits are
418 * hidden in the chip address.
420 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
421 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
423 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
427 if (i2c_xfer_init(i2c_base, dev, addr, alen))
430 start_time_rx = get_timer(0);
434 * Avoid writing to ic_cmd_data multiple times
435 * in case this loop spins too quickly and the
436 * ic_status RFNE bit isn't set after the first
437 * write. Subsequent writes to ic_cmd_data can
438 * trigger spurious i2c transfer.
441 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
443 writel(IC_CMD, &i2c_base->ic_cmd_data);
447 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
448 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
450 start_time_rx = get_timer(0);
452 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
457 return i2c_xfer_finish(i2c_base);
461 * i2c_write - Write to i2c memory
462 * @chip: target i2c address
463 * @addr: address to read from
465 * @buffer: buffer for read data
466 * @len: no of bytes to be read
468 * Write to i2c memory.
470 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
471 int alen, u8 *buffer, int len)
474 unsigned long start_time_tx;
476 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
478 * EEPROM chips that implement "address overflow" are ones
479 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
480 * address and the extra bits end up in the "chip address"
481 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
482 * four 256 byte chips.
484 * Note that we consider the length of the address field to
485 * still be one byte because the extra address bits are
486 * hidden in the chip address.
488 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
489 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
491 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
495 if (i2c_xfer_init(i2c_base, dev, addr, alen))
498 start_time_tx = get_timer(0);
500 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
502 writel(*buffer | IC_STOP,
503 &i2c_base->ic_cmd_data);
505 writel(*buffer, &i2c_base->ic_cmd_data);
508 start_time_tx = get_timer(0);
510 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
511 printf("Timed out. i2c write Failed\n");
516 return i2c_xfer_finish(i2c_base);
520 * __dw_i2c_init - Init function
521 * @speed: required i2c speed
522 * @slaveaddr: slave address for the device
524 * Initialization function.
526 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
531 ret = dw_i2c_enable(i2c_base, false);
535 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
537 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
538 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
539 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
540 #ifndef CONFIG_DM_I2C
541 _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
542 writel(slaveaddr, &i2c_base->ic_sar);
546 ret = dw_i2c_enable(i2c_base, true);
553 #ifndef CONFIG_DM_I2C
555 * The legacy I2C functions. These need to get removed once
556 * all users of this driver are converted to DM.
558 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
560 switch (adap->hwadapnr) {
561 #if CONFIG_SYS_I2C_BUS_MAX >= 4
563 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
565 #if CONFIG_SYS_I2C_BUS_MAX >= 3
567 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
569 #if CONFIG_SYS_I2C_BUS_MAX >= 2
571 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
574 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
576 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
582 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
586 return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
589 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
591 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
594 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
595 int alen, u8 *buffer, int len)
597 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
600 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
601 int alen, u8 *buffer, int len)
603 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
606 /* dw_i2c_probe - Probe the i2c chip */
607 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
609 struct i2c_regs *i2c_base = i2c_get_base(adap);
614 * Try to read the first location of the chip.
616 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
618 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
623 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
624 dw_i2c_write, dw_i2c_set_bus_speed,
625 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
627 #if CONFIG_SYS_I2C_BUS_MAX >= 2
628 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
629 dw_i2c_write, dw_i2c_set_bus_speed,
630 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
633 #if CONFIG_SYS_I2C_BUS_MAX >= 3
634 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
635 dw_i2c_write, dw_i2c_set_bus_speed,
636 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
639 #if CONFIG_SYS_I2C_BUS_MAX >= 4
640 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
641 dw_i2c_write, dw_i2c_set_bus_speed,
642 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
645 #else /* CONFIG_DM_I2C */
646 /* The DM I2C functions */
648 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
651 struct dw_i2c *i2c = dev_get_priv(bus);
654 debug("i2c_xfer: %d messages\n", nmsgs);
655 for (; nmsgs > 0; nmsgs--, msg++) {
656 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
657 if (msg->flags & I2C_M_RD) {
658 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
661 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
665 debug("i2c_write: error sending\n");
673 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
675 struct dw_i2c *i2c = dev_get_priv(bus);
678 #if CONFIG_IS_ENABLED(CLK)
679 rate = clk_get_rate(&i2c->clk);
680 if (IS_ERR_VALUE(rate))
685 return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
688 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
691 struct dw_i2c *i2c = dev_get_priv(bus);
692 struct i2c_regs *i2c_base = i2c->regs;
696 /* Try to read the first location of the chip */
697 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
699 __dw_i2c_init(i2c_base, 0, 0);
704 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
706 struct dw_i2c *priv = dev_get_priv(bus);
710 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
711 dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
712 dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
713 dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
715 ret = reset_get_bulk(bus, &priv->resets);
717 dev_warn(bus, "Can't get reset: %d\n", ret);
719 reset_deassert_bulk(&priv->resets);
721 #if CONFIG_IS_ENABLED(CLK)
722 ret = clk_get_by_index(bus, 0, &priv->clk);
726 ret = clk_enable(&priv->clk);
727 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
728 clk_free(&priv->clk);
729 dev_err(bus, "failed to enable clock\n");
737 int designware_i2c_probe(struct udevice *bus)
739 struct dw_i2c *priv = dev_get_priv(bus);
741 return __dw_i2c_init(priv->regs, 0, 0);
744 int designware_i2c_remove(struct udevice *dev)
746 struct dw_i2c *priv = dev_get_priv(dev);
748 #if CONFIG_IS_ENABLED(CLK)
749 clk_disable(&priv->clk);
750 clk_free(&priv->clk);
753 return reset_release_bulk(&priv->resets);
756 const struct dm_i2c_ops designware_i2c_ops = {
757 .xfer = designware_i2c_xfer,
758 .probe_chip = designware_i2c_probe_chip,
759 .set_bus_speed = designware_i2c_set_bus_speed,
762 static const struct udevice_id designware_i2c_ids[] = {
763 { .compatible = "snps,designware-i2c" },
767 U_BOOT_DRIVER(i2c_designware) = {
768 .name = "i2c_designware",
770 .of_match = designware_i2c_ids,
771 .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
772 .probe = designware_i2c_probe,
773 .priv_auto_alloc_size = sizeof(struct dw_i2c),
774 .remove = designware_i2c_remove,
775 .flags = DM_FLAG_OS_PREPARE,
776 .ops = &designware_i2c_ops,
779 #endif /* CONFIG_DM_I2C */