1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
14 #include "designware_i2c.h"
16 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
17 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
19 u32 ena = enable ? IC_ENABLE_0B : 0;
21 writel(ena, &i2c_base->ic_enable);
26 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
28 u32 ena = enable ? IC_ENABLE_0B : 0;
32 writel(ena, &i2c_base->ic_enable);
33 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
37 * Wait 10 times the signaling period of the highest I2C
38 * transfer supported by the driver (for 400KHz this is
39 * 25us) as described in the DesignWare I2C databook.
43 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
49 /* High and low times in different speed modes (in ns) */
52 DEFAULT_SDA_HOLD_TIME = 300,
56 * calc_counts() - Convert a period to a number of IC clk cycles
58 * @ic_clk: Input clock in Hz
59 * @period_ns: Period to represent, in ns
60 * @return calculated count
62 static uint calc_counts(uint ic_clk, uint period_ns)
64 return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
68 * struct i2c_mode_info - Information about an I2C speed mode
70 * Each speed mode has its own characteristics. This struct holds these to aid
71 * calculations in dw_i2c_calc_timing().
74 * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
75 * @min_scl_hightime_ns: Minimum value for SCL high period in ns
76 * @def_rise_time_ns: Default rise time in ns
77 * @def_fall_time_ns: Default fall time in ns
79 struct i2c_mode_info {
81 int min_scl_hightime_ns;
82 int min_scl_lowtime_ns;
87 static const struct i2c_mode_info info_for_mode[] = {
88 [IC_SPEED_MODE_STANDARD] = {
89 I2C_SPEED_STANDARD_RATE,
95 [IC_SPEED_MODE_FAST] = {
102 [IC_SPEED_MODE_FAST_PLUS] = {
103 I2C_SPEED_FAST_PLUS_RATE,
109 [IC_SPEED_MODE_HIGH] = {
119 * dw_i2c_calc_timing() - Calculate the timings to use for a bus
121 * @priv: Bus private information (NULL if not using driver model)
122 * @mode: Speed mode to use
123 * @ic_clk: IC clock speed in Hz
124 * @spk_cnt: Spike-suppression count
125 * @config: Returns value to use
126 * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
128 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
129 int ic_clk, int spk_cnt,
130 struct dw_i2c_speed_config *config)
132 int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
133 int hcnt, lcnt, period_cnt, diff, tot;
134 int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
135 const struct i2c_mode_info *info;
138 * Find the period, rise, fall, min tlow, and min thigh in terms of
139 * counts of the IC clock
141 info = &info_for_mode[mode];
142 period_cnt = ic_clk / info->speed;
143 scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
144 priv->scl_rise_time_ns : info->def_rise_time_ns;
145 scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
146 priv->scl_fall_time_ns : info->def_fall_time_ns;
147 rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
148 fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
149 min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
150 min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
152 debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
153 period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
157 * Back-solve for hcnt and lcnt according to the following equations:
158 * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
159 * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
161 hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
162 lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
164 if (hcnt < 0 || lcnt < 0) {
165 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
170 * Now add things back up to ensure the period is hit. If it is off,
171 * split the difference and bias to lcnt for remainder
173 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
175 if (tot < period_cnt) {
176 diff = (period_cnt - tot) / 2;
179 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
180 lcnt += period_cnt - tot;
183 config->scl_lcnt = lcnt;
184 config->scl_hcnt = hcnt;
186 /* Use internal default unless other value is specified */
187 sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
188 priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
189 config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
191 debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
198 * i2c_set_bus_speed - Set the i2c speed
199 * @speed: required i2c speed
203 static unsigned int __dw_i2c_set_bus_speed(struct dw_i2c *priv,
204 struct i2c_regs *i2c_base,
206 unsigned int bus_clk)
208 const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
209 struct dw_i2c_speed_config config;
210 enum i2c_speed_mode i2c_spd;
217 scl_sda_cfg = priv->scl_sda_cfg;
218 /* Allow high speed if there is no config, or the config allows it */
219 if (speed >= I2C_SPEED_HIGH_RATE &&
220 (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
221 i2c_spd = IC_SPEED_MODE_HIGH;
222 else if (speed >= I2C_SPEED_FAST_RATE)
223 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
224 else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
225 i2c_spd = IC_SPEED_MODE_FAST;
227 i2c_spd = IC_SPEED_MODE_STANDARD;
229 /* Get enable setting for restore later */
230 ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
232 /* to set speed cltr must be disabled */
233 dw_i2c_enable(i2c_base, false);
235 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
237 /* Get the proper spike-suppression count based on target speed */
238 if (!priv || !priv->has_spk_cnt)
240 else if (i2c_spd >= IC_SPEED_MODE_HIGH)
241 spk_cnt = readl(&i2c_base->hs_spklen);
243 spk_cnt = readl(&i2c_base->fs_spklen);
245 config.sda_hold = scl_sda_cfg->sda_hold;
246 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
247 config.scl_hcnt = scl_sda_cfg->ss_hcnt;
248 config.scl_lcnt = scl_sda_cfg->ss_lcnt;
250 config.scl_hcnt = scl_sda_cfg->fs_hcnt;
251 config.scl_lcnt = scl_sda_cfg->fs_lcnt;
254 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
257 return log_msg_ret("gen_confg", ret);
261 case IC_SPEED_MODE_HIGH:
262 cntl |= IC_CON_SPD_SS;
263 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
264 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
266 case IC_SPEED_MODE_STANDARD:
267 cntl |= IC_CON_SPD_SS;
268 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
269 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
271 case IC_SPEED_MODE_FAST_PLUS:
272 case IC_SPEED_MODE_FAST:
274 cntl |= IC_CON_SPD_FS;
275 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
276 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
280 writel(cntl, &i2c_base->ic_con);
282 /* Configure SDA Hold Time if required */
284 writel(config.sda_hold, &i2c_base->ic_sda_hold);
286 /* Restore back i2c now speed set */
287 if (ena == IC_ENABLE_0B)
288 dw_i2c_enable(i2c_base, true);
294 * i2c_setaddress - Sets the target slave address
295 * @i2c_addr: target i2c address
297 * Sets the target slave address.
299 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
302 dw_i2c_enable(i2c_base, false);
304 writel(i2c_addr, &i2c_base->ic_tar);
307 dw_i2c_enable(i2c_base, true);
311 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
313 * Flushes the i2c RX FIFO
315 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
317 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
318 readl(&i2c_base->ic_cmd_data);
322 * i2c_wait_for_bb - Waits for bus busy
326 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
328 unsigned long start_time_bb = get_timer(0);
330 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
331 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
333 /* Evaluate timeout */
334 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
341 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
344 if (i2c_wait_for_bb(i2c_base))
347 i2c_setaddress(i2c_base, chip);
350 /* high byte address going out first */
351 writel((addr >> (alen * 8)) & 0xff,
352 &i2c_base->ic_cmd_data);
357 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
359 ulong start_stop_det = get_timer(0);
362 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
363 readl(&i2c_base->ic_clr_stop_det);
365 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
370 if (i2c_wait_for_bb(i2c_base)) {
371 printf("Timed out waiting for bus\n");
375 i2c_flush_rxfifo(i2c_base);
381 * i2c_read - Read from i2c memory
382 * @chip: target i2c address
383 * @addr: address to read from
385 * @buffer: buffer for read data
386 * @len: no of bytes to be read
388 * Read from i2c memory.
390 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
391 int alen, u8 *buffer, int len)
393 unsigned long start_time_rx;
394 unsigned int active = 0;
396 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
398 * EEPROM chips that implement "address overflow" are ones
399 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
400 * address and the extra bits end up in the "chip address"
401 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
402 * four 256 byte chips.
404 * Note that we consider the length of the address field to
405 * still be one byte because the extra address bits are
406 * hidden in the chip address.
408 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
409 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
411 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
415 if (i2c_xfer_init(i2c_base, dev, addr, alen))
418 start_time_rx = get_timer(0);
422 * Avoid writing to ic_cmd_data multiple times
423 * in case this loop spins too quickly and the
424 * ic_status RFNE bit isn't set after the first
425 * write. Subsequent writes to ic_cmd_data can
426 * trigger spurious i2c transfer.
429 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
431 writel(IC_CMD, &i2c_base->ic_cmd_data);
435 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
436 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
438 start_time_rx = get_timer(0);
440 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
445 return i2c_xfer_finish(i2c_base);
449 * i2c_write - Write to i2c memory
450 * @chip: target i2c address
451 * @addr: address to read from
453 * @buffer: buffer for read data
454 * @len: no of bytes to be read
456 * Write to i2c memory.
458 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
459 int alen, u8 *buffer, int len)
462 unsigned long start_time_tx;
464 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
466 * EEPROM chips that implement "address overflow" are ones
467 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
468 * address and the extra bits end up in the "chip address"
469 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
470 * four 256 byte chips.
472 * Note that we consider the length of the address field to
473 * still be one byte because the extra address bits are
474 * hidden in the chip address.
476 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
477 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
479 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
483 if (i2c_xfer_init(i2c_base, dev, addr, alen))
486 start_time_tx = get_timer(0);
488 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
490 writel(*buffer | IC_STOP,
491 &i2c_base->ic_cmd_data);
493 writel(*buffer, &i2c_base->ic_cmd_data);
496 start_time_tx = get_timer(0);
498 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
499 printf("Timed out. i2c write Failed\n");
504 return i2c_xfer_finish(i2c_base);
508 * __dw_i2c_init - Init function
509 * @speed: required i2c speed
510 * @slaveaddr: slave address for the device
512 * Initialization function.
514 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
519 ret = dw_i2c_enable(i2c_base, false);
523 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
525 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
526 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
527 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
528 #ifndef CONFIG_DM_I2C
529 __dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
530 writel(slaveaddr, &i2c_base->ic_sar);
534 ret = dw_i2c_enable(i2c_base, true);
541 #ifndef CONFIG_DM_I2C
543 * The legacy I2C functions. These need to get removed once
544 * all users of this driver are converted to DM.
546 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
548 switch (adap->hwadapnr) {
549 #if CONFIG_SYS_I2C_BUS_MAX >= 4
551 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
553 #if CONFIG_SYS_I2C_BUS_MAX >= 3
555 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
557 #if CONFIG_SYS_I2C_BUS_MAX >= 2
559 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
562 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
564 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
570 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
574 return __dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
577 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
579 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
582 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
583 int alen, u8 *buffer, int len)
585 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
588 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
589 int alen, u8 *buffer, int len)
591 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
594 /* dw_i2c_probe - Probe the i2c chip */
595 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
597 struct i2c_regs *i2c_base = i2c_get_base(adap);
602 * Try to read the first location of the chip.
604 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
606 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
611 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
612 dw_i2c_write, dw_i2c_set_bus_speed,
613 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
615 #if CONFIG_SYS_I2C_BUS_MAX >= 2
616 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
617 dw_i2c_write, dw_i2c_set_bus_speed,
618 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
621 #if CONFIG_SYS_I2C_BUS_MAX >= 3
622 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
623 dw_i2c_write, dw_i2c_set_bus_speed,
624 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
627 #if CONFIG_SYS_I2C_BUS_MAX >= 4
628 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
629 dw_i2c_write, dw_i2c_set_bus_speed,
630 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
633 #else /* CONFIG_DM_I2C */
634 /* The DM I2C functions */
636 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
639 struct dw_i2c *i2c = dev_get_priv(bus);
642 debug("i2c_xfer: %d messages\n", nmsgs);
643 for (; nmsgs > 0; nmsgs--, msg++) {
644 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
645 if (msg->flags & I2C_M_RD) {
646 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
649 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
653 debug("i2c_write: error sending\n");
661 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
663 struct dw_i2c *i2c = dev_get_priv(bus);
666 #if CONFIG_IS_ENABLED(CLK)
667 rate = clk_get_rate(&i2c->clk);
668 if (IS_ERR_VALUE(rate))
673 return __dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
676 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
679 struct dw_i2c *i2c = dev_get_priv(bus);
680 struct i2c_regs *i2c_base = i2c->regs;
684 /* Try to read the first location of the chip */
685 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
687 __dw_i2c_init(i2c_base, 0, 0);
692 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
694 struct dw_i2c *priv = dev_get_priv(bus);
697 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
698 dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
699 dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
700 dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
705 int designware_i2c_probe(struct udevice *bus)
707 struct dw_i2c *priv = dev_get_priv(bus);
710 ret = reset_get_bulk(bus, &priv->resets);
712 dev_warn(bus, "Can't get reset: %d\n", ret);
714 reset_deassert_bulk(&priv->resets);
716 #if CONFIG_IS_ENABLED(CLK)
717 ret = clk_get_by_index(bus, 0, &priv->clk);
721 ret = clk_enable(&priv->clk);
722 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
723 clk_free(&priv->clk);
724 dev_err(bus, "failed to enable clock\n");
729 return __dw_i2c_init(priv->regs, 0, 0);
732 int designware_i2c_remove(struct udevice *dev)
734 struct dw_i2c *priv = dev_get_priv(dev);
736 #if CONFIG_IS_ENABLED(CLK)
737 clk_disable(&priv->clk);
738 clk_free(&priv->clk);
741 return reset_release_bulk(&priv->resets);
744 const struct dm_i2c_ops designware_i2c_ops = {
745 .xfer = designware_i2c_xfer,
746 .probe_chip = designware_i2c_probe_chip,
747 .set_bus_speed = designware_i2c_set_bus_speed,
750 static const struct udevice_id designware_i2c_ids[] = {
751 { .compatible = "snps,designware-i2c" },
755 U_BOOT_DRIVER(i2c_designware) = {
756 .name = "i2c_designware",
758 .of_match = designware_i2c_ids,
759 .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
760 .probe = designware_i2c_probe,
761 .priv_auto_alloc_size = sizeof(struct dw_i2c),
762 .remove = designware_i2c_remove,
763 .flags = DM_FLAG_OS_PREPARE,
764 .ops = &designware_i2c_ops,
767 #endif /* CONFIG_DM_I2C */