2 * TI DaVinci (TMS320DM644x) I2C driver.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * --------------------------------------------------------
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/hardware.h>
30 #include <asm/arch/i2c_defs.h>
32 #define CHECK_NACK() \
34 if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
41 static int wait_for_bus(void)
45 REG(I2C_STAT) = 0xffff;
47 for (timeout = 0; timeout < 10; timeout++) {
48 if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) {
49 REG(I2C_STAT) = 0xffff;
57 REG(I2C_STAT) = 0xffff;
62 static int poll_i2c_irq(int mask)
66 for (timeout = 0; timeout < 10; timeout++) {
74 REG(I2C_STAT) = 0xffff;
75 return(stat | I2C_TIMEOUT);
84 if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
88 REG(I2C_STAT) = I2C_STAT_RRDY;
94 void i2c_init(int speed, int slaveadd)
98 if (REG(I2C_CON) & I2C_CON_EN) {
104 div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
105 REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */
106 REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */
107 REG(I2C_SCLH) = div - REG(I2C_SCLL);
109 REG(I2C_OA) = slaveadd;
112 /* Interrupts must be enabled or I2C module won't work */
113 REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
114 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
116 /* Now enable I2C controller (get it out of reset) */
117 REG(I2C_CON) = I2C_CON_EN;
122 int i2c_set_bus_speed(unsigned int speed)
124 i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
128 int i2c_probe(u_int8_t chip)
132 if (chip == REG(I2C_OA)) {
137 if (wait_for_bus()) {return(1);}
139 /* try to read one byte from current (or only) address */
142 REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP);
145 if (!(REG(I2C_STAT) & I2C_STAT_NACK)) {
148 REG(I2C_STAT) = 0xffff;
150 REG(I2C_STAT) = 0xffff;
151 REG(I2C_CON) |= I2C_CON_STP;
153 if (wait_for_bus()) {return(1);}
157 REG(I2C_STAT) = 0xffff;
163 int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
168 if ((alen < 0) || (alen > 2)) {
169 printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
173 if (wait_for_bus()) {return(1);}
176 /* Start address phase */
177 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
182 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
188 /* Send address MSByte */
189 if (tmp & I2C_STAT_XRDY) {
190 REG(I2C_DXR) = (addr >> 8) & 0xff;
196 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
199 /* No break, fall through */
201 /* Send address LSByte */
202 if (tmp & I2C_STAT_XRDY) {
203 REG(I2C_DXR) = addr & 0xff;
209 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY);
213 if (!(tmp & I2C_STAT_ARDY)) {
220 /* Address phase is over, now read 'len' bytes and stop */
221 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
222 REG(I2C_CNT) = len & 0xffff;
226 for (i = 0; i < len; i++) {
227 tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR);
231 if (tmp & I2C_STAT_RRDY) {
232 buf[i] = REG(I2C_DRR);
239 tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
243 if (!(tmp & I2C_STAT_SCD)) {
249 REG(I2C_STAT) = 0xffff;
257 int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
262 if ((alen < 0) || (alen > 2)) {
263 printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
267 printf("%s(): bogus length %x\n", __FUNCTION__, len);
271 if (wait_for_bus()) {return(1);}
273 /* Start address phase */
274 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP;
275 REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen;
281 /* Send address MSByte */
282 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
286 if (tmp & I2C_STAT_XRDY) {
287 REG(I2C_DXR) = (addr >> 8) & 0xff;
292 /* No break, fall through */
294 /* Send address LSByte */
295 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
299 if (tmp & I2C_STAT_XRDY) {
300 REG(I2C_DXR) = addr & 0xff;
307 for (i = 0; i < len; i++) {
308 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
312 if (tmp & I2C_STAT_XRDY) {
313 REG(I2C_DXR) = buf[i];
319 tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
323 if (!(tmp & I2C_STAT_SCD)) {
329 REG(I2C_STAT) = 0xffff;