drivers/i2c/busses/i2c-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * drivers/i2c/busses/i2c-tegra.c
   4  *
   5  * Copyright (C) 2010 Google, Inc.
   6  * Author: Colin Cross <ccross@android.com>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/i2c.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/of_device.h>
  22 #include <linux/pinctrl/consumer.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/reset.h>
  26
  27 #define BYTES_PER_FIFO_WORD 4
  28
  29 #define I2C_CNFG                                0x000
  30 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  31 #define I2C_CNFG_PACKET_MODE_EN                 BIT(10)
  32 #define I2C_CNFG_NEW_MASTER_FSM                 BIT(11)
  33 #define I2C_CNFG_MULTI_MASTER_MODE              BIT(17)
  34 #define I2C_STATUS                              0x01C
  35 #define I2C_SL_CNFG                             0x020
  36 #define I2C_SL_CNFG_NACK                        BIT(1)
  37 #define I2C_SL_CNFG_NEWSL                       BIT(2)
  38 #define I2C_SL_ADDR1                            0x02c
  39 #define I2C_SL_ADDR2                            0x030
  40 #define I2C_TX_FIFO                             0x050
  41 #define I2C_RX_FIFO                             0x054
  42 #define I2C_PACKET_TRANSFER_STATUS              0x058
  43 #define I2C_FIFO_CONTROL                        0x05c
  44 #define I2C_FIFO_CONTROL_TX_FLUSH               BIT(1)
  45 #define I2C_FIFO_CONTROL_RX_FLUSH               BIT(0)
  46 #define I2C_FIFO_CONTROL_TX_TRIG(x)             (((x) - 1) << 5)
  47 #define I2C_FIFO_CONTROL_RX_TRIG(x)             (((x) - 1) << 2)
  48 #define I2C_FIFO_STATUS                         0x060
  49 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  50 #define I2C_FIFO_STATUS_TX_SHIFT                4
  51 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  52 #define I2C_FIFO_STATUS_RX_SHIFT                0
  53 #define I2C_INT_MASK                            0x064
  54 #define I2C_INT_STATUS                          0x068
  55 #define I2C_INT_BUS_CLR_DONE                    BIT(11)
  56 #define I2C_INT_PACKET_XFER_COMPLETE            BIT(7)
  57 #define I2C_INT_NO_ACK                          BIT(3)
  58 #define I2C_INT_ARBITRATION_LOST                BIT(2)
  59 #define I2C_INT_TX_FIFO_DATA_REQ                BIT(1)
  60 #define I2C_INT_RX_FIFO_DATA_REQ                BIT(0)
  61 #define I2C_CLK_DIVISOR                         0x06c
  62 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  63
  64 #define DVC_CTRL_REG1                           0x000
  65 #define DVC_CTRL_REG1_INTR_EN                   BIT(10)
  66 #define DVC_CTRL_REG3                           0x008
  67 #define DVC_CTRL_REG3_SW_PROG                   BIT(26)
  68 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          BIT(30)
  69 #define DVC_STATUS                              0x00c
  70 #define DVC_STATUS_I2C_DONE_INTR                BIT(30)
  71
  72 #define I2C_ERR_NONE                            0x00
  73 #define I2C_ERR_NO_ACK                          BIT(0)
  74 #define I2C_ERR_ARBITRATION_LOST                BIT(1)
  75 #define I2C_ERR_UNKNOWN_INTERRUPT               BIT(2)
  76 #define I2C_ERR_RX_BUFFER_OVERFLOW              BIT(3)
  77
  78 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  79 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  80 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  81 #define PACKET_HEADER0_PROTOCOL_I2C             BIT(4)
  82
  83 #define I2C_HEADER_CONT_ON_NAK                  BIT(21)
  84 #define I2C_HEADER_READ                         BIT(19)
  85 #define I2C_HEADER_10BIT_ADDR                   BIT(18)
  86 #define I2C_HEADER_IE_ENABLE                    BIT(17)
  87 #define I2C_HEADER_REPEAT_START                 BIT(16)
  88 #define I2C_HEADER_CONTINUE_XFER                BIT(15)
  89 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
  90
  91 #define I2C_BUS_CLEAR_CNFG                      0x084
  92 #define I2C_BC_SCLK_THRESHOLD                   9
  93 #define I2C_BC_SCLK_THRESHOLD_SHIFT             16
  94 #define I2C_BC_STOP_COND                        BIT(2)
  95 #define I2C_BC_TERMINATE                        BIT(1)
  96 #define I2C_BC_ENABLE                           BIT(0)
  97 #define I2C_BUS_CLEAR_STATUS                    0x088
  98 #define I2C_BC_STATUS                           BIT(0)
  99
 100 #define I2C_CONFIG_LOAD                         0x08C
 101 #define I2C_MSTR_CONFIG_LOAD                    BIT(0)
 102
 103 #define I2C_CLKEN_OVERRIDE                      0x090
 104 #define I2C_MST_CORE_CLKEN_OVR                  BIT(0)
 105
 106 #define I2C_CONFIG_LOAD_TIMEOUT                 1000000
 107
 108 #define I2C_MST_FIFO_CONTROL                    0x0b4
 109 #define I2C_MST_FIFO_CONTROL_RX_FLUSH           BIT(0)
 110 #define I2C_MST_FIFO_CONTROL_TX_FLUSH           BIT(1)
 111 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x)         (((x) - 1) <<  4)
 112 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x)         (((x) - 1) << 16)
 113
 114 #define I2C_MST_FIFO_STATUS                     0x0b8
 115 #define I2C_MST_FIFO_STATUS_RX_MASK             0xff
 116 #define I2C_MST_FIFO_STATUS_RX_SHIFT            0
 117 #define I2C_MST_FIFO_STATUS_TX_MASK             0xff0000
 118 #define I2C_MST_FIFO_STATUS_TX_SHIFT            16
 119
 120 #define I2C_INTERFACE_TIMING_0                  0x94
 121 #define I2C_THIGH_SHIFT                         8
 122 #define I2C_INTERFACE_TIMING_1                  0x98
 123
 124 #define I2C_STANDARD_MODE                       100000
 125 #define I2C_FAST_MODE                           400000
 126 #define I2C_FAST_PLUS_MODE                      1000000
 127
 128 /* Packet header size in bytes */
 129 #define I2C_PACKET_HEADER_SIZE                  12
 130
 131 /*
 132  * Upto I2C_PIO_MODE_MAX_LEN bytes, controller will use PIO mode,
 133  * above this, controller will use DMA to fill FIFO.
 134  * MAX PIO len is 20 bytes excluding packet header.
 135  */
 136 #define I2C_PIO_MODE_MAX_LEN                    32
 137
 138 /*
 139  * msg_end_type: The bus control which need to be send at end of transfer.
 140  * @MSG_END_STOP: Send stop pulse at end of transfer.
 141  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 142  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 143  *              stop or repeat start.
 144  */
 145 enum msg_end_type {
 146         MSG_END_STOP,
 147         MSG_END_REPEAT_START,
 148         MSG_END_CONTINUE,
 149 };
 150
 151 /**
 152  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 153  * @has_continue_xfer_support: Continue transfer supports.
 154  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 155  *              complete interrupt per packet basis.
 156  * @has_single_clk_source: The I2C controller has single clock source. Tegra30
 157  *              and earlier SoCs have two clock sources i.e. div-clk and
 158  *              fast-clk.
 159  * @has_config_load_reg: Has the config load register to load the new
 160  *              configuration.
 161  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 162  * @clk_divisor_std_mode: Clock divisor in standard mode. It is
 163  *              applicable if there is no fast clock source i.e. single clock
 164  *              source.
 165  * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
 166  *              applicable if there is no fast clock source i.e. single clock
 167  *              source.
 168  * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
 169  *              applicable if there is no fast clock source (i.e. single
 170  *              clock source).
 171  * @has_multi_master_mode: The I2C controller supports running in single-master
 172  *              or multi-master mode.
 173  * @has_slcg_override_reg: The I2C controller supports a register that
 174  *              overrides the second level clock gating.
 175  * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
 176  *              provides additional features and allows for longer messages to
 177  *              be transferred in one go.
 178  * @quirks: i2c adapter quirks for limiting write/read transfer size and not
 179  *              allowing 0 length transfers.
 180  * @supports_bus_clear: Bus Clear support to recover from bus hang during
 181  *              SDA stuck low from device for some unknown reasons.
 182  * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
 183  * @tlow_std_mode: Low period of the clock in standard mode.
 184  * @thigh_std_mode: High period of the clock in standard mode.
 185  * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
 186  * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
 187  * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
 188  *              in standard mode.
 189  * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
 190  *              conditions in fast/fast-plus modes.
 191  * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
 192  *              in HS mode.
 193  * @has_interface_timing_reg: Has interface timing register to program the tuned
 194  *              timing settings.
 195  */
 196 struct tegra_i2c_hw_feature {
 197         bool has_continue_xfer_support;
 198         bool has_per_pkt_xfer_complete_irq;
 199         bool has_single_clk_source;
 200         bool has_config_load_reg;
 201         int clk_divisor_hs_mode;
 202         int clk_divisor_std_mode;
 203         int clk_divisor_fast_mode;
 204         u16 clk_divisor_fast_plus_mode;
 205         bool has_multi_master_mode;
 206         bool has_slcg_override_reg;
 207         bool has_mst_fifo;
 208         const struct i2c_adapter_quirks *quirks;
 209         bool supports_bus_clear;
 210         bool has_apb_dma;
 211         u8 tlow_std_mode;
 212         u8 thigh_std_mode;
 213         u8 tlow_fast_fastplus_mode;
 214         u8 thigh_fast_fastplus_mode;
 215         u32 setup_hold_time_std_mode;
 216         u32 setup_hold_time_fast_fast_plus_mode;
 217         u32 setup_hold_time_hs_mode;
 218         bool has_interface_timing_reg;
 219 };
 220
 221 /**
 222  * struct tegra_i2c_dev - per device I2C context
 223  * @dev: device reference for power management
 224  * @hw: Tegra I2C HW feature
 225  * @adapter: core I2C layer adapter information
 226  * @div_clk: clock reference for div clock of I2C controller
 227  * @fast_clk: clock reference for fast clock of I2C controller
 228  * @rst: reset control for the I2C controller
 229  * @base: ioremapped registers cookie
 230  * @base_phys: physical base address of the I2C controller
 231  * @cont_id: I2C controller ID, used for packet header
 232  * @irq: IRQ number of transfer complete interrupt
 233  * @irq_disabled: used to track whether or not the interrupt is enabled
 234  * @is_dvc: identifies the DVC I2C controller, has a different register layout
 235  * @msg_complete: transfer completion notifier
 236  * @msg_err: error code for completed message
 237  * @msg_buf: pointer to current message data
 238  * @msg_buf_remaining: size of unsent data in the message buffer
 239  * @msg_read: identifies read transfers
 240  * @bus_clk_rate: current I2C bus clock rate
 241  * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
 242  * @is_multimaster_mode: track if I2C controller is in multi-master mode
 243  * @xfer_lock: lock to serialize transfer submission and processing
 244  * @tx_dma_chan: DMA transmit channel
 245  * @rx_dma_chan: DMA receive channel
 246  * @dma_phys: handle to DMA resources
 247  * @dma_buf: pointer to allocated DMA buffer
 248  * @dma_buf_size: DMA buffer size
 249  * @is_curr_dma_xfer: indicates active DMA transfer
 250  * @dma_complete: DMA completion notifier
 251  */
 252 struct tegra_i2c_dev {
 253         struct device *dev;
 254         const struct tegra_i2c_hw_feature *hw;
 255         struct i2c_adapter adapter;
 256         struct clk *div_clk;
 257         struct clk *fast_clk;
 258         struct reset_control *rst;
 259         void __iomem *base;
 260         phys_addr_t base_phys;
 261         int cont_id;
 262         int irq;
 263         bool irq_disabled;
 264         int is_dvc;
 265         struct completion msg_complete;
 266         int msg_err;
 267         u8 *msg_buf;
 268         size_t msg_buf_remaining;
 269         int msg_read;
 270         u32 bus_clk_rate;
 271         u16 clk_divisor_non_hs_mode;
 272         bool is_multimaster_mode;
 273         /* xfer_lock: lock to serialize transfer submission and processing */
 274         spinlock_t xfer_lock;
 275         struct dma_chan *tx_dma_chan;
 276         struct dma_chan *rx_dma_chan;
 277         dma_addr_t dma_phys;
 278         u32 *dma_buf;
 279         unsigned int dma_buf_size;
 280         bool is_curr_dma_xfer;
 281         struct completion dma_complete;
 282 };
 283
 284 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 285                        unsigned long reg)
 286 {
 287         writel(val, i2c_dev->base + reg);
 288 }
 289
 290 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 291 {
 292         return readl(i2c_dev->base + reg);
 293 }
 294
 295 /*
 296  * i2c_writel and i2c_readl will offset the register if necessary to talk
 297  * to the I2C block inside the DVC block
 298  */
 299 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 300                                         unsigned long reg)
 301 {
 302         if (i2c_dev->is_dvc)
 303                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 304         return reg;
 305 }
 306
 307 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 308                        unsigned long reg)
 309 {
 310         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 311
 312         /* Read back register to make sure that register writes completed */
 313         if (reg != I2C_TX_FIFO)
 314                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 315 }
 316
 317 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 318 {
 319         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 320 }
 321
 322 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 323                         unsigned long reg, int len)
 324 {
 325         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 326 }
 327
 328 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 329                        unsigned long reg, int len)
 330 {
 331         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 332 }
 333
 334 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 335 {
 336         u32 int_mask;
 337
 338         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
 339         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 340 }
 341
 342 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 343 {
 344         u32 int_mask;
 345
 346         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
 347         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 348 }
 349
 350 static void tegra_i2c_dma_complete(void *args)
 351 {
 352         struct tegra_i2c_dev *i2c_dev = args;
 353
 354         complete(&i2c_dev->dma_complete);
 355 }
 356
 357 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
 358 {
 359         struct dma_async_tx_descriptor *dma_desc;
 360         enum dma_transfer_direction dir;
 361         struct dma_chan *chan;
 362
 363         dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
 364         reinit_completion(&i2c_dev->dma_complete);
 365         dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
 366         chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
 367         dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
 368                                                len, dir, DMA_PREP_INTERRUPT |
 369                                                DMA_CTRL_ACK);
 370         if (!dma_desc) {
 371                 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n");
 372                 return -EINVAL;
 373         }
 374
 375         dma_desc->callback = tegra_i2c_dma_complete;
 376         dma_desc->callback_param = i2c_dev;
 377         dmaengine_submit(dma_desc);
 378         dma_async_issue_pending(chan);
 379         return 0;
 380 }
 381
 382 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
 383 {
 384         if (i2c_dev->dma_buf) {
 385                 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
 386                                   i2c_dev->dma_buf, i2c_dev->dma_phys);
 387                 i2c_dev->dma_buf = NULL;
 388         }
 389
 390         if (i2c_dev->tx_dma_chan) {
 391                 dma_release_channel(i2c_dev->tx_dma_chan);
 392                 i2c_dev->tx_dma_chan = NULL;
 393         }
 394
 395         if (i2c_dev->rx_dma_chan) {
 396                 dma_release_channel(i2c_dev->rx_dma_chan);
 397                 i2c_dev->rx_dma_chan = NULL;
 398         }
 399 }
 400
 401 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
 402 {
 403         struct dma_chan *chan;
 404         u32 *dma_buf;
 405         dma_addr_t dma_phys;
 406         int err;
 407
 408         if (!i2c_dev->hw->has_apb_dma)
 409                 return 0;
 410
 411         if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
 412                 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n");
 413                 return 0;
 414         }
 415
 416         chan = dma_request_slave_channel_reason(i2c_dev->dev, "rx");
 417         if (IS_ERR(chan)) {
 418                 err = PTR_ERR(chan);
 419                 goto err_out;
 420         }
 421
 422         i2c_dev->rx_dma_chan = chan;
 423
 424         chan = dma_request_slave_channel_reason(i2c_dev->dev, "tx");
 425         if (IS_ERR(chan)) {
 426                 err = PTR_ERR(chan);
 427                 goto err_out;
 428         }
 429
 430         i2c_dev->tx_dma_chan = chan;
 431
 432         dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
 433                                      &dma_phys, GFP_KERNEL | __GFP_NOWARN);
 434         if (!dma_buf) {
 435                 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n");
 436                 err = -ENOMEM;
 437                 goto err_out;
 438         }
 439
 440         i2c_dev->dma_buf = dma_buf;
 441         i2c_dev->dma_phys = dma_phys;
 442         return 0;
 443
 444 err_out:
 445         tegra_i2c_release_dma(i2c_dev);
 446         if (err != -EPROBE_DEFER) {
 447                 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
 448                 dev_err(i2c_dev->dev, "falling back to PIO\n");
 449                 return 0;
 450         }
 451
 452         return err;
 453 }
 454
 455 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 456 {
 457         unsigned long timeout = jiffies + HZ;
 458         unsigned int offset;
 459         u32 mask, val;
 460
 461         if (i2c_dev->hw->has_mst_fifo) {
 462                 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
 463                        I2C_MST_FIFO_CONTROL_RX_FLUSH;
 464                 offset = I2C_MST_FIFO_CONTROL;
 465         } else {
 466                 mask = I2C_FIFO_CONTROL_TX_FLUSH |
 467                        I2C_FIFO_CONTROL_RX_FLUSH;
 468                 offset = I2C_FIFO_CONTROL;
 469         }
 470
 471         val = i2c_readl(i2c_dev, offset);
 472         val |= mask;
 473         i2c_writel(i2c_dev, val, offset);
 474
 475         while (i2c_readl(i2c_dev, offset) & mask) {
 476                 if (time_after(jiffies, timeout)) {
 477                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 478                         return -ETIMEDOUT;
 479                 }
 480                 usleep_range(1000, 2000);
 481         }
 482         return 0;
 483 }
 484
 485 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 486 {
 487         u32 val;
 488         int rx_fifo_avail;
 489         u8 *buf = i2c_dev->msg_buf;
 490         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 491         int words_to_transfer;
 492
 493         /*
 494          * Catch overflow due to message fully sent
 495          * before the check for RX FIFO availability.
 496          */
 497         if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
 498                 return -EINVAL;
 499
 500         if (i2c_dev->hw->has_mst_fifo) {
 501                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 502                 rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >>
 503                         I2C_MST_FIFO_STATUS_RX_SHIFT;
 504         } else {
 505                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 506                 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 507                         I2C_FIFO_STATUS_RX_SHIFT;
 508         }
 509
 510         /* Rounds down to not include partial word at the end of buf */
 511         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 512         if (words_to_transfer > rx_fifo_avail)
 513                 words_to_transfer = rx_fifo_avail;
 514
 515         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 516
 517         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 518         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 519         rx_fifo_avail -= words_to_transfer;
 520
 521         /*
 522          * If there is a partial word at the end of buf, handle it manually to
 523          * prevent overwriting past the end of buf
 524          */
 525         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 526                 /*
 527                  * buf_remaining > 3 check not needed as rx_fifo_avail == 0
 528                  * when (words_to_transfer was > rx_fifo_avail) earlier
 529                  * in this function.
 530                  */
 531                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 532                 val = cpu_to_le32(val);
 533                 memcpy(buf, &val, buf_remaining);
 534                 buf_remaining = 0;
 535                 rx_fifo_avail--;
 536         }
 537
 538         /* RX FIFO must be drained, otherwise it's an Overflow case. */
 539         if (WARN_ON_ONCE(rx_fifo_avail))
 540                 return -EINVAL;
 541
 542         i2c_dev->msg_buf_remaining = buf_remaining;
 543         i2c_dev->msg_buf = buf;
 544
 545         return 0;
 546 }
 547
 548 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 549 {
 550         u32 val;
 551         int tx_fifo_avail;
 552         u8 *buf = i2c_dev->msg_buf;
 553         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 554         int words_to_transfer;
 555
 556         if (i2c_dev->hw->has_mst_fifo) {
 557                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 558                 tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >>
 559                         I2C_MST_FIFO_STATUS_TX_SHIFT;
 560         } else {
 561                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 562                 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 563                         I2C_FIFO_STATUS_TX_SHIFT;
 564         }
 565
 566         /* Rounds down to not include partial word at the end of buf */
 567         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 568
 569         /* It's very common to have < 4 bytes, so optimize that case. */
 570         if (words_to_transfer) {
 571                 if (words_to_transfer > tx_fifo_avail)
 572                         words_to_transfer = tx_fifo_avail;
 573
 574                 /*
 575                  * Update state before writing to FIFO.  If this casues us
 576                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 577                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 578                  * not maskable).  We need to make sure that the isr sees
 579                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 580                  */
 581                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 582                 tx_fifo_avail -= words_to_transfer;
 583                 i2c_dev->msg_buf_remaining = buf_remaining;
 584                 i2c_dev->msg_buf = buf +
 585                         words_to_transfer * BYTES_PER_FIFO_WORD;
 586                 barrier();
 587
 588                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 589
 590                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 591         }
 592
 593         /*
 594          * If there is a partial word at the end of buf, handle it manually to
 595          * prevent reading past the end of buf, which could cross a page
 596          * boundary and fault.
 597          */
 598         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 599                 /*
 600                  * buf_remaining > 3 check not needed as tx_fifo_avail == 0
 601                  * when (words_to_transfer was > tx_fifo_avail) earlier
 602                  * in this function for non-zero words_to_transfer.
 603                  */
 604                 memcpy(&val, buf, buf_remaining);
 605                 val = le32_to_cpu(val);
 606
 607                 /* Again update before writing to FIFO to make sure isr sees. */
 608                 i2c_dev->msg_buf_remaining = 0;
 609                 i2c_dev->msg_buf = NULL;
 610                 barrier();
 611
 612                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 613         }
 614
 615         return 0;
 616 }
 617
 618 /*
 619  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 620  * block.  This block is identical to the rest of the I2C blocks, except that
 621  * it only supports master mode, it has registers moved around, and it needs
 622  * some extra init to get it into I2C mode.  The register moves are handled
 623  * by i2c_readl and i2c_writel
 624  */
 625 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 626 {
 627         u32 val;
 628
 629         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 630         val |= DVC_CTRL_REG3_SW_PROG;
 631         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 632         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 633
 634         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 635         val |= DVC_CTRL_REG1_INTR_EN;
 636         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 637 }
 638
 639 static int tegra_i2c_runtime_resume(struct device *dev)
 640 {
 641         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 642         int ret;
 643
 644         ret = pinctrl_pm_select_default_state(i2c_dev->dev);
 645         if (ret)
 646                 return ret;
 647
 648         if (!i2c_dev->hw->has_single_clk_source) {
 649                 ret = clk_enable(i2c_dev->fast_clk);
 650                 if (ret < 0) {
 651                         dev_err(i2c_dev->dev,
 652                                 "Enabling fast clk failed, err %d\n", ret);
 653                         return ret;
 654                 }
 655         }
 656
 657         ret = clk_enable(i2c_dev->div_clk);
 658         if (ret < 0) {
 659                 dev_err(i2c_dev->dev,
 660                         "Enabling div clk failed, err %d\n", ret);
 661                 clk_disable(i2c_dev->fast_clk);
 662                 return ret;
 663         }
 664
 665         return 0;
 666 }
 667
 668 static int tegra_i2c_runtime_suspend(struct device *dev)
 669 {
 670         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 671
 672         clk_disable(i2c_dev->div_clk);
 673         if (!i2c_dev->hw->has_single_clk_source)
 674                 clk_disable(i2c_dev->fast_clk);
 675
 676         return pinctrl_pm_select_idle_state(i2c_dev->dev);
 677 }
 678
 679 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
 680 {
 681         unsigned long reg_offset;
 682         void __iomem *addr;
 683         u32 val;
 684         int err;
 685
 686         if (i2c_dev->hw->has_config_load_reg) {
 687                 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
 688                 addr = i2c_dev->base + reg_offset;
 689                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 690                 if (in_interrupt())
 691                         err = readl_poll_timeout_atomic(addr, val, val == 0,
 692                                                         1000,
 693                                                         I2C_CONFIG_LOAD_TIMEOUT);
 694                 else
 695                         err = readl_poll_timeout(addr, val, val == 0, 1000,
 696                                                  I2C_CONFIG_LOAD_TIMEOUT);
 697
 698                 if (err) {
 699                         dev_warn(i2c_dev->dev,
 700                                  "timeout waiting for config load\n");
 701                         return err;
 702                 }
 703         }
 704
 705         return 0;
 706 }
 707
 708 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
 709 {
 710         u32 val;
 711         int err;
 712         u32 clk_divisor, clk_multiplier;
 713         u32 tsu_thd;
 714         u8 tlow, thigh;
 715
 716         reset_control_assert(i2c_dev->rst);
 717         udelay(2);
 718         reset_control_deassert(i2c_dev->rst);
 719
 720         if (i2c_dev->is_dvc)
 721                 tegra_dvc_init(i2c_dev);
 722
 723         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 724                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 725
 726         if (i2c_dev->hw->has_multi_master_mode)
 727                 val |= I2C_CNFG_MULTI_MASTER_MODE;
 728
 729         i2c_writel(i2c_dev, val, I2C_CNFG);
 730         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 731
 732         /* Make sure clock divisor programmed correctly */
 733         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 734         clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
 735                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 736         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 737
 738         if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE &&
 739             i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) {
 740                 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
 741                 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
 742                 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
 743         } else {
 744                 tlow = i2c_dev->hw->tlow_std_mode;
 745                 thigh = i2c_dev->hw->thigh_std_mode;
 746                 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
 747         }
 748
 749         if (i2c_dev->hw->has_interface_timing_reg) {
 750                 val = (thigh << I2C_THIGH_SHIFT) | tlow;
 751                 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
 752         }
 753
 754         /*
 755          * configure setup and hold times only when tsu_thd is non-zero.
 756          * otherwise, preserve the chip default values
 757          */
 758         if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
 759                 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
 760
 761         if (!clk_reinit) {
 762                 clk_multiplier = (tlow + thigh + 2);
 763                 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
 764                 err = clk_set_rate(i2c_dev->div_clk,
 765                                    i2c_dev->bus_clk_rate * clk_multiplier);
 766                 if (err) {
 767                         dev_err(i2c_dev->dev,
 768                                 "failed changing clock rate: %d\n", err);
 769                         return err;
 770                 }
 771         }
 772
 773         if (!i2c_dev->is_dvc) {
 774                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 775
 776                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 777                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 778                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 779                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 780         }
 781
 782         err = tegra_i2c_flush_fifos(i2c_dev);
 783         if (err)
 784                 return err;
 785
 786         if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 787                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 788
 789         err = tegra_i2c_wait_for_config_load(i2c_dev);
 790         if (err)
 791                 return err;
 792
 793         if (i2c_dev->irq_disabled) {
 794                 i2c_dev->irq_disabled = false;
 795                 enable_irq(i2c_dev->irq);
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
 802 {
 803         u32 cnfg;
 804
 805         /*
 806          * NACK interrupt is generated before the I2C controller generates
 807          * the STOP condition on the bus. So wait for 2 clock periods
 808          * before disabling the controller so that the STOP condition has
 809          * been delivered properly.
 810          */
 811         udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 812
 813         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
 814         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
 815                 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
 816
 817         return tegra_i2c_wait_for_config_load(i2c_dev);
 818 }
 819
 820 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 821 {
 822         u32 status;
 823         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 824         struct tegra_i2c_dev *i2c_dev = dev_id;
 825
 826         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 827
 828         spin_lock(&i2c_dev->xfer_lock);
 829         if (status == 0) {
 830                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 831                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 832                          i2c_readl(i2c_dev, I2C_STATUS),
 833                          i2c_readl(i2c_dev, I2C_CNFG));
 834                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 835
 836                 if (!i2c_dev->irq_disabled) {
 837                         disable_irq_nosync(i2c_dev->irq);
 838                         i2c_dev->irq_disabled = true;
 839                 }
 840                 goto err;
 841         }
 842
 843         if (unlikely(status & status_err)) {
 844                 tegra_i2c_disable_packet_mode(i2c_dev);
 845                 if (status & I2C_INT_NO_ACK)
 846                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 847                 if (status & I2C_INT_ARBITRATION_LOST)
 848                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 849                 goto err;
 850         }
 851
 852         /*
 853          * I2C transfer is terminated during the bus clear so skip
 854          * processing the other interrupts.
 855          */
 856         if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
 857                 goto err;
 858
 859         if (!i2c_dev->is_curr_dma_xfer) {
 860                 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 861                         if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
 862                                 /*
 863                                  * Overflow error condition: message fully sent,
 864                                  * with no XFER_COMPLETE interrupt but hardware
 865                                  * asks to transfer more.
 866                                  */
 867                                 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
 868                                 goto err;
 869                         }
 870                 }
 871
 872                 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 873                         if (i2c_dev->msg_buf_remaining)
 874                                 tegra_i2c_fill_tx_fifo(i2c_dev);
 875                         else
 876                                 tegra_i2c_mask_irq(i2c_dev,
 877                                                    I2C_INT_TX_FIFO_DATA_REQ);
 878                 }
 879         }
 880
 881         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 882         if (i2c_dev->is_dvc)
 883                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 884
 885         /*
 886          * During message read XFER_COMPLETE interrupt is triggered prior to
 887          * DMA completion and during message write XFER_COMPLETE interrupt is
 888          * triggered after DMA completion.
 889          * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer.
 890          * so forcing msg_buf_remaining to 0 in DMA mode.
 891          */
 892         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 893                 if (i2c_dev->is_curr_dma_xfer)
 894                         i2c_dev->msg_buf_remaining = 0;
 895                 /*
 896                  * Underflow error condition: XFER_COMPLETE before message
 897                  * fully sent.
 898                  */
 899                 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
 900                         i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 901                         goto err;
 902                 }
 903                 complete(&i2c_dev->msg_complete);
 904         }
 905         goto done;
 906 err:
 907         /* An error occurred, mask all interrupts */
 908         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 909                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 910                 I2C_INT_RX_FIFO_DATA_REQ);
 911         if (i2c_dev->hw->supports_bus_clear)
 912                 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
 913         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 914         if (i2c_dev->is_dvc)
 915                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 916
 917         if (i2c_dev->is_curr_dma_xfer) {
 918                 if (i2c_dev->msg_read)
 919                         dmaengine_terminate_async(i2c_dev->rx_dma_chan);
 920                 else
 921                         dmaengine_terminate_async(i2c_dev->tx_dma_chan);
 922
 923                 complete(&i2c_dev->dma_complete);
 924         }
 925
 926         complete(&i2c_dev->msg_complete);
 927 done:
 928         spin_unlock(&i2c_dev->xfer_lock);
 929         return IRQ_HANDLED;
 930 }
 931
 932 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
 933                                        size_t len)
 934 {
 935         u32 val, reg;
 936         u8 dma_burst;
 937         struct dma_slave_config slv_config = {0};
 938         struct dma_chan *chan;
 939         int ret;
 940         unsigned long reg_offset;
 941
 942         if (i2c_dev->hw->has_mst_fifo)
 943                 reg = I2C_MST_FIFO_CONTROL;
 944         else
 945                 reg = I2C_FIFO_CONTROL;
 946
 947         if (i2c_dev->is_curr_dma_xfer) {
 948                 if (len & 0xF)
 949                         dma_burst = 1;
 950                 else if (len & 0x10)
 951                         dma_burst = 4;
 952                 else
 953                         dma_burst = 8;
 954
 955                 if (i2c_dev->msg_read) {
 956                         chan = i2c_dev->rx_dma_chan;
 957                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
 958                         slv_config.src_addr = i2c_dev->base_phys + reg_offset;
 959                         slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 960                         slv_config.src_maxburst = dma_burst;
 961
 962                         if (i2c_dev->hw->has_mst_fifo)
 963                                 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
 964                         else
 965                                 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
 966                 } else {
 967                         chan = i2c_dev->tx_dma_chan;
 968                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
 969                         slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
 970                         slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 971                         slv_config.dst_maxburst = dma_burst;
 972
 973                         if (i2c_dev->hw->has_mst_fifo)
 974                                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
 975                         else
 976                                 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
 977                 }
 978
 979                 slv_config.device_fc = true;
 980                 ret = dmaengine_slave_config(chan, &slv_config);
 981                 if (ret < 0) {
 982                         dev_err(i2c_dev->dev, "DMA slave config failed: %d\n",
 983                                 ret);
 984                         dev_err(i2c_dev->dev, "falling back to PIO\n");
 985                         tegra_i2c_release_dma(i2c_dev);
 986                         i2c_dev->is_curr_dma_xfer = false;
 987                 } else {
 988                         goto out;
 989                 }
 990         }
 991
 992         if (i2c_dev->hw->has_mst_fifo)
 993                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
 994                       I2C_MST_FIFO_CONTROL_RX_TRIG(1);
 995         else
 996                 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
 997                       I2C_FIFO_CONTROL_RX_TRIG(1);
 998 out:
 999         i2c_writel(i2c_dev, val, reg);
1000 }
1001
1002 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1003 {
1004         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1005         int err;
1006         unsigned long time_left;
1007         u32 reg;
1008
1009         reinit_completion(&i2c_dev->msg_complete);
1010         reg = (I2C_BC_SCLK_THRESHOLD << I2C_BC_SCLK_THRESHOLD_SHIFT) |
1011               I2C_BC_STOP_COND | I2C_BC_TERMINATE;
1012         i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1013         if (i2c_dev->hw->has_config_load_reg) {
1014                 err = tegra_i2c_wait_for_config_load(i2c_dev);
1015                 if (err)
1016                         return err;
1017         }
1018
1019         reg |= I2C_BC_ENABLE;
1020         i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1021         tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1022
1023         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
1024                                                 msecs_to_jiffies(50));
1025         if (time_left == 0) {
1026                 dev_err(i2c_dev->dev, "timed out for bus clear\n");
1027                 return -ETIMEDOUT;
1028         }
1029
1030         reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1031         if (!(reg & I2C_BC_STATUS)) {
1032                 dev_err(i2c_dev->dev,
1033                         "un-recovered arbitration lost\n");
1034                 return -EIO;
1035         }
1036
1037         return -EAGAIN;
1038 }
1039
1040 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1041                               struct i2c_msg *msg,
1042                               enum msg_end_type end_state)
1043 {
1044         u32 packet_header;
1045         u32 int_mask;
1046         unsigned long time_left;
1047         unsigned long flags;
1048         size_t xfer_size;
1049         u32 *buffer = NULL;
1050         int err = 0;
1051         bool dma;
1052         u16 xfer_time = 100;
1053
1054         tegra_i2c_flush_fifos(i2c_dev);
1055
1056         i2c_dev->msg_buf = msg->buf;
1057         i2c_dev->msg_buf_remaining = msg->len;
1058         i2c_dev->msg_err = I2C_ERR_NONE;
1059         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
1060         reinit_completion(&i2c_dev->msg_complete);
1061
1062         if (i2c_dev->msg_read)
1063                 xfer_size = msg->len;
1064         else
1065                 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1066
1067         xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1068         i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_MAX_LEN) &&
1069                                     i2c_dev->dma_buf;
1070         tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1071         dma = i2c_dev->is_curr_dma_xfer;
1072         /*
1073          * Transfer time in mSec = Total bits / transfer rate
1074          * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1075          */
1076         xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1077                                         i2c_dev->bus_clk_rate);
1078         spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
1079
1080         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1081         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1082         if (dma) {
1083                 if (i2c_dev->msg_read) {
1084                         dma_sync_single_for_device(i2c_dev->dev,
1085                                                    i2c_dev->dma_phys,
1086                                                    xfer_size,
1087                                                    DMA_FROM_DEVICE);
1088                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1089                         if (err < 0) {
1090                                 dev_err(i2c_dev->dev,
1091                                         "starting RX DMA failed, err %d\n",
1092                                         err);
1093                                 goto unlock;
1094                         }
1095
1096                 } else {
1097                         dma_sync_single_for_cpu(i2c_dev->dev,
1098                                                 i2c_dev->dma_phys,
1099                                                 xfer_size,
1100                                                 DMA_TO_DEVICE);
1101                         buffer = i2c_dev->dma_buf;
1102                 }
1103         }
1104
1105         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
1106                         PACKET_HEADER0_PROTOCOL_I2C |
1107                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
1108                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
1109         if (dma && !i2c_dev->msg_read)
1110                 *buffer++ = packet_header;
1111         else
1112                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1113
1114         packet_header = msg->len - 1;
1115         if (dma && !i2c_dev->msg_read)
1116                 *buffer++ = packet_header;
1117         else
1118                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1119
1120         packet_header = I2C_HEADER_IE_ENABLE;
1121         if (end_state == MSG_END_CONTINUE)
1122                 packet_header |= I2C_HEADER_CONTINUE_XFER;
1123         else if (end_state == MSG_END_REPEAT_START)
1124                 packet_header |= I2C_HEADER_REPEAT_START;
1125         if (msg->flags & I2C_M_TEN) {
1126                 packet_header |= msg->addr;
1127                 packet_header |= I2C_HEADER_10BIT_ADDR;
1128         } else {
1129                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1130         }
1131         if (msg->flags & I2C_M_IGNORE_NAK)
1132                 packet_header |= I2C_HEADER_CONT_ON_NAK;
1133         if (msg->flags & I2C_M_RD)
1134                 packet_header |= I2C_HEADER_READ;
1135         if (dma && !i2c_dev->msg_read)
1136                 *buffer++ = packet_header;
1137         else
1138                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1139
1140         if (!i2c_dev->msg_read) {
1141                 if (dma) {
1142                         memcpy(buffer, msg->buf, msg->len);
1143                         dma_sync_single_for_device(i2c_dev->dev,
1144                                                    i2c_dev->dma_phys,
1145                                                    xfer_size,
1146                                                    DMA_TO_DEVICE);
1147                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1148                         if (err < 0) {
1149                                 dev_err(i2c_dev->dev,
1150                                         "starting TX DMA failed, err %d\n",
1151                                         err);
1152                                 goto unlock;
1153                         }
1154                 } else {
1155                         tegra_i2c_fill_tx_fifo(i2c_dev);
1156                 }
1157         }
1158
1159         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1160                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1161         if (!dma) {
1162                 if (msg->flags & I2C_M_RD)
1163                         int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1164                 else if (i2c_dev->msg_buf_remaining)
1165                         int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1166         }
1167
1168         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1169         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
1170                 i2c_readl(i2c_dev, I2C_INT_MASK));
1171
1172 unlock:
1173         spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
1174
1175         if (dma) {
1176                 if (err)
1177                         return err;
1178
1179                 time_left = wait_for_completion_timeout(&i2c_dev->dma_complete,
1180                                                         msecs_to_jiffies(xfer_time));
1181                 if (time_left == 0) {
1182                         dev_err(i2c_dev->dev, "DMA transfer timeout\n");
1183                         dmaengine_terminate_sync(i2c_dev->msg_read ?
1184                                                  i2c_dev->rx_dma_chan :
1185                                                  i2c_dev->tx_dma_chan);
1186                         tegra_i2c_init(i2c_dev, true);
1187                         return -ETIMEDOUT;
1188                 }
1189
1190                 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1191                         dma_sync_single_for_cpu(i2c_dev->dev,
1192                                                 i2c_dev->dma_phys,
1193                                                 xfer_size,
1194                                                 DMA_FROM_DEVICE);
1195                         memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf,
1196                                msg->len);
1197                 }
1198
1199                 if (i2c_dev->msg_err != I2C_ERR_NONE)
1200                         dmaengine_synchronize(i2c_dev->msg_read ?
1201                                               i2c_dev->rx_dma_chan :
1202                                               i2c_dev->tx_dma_chan);
1203         }
1204
1205         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
1206                                                 msecs_to_jiffies(xfer_time));
1207         tegra_i2c_mask_irq(i2c_dev, int_mask);
1208
1209         if (time_left == 0) {
1210                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
1211
1212                 tegra_i2c_init(i2c_dev, true);
1213                 return -ETIMEDOUT;
1214         }
1215
1216         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1217                 time_left, completion_done(&i2c_dev->msg_complete),
1218                 i2c_dev->msg_err);
1219
1220         i2c_dev->is_curr_dma_xfer = false;
1221         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
1222                 return 0;
1223
1224         tegra_i2c_init(i2c_dev, true);
1225         /* start recovery upon arbitration loss in single master mode */
1226         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1227                 if (!i2c_dev->is_multimaster_mode)
1228                         return i2c_recover_bus(&i2c_dev->adapter);
1229                 return -EAGAIN;
1230         }
1231
1232         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1233                 if (msg->flags & I2C_M_IGNORE_NAK)
1234                         return 0;
1235                 return -EREMOTEIO;
1236         }
1237
1238         return -EIO;
1239 }
1240
1241 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1242                           int num)
1243 {
1244         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1245         int i;
1246         int ret;
1247
1248         ret = pm_runtime_get_sync(i2c_dev->dev);
1249         if (ret < 0) {
1250                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1251                 return ret;
1252         }
1253
1254         for (i = 0; i < num; i++) {
1255                 enum msg_end_type end_type = MSG_END_STOP;
1256
1257                 if (i < (num - 1)) {
1258                         if (msgs[i + 1].flags & I2C_M_NOSTART)
1259                                 end_type = MSG_END_CONTINUE;
1260                         else
1261                                 end_type = MSG_END_REPEAT_START;
1262                 }
1263                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1264                 if (ret)
1265                         break;
1266         }
1267
1268         pm_runtime_put(i2c_dev->dev);
1269
1270         return ret ?: i;
1271 }
1272
1273 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1274 {
1275         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1276         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1277                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1278
1279         if (i2c_dev->hw->has_continue_xfer_support)
1280                 ret |= I2C_FUNC_NOSTART;
1281         return ret;
1282 }
1283
1284 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1285 {
1286         struct device_node *np = i2c_dev->dev->of_node;
1287         int ret;
1288         bool multi_mode;
1289
1290         ret = of_property_read_u32(np, "clock-frequency",
1291                                    &i2c_dev->bus_clk_rate);
1292         if (ret)
1293                 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
1294
1295         multi_mode = of_property_read_bool(np, "multi-master");
1296         i2c_dev->is_multimaster_mode = multi_mode;
1297 }
1298
1299 static const struct i2c_algorithm tegra_i2c_algo = {
1300         .master_xfer    = tegra_i2c_xfer,
1301         .functionality  = tegra_i2c_func,
1302 };
1303
1304 /* payload size is only 12 bit */
1305 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1306         .flags = I2C_AQ_NO_ZERO_LEN,
1307         .max_read_len = SZ_4K,
1308         .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1309 };
1310
1311 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1312         .flags = I2C_AQ_NO_ZERO_LEN,
1313         .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1314 };
1315
1316 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1317         .recover_bus = tegra_i2c_issue_bus_clear,
1318 };
1319
1320 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1321         .has_continue_xfer_support = false,
1322         .has_per_pkt_xfer_complete_irq = false,
1323         .has_single_clk_source = false,
1324         .clk_divisor_hs_mode = 3,
1325         .clk_divisor_std_mode = 0,
1326         .clk_divisor_fast_mode = 0,
1327         .clk_divisor_fast_plus_mode = 0,
1328         .has_config_load_reg = false,
1329         .has_multi_master_mode = false,
1330         .has_slcg_override_reg = false,
1331         .has_mst_fifo = false,
1332         .quirks = &tegra_i2c_quirks,
1333         .supports_bus_clear = false,
1334         .has_apb_dma = true,
1335         .tlow_std_mode = 0x4,
1336         .thigh_std_mode = 0x2,
1337         .tlow_fast_fastplus_mode = 0x4,
1338         .thigh_fast_fastplus_mode = 0x2,
1339         .setup_hold_time_std_mode = 0x0,
1340         .setup_hold_time_fast_fast_plus_mode = 0x0,
1341         .setup_hold_time_hs_mode = 0x0,
1342         .has_interface_timing_reg = false,
1343 };
1344
1345 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1346         .has_continue_xfer_support = true,
1347         .has_per_pkt_xfer_complete_irq = false,
1348         .has_single_clk_source = false,
1349         .clk_divisor_hs_mode = 3,
1350         .clk_divisor_std_mode = 0,
1351         .clk_divisor_fast_mode = 0,
1352         .clk_divisor_fast_plus_mode = 0,
1353         .has_config_load_reg = false,
1354         .has_multi_master_mode = false,
1355         .has_slcg_override_reg = false,
1356         .has_mst_fifo = false,
1357         .quirks = &tegra_i2c_quirks,
1358         .supports_bus_clear = false,
1359         .has_apb_dma = true,
1360         .tlow_std_mode = 0x4,
1361         .thigh_std_mode = 0x2,
1362         .tlow_fast_fastplus_mode = 0x4,
1363         .thigh_fast_fastplus_mode = 0x2,
1364         .setup_hold_time_std_mode = 0x0,
1365         .setup_hold_time_fast_fast_plus_mode = 0x0,
1366         .setup_hold_time_hs_mode = 0x0,
1367         .has_interface_timing_reg = false,
1368 };
1369
1370 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1371         .has_continue_xfer_support = true,
1372         .has_per_pkt_xfer_complete_irq = true,
1373         .has_single_clk_source = true,
1374         .clk_divisor_hs_mode = 1,
1375         .clk_divisor_std_mode = 0x19,
1376         .clk_divisor_fast_mode = 0x19,
1377         .clk_divisor_fast_plus_mode = 0x10,
1378         .has_config_load_reg = false,
1379         .has_multi_master_mode = false,
1380         .has_slcg_override_reg = false,
1381         .has_mst_fifo = false,
1382         .quirks = &tegra_i2c_quirks,
1383         .supports_bus_clear = true,
1384         .has_apb_dma = true,
1385         .tlow_std_mode = 0x4,
1386         .thigh_std_mode = 0x2,
1387         .tlow_fast_fastplus_mode = 0x4,
1388         .thigh_fast_fastplus_mode = 0x2,
1389         .setup_hold_time_std_mode = 0x0,
1390         .setup_hold_time_fast_fast_plus_mode = 0x0,
1391         .setup_hold_time_hs_mode = 0x0,
1392         .has_interface_timing_reg = false,
1393 };
1394
1395 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1396         .has_continue_xfer_support = true,
1397         .has_per_pkt_xfer_complete_irq = true,
1398         .has_single_clk_source = true,
1399         .clk_divisor_hs_mode = 1,
1400         .clk_divisor_std_mode = 0x19,
1401         .clk_divisor_fast_mode = 0x19,
1402         .clk_divisor_fast_plus_mode = 0x10,
1403         .has_config_load_reg = true,
1404         .has_multi_master_mode = false,
1405         .has_slcg_override_reg = true,
1406         .has_mst_fifo = false,
1407         .quirks = &tegra_i2c_quirks,
1408         .supports_bus_clear = true,
1409         .has_apb_dma = true,
1410         .tlow_std_mode = 0x4,
1411         .thigh_std_mode = 0x2,
1412         .tlow_fast_fastplus_mode = 0x4,
1413         .thigh_fast_fastplus_mode = 0x2,
1414         .setup_hold_time_std_mode = 0x0,
1415         .setup_hold_time_fast_fast_plus_mode = 0x0,
1416         .setup_hold_time_hs_mode = 0x0,
1417         .has_interface_timing_reg = true,
1418 };
1419
1420 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1421         .has_continue_xfer_support = true,
1422         .has_per_pkt_xfer_complete_irq = true,
1423         .has_single_clk_source = true,
1424         .clk_divisor_hs_mode = 1,
1425         .clk_divisor_std_mode = 0x19,
1426         .clk_divisor_fast_mode = 0x19,
1427         .clk_divisor_fast_plus_mode = 0x10,
1428         .has_config_load_reg = true,
1429         .has_multi_master_mode = false,
1430         .has_slcg_override_reg = true,
1431         .has_mst_fifo = false,
1432         .quirks = &tegra_i2c_quirks,
1433         .supports_bus_clear = true,
1434         .has_apb_dma = true,
1435         .tlow_std_mode = 0x4,
1436         .thigh_std_mode = 0x2,
1437         .tlow_fast_fastplus_mode = 0x4,
1438         .thigh_fast_fastplus_mode = 0x2,
1439         .setup_hold_time_std_mode = 0,
1440         .setup_hold_time_fast_fast_plus_mode = 0,
1441         .setup_hold_time_hs_mode = 0,
1442         .has_interface_timing_reg = true,
1443 };
1444
1445 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1446         .has_continue_xfer_support = true,
1447         .has_per_pkt_xfer_complete_irq = true,
1448         .has_single_clk_source = true,
1449         .clk_divisor_hs_mode = 1,
1450         .clk_divisor_std_mode = 0x16,
1451         .clk_divisor_fast_mode = 0x19,
1452         .clk_divisor_fast_plus_mode = 0x10,
1453         .has_config_load_reg = true,
1454         .has_multi_master_mode = false,
1455         .has_slcg_override_reg = true,
1456         .has_mst_fifo = false,
1457         .quirks = &tegra_i2c_quirks,
1458         .supports_bus_clear = true,
1459         .has_apb_dma = false,
1460         .tlow_std_mode = 0x4,
1461         .thigh_std_mode = 0x3,
1462         .tlow_fast_fastplus_mode = 0x4,
1463         .thigh_fast_fastplus_mode = 0x2,
1464         .setup_hold_time_std_mode = 0,
1465         .setup_hold_time_fast_fast_plus_mode = 0,
1466         .setup_hold_time_hs_mode = 0,
1467         .has_interface_timing_reg = true,
1468 };
1469
1470 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1471         .has_continue_xfer_support = true,
1472         .has_per_pkt_xfer_complete_irq = true,
1473         .has_single_clk_source = true,
1474         .clk_divisor_hs_mode = 1,
1475         .clk_divisor_std_mode = 0x4f,
1476         .clk_divisor_fast_mode = 0x3c,
1477         .clk_divisor_fast_plus_mode = 0x16,
1478         .has_config_load_reg = true,
1479         .has_multi_master_mode = true,
1480         .has_slcg_override_reg = true,
1481         .has_mst_fifo = true,
1482         .quirks = &tegra194_i2c_quirks,
1483         .supports_bus_clear = true,
1484         .has_apb_dma = false,
1485         .tlow_std_mode = 0x8,
1486         .thigh_std_mode = 0x7,
1487         .tlow_fast_fastplus_mode = 0x2,
1488         .thigh_fast_fastplus_mode = 0x2,
1489         .setup_hold_time_std_mode = 0x08080808,
1490         .setup_hold_time_fast_fast_plus_mode = 0x02020202,
1491         .setup_hold_time_hs_mode = 0x090909,
1492         .has_interface_timing_reg = true,
1493 };
1494
1495 /* Match table for of_platform binding */
1496 static const struct of_device_id tegra_i2c_of_match[] = {
1497         { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1498         { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1499         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1500         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1501         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1502         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1503         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1504         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1505         {},
1506 };
1507 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1508
1509 static int tegra_i2c_probe(struct platform_device *pdev)
1510 {
1511         struct tegra_i2c_dev *i2c_dev;
1512         struct resource *res;
1513         struct clk *div_clk;
1514         struct clk *fast_clk;
1515         void __iomem *base;
1516         phys_addr_t base_phys;
1517         int irq;
1518         int ret;
1519
1520         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1521         base_phys = res->start;
1522         base = devm_ioremap_resource(&pdev->dev, res);
1523         if (IS_ERR(base))
1524                 return PTR_ERR(base);
1525
1526         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1527         if (!res) {
1528                 dev_err(&pdev->dev, "no irq resource\n");
1529                 return -EINVAL;
1530         }
1531         irq = res->start;
1532
1533         div_clk = devm_clk_get(&pdev->dev, "div-clk");
1534         if (IS_ERR(div_clk)) {
1535                 if (PTR_ERR(div_clk) != -EPROBE_DEFER)
1536                         dev_err(&pdev->dev, "missing controller clock\n");
1537
1538                 return PTR_ERR(div_clk);
1539         }
1540
1541         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1542         if (!i2c_dev)
1543                 return -ENOMEM;
1544
1545         i2c_dev->base = base;
1546         i2c_dev->base_phys = base_phys;
1547         i2c_dev->div_clk = div_clk;
1548         i2c_dev->adapter.algo = &tegra_i2c_algo;
1549         i2c_dev->adapter.retries = 1;
1550         i2c_dev->adapter.timeout = 6 * HZ;
1551         i2c_dev->irq = irq;
1552         i2c_dev->cont_id = pdev->id;
1553         i2c_dev->dev = &pdev->dev;
1554
1555         i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
1556         if (IS_ERR(i2c_dev->rst)) {
1557                 dev_err(&pdev->dev, "missing controller reset\n");
1558                 return PTR_ERR(i2c_dev->rst);
1559         }
1560
1561         tegra_i2c_parse_dt(i2c_dev);
1562
1563         i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1564         i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
1565                                                   "nvidia,tegra20-i2c-dvc");
1566         i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1567         i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len +
1568                                 I2C_PACKET_HEADER_SIZE;
1569         init_completion(&i2c_dev->msg_complete);
1570         init_completion(&i2c_dev->dma_complete);
1571         spin_lock_init(&i2c_dev->xfer_lock);
1572
1573         if (!i2c_dev->hw->has_single_clk_source) {
1574                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1575                 if (IS_ERR(fast_clk)) {
1576                         dev_err(&pdev->dev, "missing fast clock\n");
1577                         return PTR_ERR(fast_clk);
1578                 }
1579                 i2c_dev->fast_clk = fast_clk;
1580         }
1581
1582         platform_set_drvdata(pdev, i2c_dev);
1583
1584         if (!i2c_dev->hw->has_single_clk_source) {
1585                 ret = clk_prepare(i2c_dev->fast_clk);
1586                 if (ret < 0) {
1587                         dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1588                         return ret;
1589                 }
1590         }
1591
1592         if (i2c_dev->bus_clk_rate > I2C_FAST_MODE &&
1593             i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE)
1594                 i2c_dev->clk_divisor_non_hs_mode =
1595                                 i2c_dev->hw->clk_divisor_fast_plus_mode;
1596         else if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE &&
1597                  i2c_dev->bus_clk_rate <= I2C_FAST_MODE)
1598                 i2c_dev->clk_divisor_non_hs_mode =
1599                                 i2c_dev->hw->clk_divisor_fast_mode;
1600         else
1601                 i2c_dev->clk_divisor_non_hs_mode =
1602                                 i2c_dev->hw->clk_divisor_std_mode;
1603
1604         ret = clk_prepare(i2c_dev->div_clk);
1605         if (ret < 0) {
1606                 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1607                 goto unprepare_fast_clk;
1608         }
1609
1610         pm_runtime_enable(&pdev->dev);
1611         if (!pm_runtime_enabled(&pdev->dev))
1612                 ret = tegra_i2c_runtime_resume(&pdev->dev);
1613         else
1614                 ret = pm_runtime_get_sync(i2c_dev->dev);
1615
1616         if (ret < 0) {
1617                 dev_err(&pdev->dev, "runtime resume failed\n");
1618                 goto unprepare_div_clk;
1619         }
1620
1621         if (i2c_dev->is_multimaster_mode) {
1622                 ret = clk_enable(i2c_dev->div_clk);
1623                 if (ret < 0) {
1624                         dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
1625                                 ret);
1626                         goto disable_rpm;
1627                 }
1628         }
1629
1630         if (i2c_dev->hw->supports_bus_clear)
1631                 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1632
1633         ret = tegra_i2c_init_dma(i2c_dev);
1634         if (ret < 0)
1635                 goto disable_div_clk;
1636
1637         ret = tegra_i2c_init(i2c_dev, false);
1638         if (ret) {
1639                 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
1640                 goto release_dma;
1641         }
1642
1643         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1644                                tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
1645         if (ret) {
1646                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1647                 goto release_dma;
1648         }
1649
1650         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1651         i2c_dev->adapter.owner = THIS_MODULE;
1652         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1653         strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1654                 sizeof(i2c_dev->adapter.name));
1655         i2c_dev->adapter.dev.parent = &pdev->dev;
1656         i2c_dev->adapter.nr = pdev->id;
1657         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1658
1659         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1660         if (ret)
1661                 goto release_dma;
1662
1663         pm_runtime_put(&pdev->dev);
1664
1665         return 0;
1666
1667 release_dma:
1668         tegra_i2c_release_dma(i2c_dev);
1669
1670 disable_div_clk:
1671         if (i2c_dev->is_multimaster_mode)
1672                 clk_disable(i2c_dev->div_clk);
1673
1674 disable_rpm:
1675         pm_runtime_disable(&pdev->dev);
1676         if (!pm_runtime_status_suspended(&pdev->dev))
1677                 tegra_i2c_runtime_suspend(&pdev->dev);
1678
1679 unprepare_div_clk:
1680         clk_unprepare(i2c_dev->div_clk);
1681
1682 unprepare_fast_clk:
1683         if (!i2c_dev->hw->has_single_clk_source)
1684                 clk_unprepare(i2c_dev->fast_clk);
1685
1686         return ret;
1687 }
1688
1689 static int tegra_i2c_remove(struct platform_device *pdev)
1690 {
1691         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1692
1693         i2c_del_adapter(&i2c_dev->adapter);
1694
1695         if (i2c_dev->is_multimaster_mode)
1696                 clk_disable(i2c_dev->div_clk);
1697
1698         pm_runtime_disable(&pdev->dev);
1699         if (!pm_runtime_status_suspended(&pdev->dev))
1700                 tegra_i2c_runtime_suspend(&pdev->dev);
1701
1702         clk_unprepare(i2c_dev->div_clk);
1703         if (!i2c_dev->hw->has_single_clk_source)
1704                 clk_unprepare(i2c_dev->fast_clk);
1705
1706         tegra_i2c_release_dma(i2c_dev);
1707         return 0;
1708 }
1709
1710 #ifdef CONFIG_PM_SLEEP
1711 static int tegra_i2c_suspend(struct device *dev)
1712 {
1713         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1714
1715         i2c_mark_adapter_suspended(&i2c_dev->adapter);
1716
1717         return 0;
1718 }
1719
1720 static int tegra_i2c_resume(struct device *dev)
1721 {
1722         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1723         int err;
1724
1725         err = tegra_i2c_runtime_resume(dev);
1726         if (err)
1727                 return err;
1728
1729         err = tegra_i2c_init(i2c_dev, false);
1730         if (err)
1731                 return err;
1732
1733         err = tegra_i2c_runtime_suspend(dev);
1734         if (err)
1735                 return err;
1736
1737         i2c_mark_adapter_resumed(&i2c_dev->adapter);
1738
1739         return 0;
1740 }
1741
1742 static const struct dev_pm_ops tegra_i2c_pm = {
1743         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1744         SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1745                            NULL)
1746 };
1747
1748 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
1749 #else
1750 #define TEGRA_I2C_PM    NULL
1751 #endif
1752
1753 static struct platform_driver tegra_i2c_driver = {
1754         .probe   = tegra_i2c_probe,
1755         .remove  = tegra_i2c_remove,
1756         .driver  = {
1757                 .name  = "tegra-i2c",
1758                 .of_match_table = tegra_i2c_of_match,
1759                 .pm    = TEGRA_I2C_PM,
1760         },
1761 };
1762
1763 module_platform_driver(tegra_i2c_driver);
1764
1765 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1766 MODULE_AUTHOR("Colin Cross");
1767 MODULE_LICENSE("GPL v2");