1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
4 Philip Edelbrock <phil@netroedge.com>
11 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
12 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
17 Note: we assume there can only be one device, with one or more
19 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
20 For devices supporting multiple ports the i2c_adapter should provide
21 an i2c_algorithm to access them.
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/delay.h>
29 #include <linux/stddef.h>
30 #include <linux/ioport.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33 #include <linux/dmi.h>
34 #include <linux/acpi.h>
38 /* PIIX4 SMBus address offsets */
39 #define SMBHSTSTS (0 + piix4_smba)
40 #define SMBHSLVSTS (1 + piix4_smba)
41 #define SMBHSTCNT (2 + piix4_smba)
42 #define SMBHSTCMD (3 + piix4_smba)
43 #define SMBHSTADD (4 + piix4_smba)
44 #define SMBHSTDAT0 (5 + piix4_smba)
45 #define SMBHSTDAT1 (6 + piix4_smba)
46 #define SMBBLKDAT (7 + piix4_smba)
47 #define SMBSLVCNT (8 + piix4_smba)
48 #define SMBSHDWCMD (9 + piix4_smba)
49 #define SMBSLVEVT (0xA + piix4_smba)
50 #define SMBSLVDAT (0xC + piix4_smba)
52 /* count for request_region */
55 /* PCI Address Constants */
57 #define SMBHSTCFG 0x0D2
59 #define SMBSHDW1 0x0D4
60 #define SMBSHDW2 0x0D5
64 #define MAX_TIMEOUT 500
68 #define PIIX4_QUICK 0x00
69 #define PIIX4_BYTE 0x04
70 #define PIIX4_BYTE_DATA 0x08
71 #define PIIX4_WORD_DATA 0x0C
72 #define PIIX4_BLOCK_DATA 0x14
74 /* Multi-port constants */
75 #define PIIX4_MAX_ADAPTERS 4
78 #define SB800_PIIX4_SMB_IDX 0xcd6
80 #define KERNCZ_IMC_IDX 0x3e
81 #define KERNCZ_IMC_DATA 0x3f
84 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
85 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
86 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
88 #define SB800_PIIX4_PORT_IDX 0x2c
89 #define SB800_PIIX4_PORT_IDX_ALT 0x2e
90 #define SB800_PIIX4_PORT_IDX_SEL 0x2f
91 #define SB800_PIIX4_PORT_IDX_MASK 0x06
92 #define SB800_PIIX4_PORT_IDX_SHIFT 1
94 /* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
95 #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
96 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
97 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
99 /* insmod parameters */
101 /* If force is set to anything different from 0, we forcibly enable the
104 module_param (force, int, 0);
105 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
107 /* If force_addr is set to anything different from 0, we forcibly enable
108 the PIIX4 at the given address. VERY DANGEROUS! */
109 static int force_addr;
110 module_param_hw(force_addr, int, ioport, 0);
111 MODULE_PARM_DESC(force_addr,
112 "Forcibly enable the PIIX4 at the given address. "
113 "EXTREMELY DANGEROUS!");
115 static int srvrworks_csb5_delay;
116 static struct pci_driver piix4_driver;
118 static const struct dmi_system_id piix4_dmi_blacklist[] = {
120 .ident = "Sapphire AM2RD790",
122 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
123 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
127 .ident = "DFI Lanparty UT 790FX",
129 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
130 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
136 /* The IBM entry is in a separate table because we only check it
137 on Intel-based systems */
138 static const struct dmi_system_id piix4_dmi_ibm[] = {
141 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
149 static u8 piix4_port_sel_sb800;
150 static u8 piix4_port_mask_sb800;
151 static u8 piix4_port_shift_sb800;
152 static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
153 " port 0", " port 2", " port 3", " port 4"
155 static const char *piix4_aux_port_name_sb800 = " port 1";
157 struct i2c_piix4_adapdata {
163 u8 port; /* Port number, shifted */
166 static int piix4_setup(struct pci_dev *PIIX4_dev,
167 const struct pci_device_id *id)
170 unsigned short piix4_smba;
172 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
173 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
174 srvrworks_csb5_delay = 1;
176 /* On some motherboards, it was reported that accessing the SMBus
177 caused severe hardware problems */
178 if (dmi_check_system(piix4_dmi_blacklist)) {
179 dev_err(&PIIX4_dev->dev,
180 "Accessing the SMBus on this system is unsafe!\n");
184 /* Don't access SMBus on IBM systems which get corrupted eeproms */
185 if (dmi_check_system(piix4_dmi_ibm) &&
186 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
187 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
188 "may corrupt your serial eeprom! Refusing to load "
193 /* Determine the address of the SMBus areas */
195 piix4_smba = force_addr & 0xfff0;
198 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
199 piix4_smba &= 0xfff0;
200 if(piix4_smba == 0) {
201 dev_err(&PIIX4_dev->dev, "SMBus base address "
202 "uninitialized - upgrade BIOS or use "
203 "force_addr=0xaddr\n");
208 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
211 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
212 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
217 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
219 /* If force_addr is set, we program the new address here. Just to make
220 sure, we disable the PIIX4 first. */
222 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
223 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
224 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
225 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
226 "new address %04x!\n", piix4_smba);
227 } else if ((temp & 1) == 0) {
229 /* This should never need to be done, but has been
230 * noted that many Dell machines have the SMBus
231 * interface on the PIIX4 disabled!? NOTE: This assumes
232 * I/O space and other allocations WERE done by the
233 * Bios! Don't complain if your hardware does weird
234 * things after enabling this. :') Check for Bios
235 * updates before resorting to this.
237 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
239 dev_notice(&PIIX4_dev->dev,
240 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
242 dev_err(&PIIX4_dev->dev,
243 "SMBus Host Controller not enabled!\n");
244 release_region(piix4_smba, SMBIOSIZE);
249 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
250 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
251 else if ((temp & 0x0E) == 0)
252 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
254 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
255 "(or code out of date)!\n");
257 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
258 dev_info(&PIIX4_dev->dev,
259 "SMBus Host Controller at 0x%x, revision %d\n",
265 static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
266 const struct pci_device_id *id, u8 aux)
268 unsigned short piix4_smba;
269 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel;
270 u8 i2ccfg, i2ccfg_offset = 0x10;
272 /* SB800 and later SMBus does not support forcing address */
273 if (force || force_addr) {
274 dev_err(&PIIX4_dev->dev, "SMBus does not support "
275 "forcing address!\n");
279 /* Determine the address of the SMBus areas */
280 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
281 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
282 PIIX4_dev->revision >= 0x41) ||
283 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
284 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
285 PIIX4_dev->revision >= 0x49) ||
286 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
287 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
290 smb_en = (aux) ? 0x28 : 0x2c;
292 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) {
293 dev_err(&PIIX4_dev->dev,
294 "SMB base address index region 0x%x already in use.\n",
295 SB800_PIIX4_SMB_IDX);
299 outb_p(smb_en, SB800_PIIX4_SMB_IDX);
300 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
301 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
302 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
304 release_region(SB800_PIIX4_SMB_IDX, 2);
307 smb_en_status = smba_en_lo & 0x10;
308 piix4_smba = smba_en_hi << 8;
312 smb_en_status = smba_en_lo & 0x01;
313 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
316 if (!smb_en_status) {
317 dev_err(&PIIX4_dev->dev,
318 "SMBus Host Controller not enabled!\n");
322 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
325 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
326 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
331 /* Aux SMBus does not support IRQ information */
333 dev_info(&PIIX4_dev->dev,
334 "Auxiliary SMBus Host Controller at 0x%x\n",
339 /* Request the SMBus I2C bus config region */
340 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
341 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
342 "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
343 release_region(piix4_smba, SMBIOSIZE);
346 i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
347 release_region(piix4_smba + i2ccfg_offset, 1);
350 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
352 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
354 dev_info(&PIIX4_dev->dev,
355 "SMBus Host Controller at 0x%x, revision %d\n",
356 piix4_smba, i2ccfg >> 4);
358 /* Find which register is used for port selection */
359 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
360 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
361 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
362 (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
363 PIIX4_dev->revision >= 0x1F)) {
364 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
365 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
366 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
368 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
369 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
370 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
373 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2,
374 "sb800_piix4_smb")) {
375 release_region(piix4_smba, SMBIOSIZE);
379 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
380 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
381 piix4_port_sel_sb800 = (port_sel & 0x01) ?
382 SB800_PIIX4_PORT_IDX_ALT :
383 SB800_PIIX4_PORT_IDX;
384 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
385 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
386 release_region(SB800_PIIX4_SMB_IDX, 2);
389 dev_info(&PIIX4_dev->dev,
390 "Using register 0x%02x for SMBus port selection\n",
391 (unsigned int)piix4_port_sel_sb800);
396 static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
397 const struct pci_device_id *id,
398 unsigned short base_reg_addr)
400 /* Set up auxiliary SMBus controllers found on some
401 * AMD chipsets e.g. SP5100 (SB700 derivative) */
403 unsigned short piix4_smba;
405 /* Read address of auxiliary SMBus controller */
406 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
407 if ((piix4_smba & 1) == 0) {
408 dev_dbg(&PIIX4_dev->dev,
409 "Auxiliary SMBus controller not enabled\n");
413 piix4_smba &= 0xfff0;
414 if (piix4_smba == 0) {
415 dev_dbg(&PIIX4_dev->dev,
416 "Auxiliary SMBus base address uninitialized\n");
420 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
423 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
424 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
425 "already in use!\n", piix4_smba);
429 dev_info(&PIIX4_dev->dev,
430 "Auxiliary SMBus Host Controller at 0x%x\n",
436 static int piix4_transaction(struct i2c_adapter *piix4_adapter)
438 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
439 unsigned short piix4_smba = adapdata->smba;
444 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
445 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
446 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
449 /* Make sure the SMBus host is ready to start transmitting */
450 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
451 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
452 "Resetting...\n", temp);
453 outb_p(temp, SMBHSTSTS);
454 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
455 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
458 dev_dbg(&piix4_adapter->dev, "Successful!\n");
462 /* start the transaction by setting bit 6 */
463 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
465 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
466 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
467 usleep_range(2000, 2100);
469 usleep_range(250, 500);
471 while ((++timeout < MAX_TIMEOUT) &&
472 ((temp = inb_p(SMBHSTSTS)) & 0x01))
473 usleep_range(250, 500);
475 /* If the SMBus is still busy, we give up */
476 if (timeout == MAX_TIMEOUT) {
477 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
483 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
488 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
489 "locked until next hard reset. (sorry!)\n");
490 /* Clock stops and slave is stuck in mid-transmission */
495 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
498 if (inb_p(SMBHSTSTS) != 0x00)
499 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
501 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
502 dev_err(&piix4_adapter->dev, "Failed reset at end of "
503 "transaction (%02x)\n", temp);
505 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
506 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
507 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
512 /* Return negative errno on error. */
513 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
514 unsigned short flags, char read_write,
515 u8 command, int size, union i2c_smbus_data * data)
517 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
518 unsigned short piix4_smba = adapdata->smba;
523 case I2C_SMBUS_QUICK:
524 outb_p((addr << 1) | read_write,
529 outb_p((addr << 1) | read_write,
531 if (read_write == I2C_SMBUS_WRITE)
532 outb_p(command, SMBHSTCMD);
535 case I2C_SMBUS_BYTE_DATA:
536 outb_p((addr << 1) | read_write,
538 outb_p(command, SMBHSTCMD);
539 if (read_write == I2C_SMBUS_WRITE)
540 outb_p(data->byte, SMBHSTDAT0);
541 size = PIIX4_BYTE_DATA;
543 case I2C_SMBUS_WORD_DATA:
544 outb_p((addr << 1) | read_write,
546 outb_p(command, SMBHSTCMD);
547 if (read_write == I2C_SMBUS_WRITE) {
548 outb_p(data->word & 0xff, SMBHSTDAT0);
549 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
551 size = PIIX4_WORD_DATA;
553 case I2C_SMBUS_BLOCK_DATA:
554 outb_p((addr << 1) | read_write,
556 outb_p(command, SMBHSTCMD);
557 if (read_write == I2C_SMBUS_WRITE) {
558 len = data->block[0];
559 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
561 outb_p(len, SMBHSTDAT0);
562 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
563 for (i = 1; i <= len; i++)
564 outb_p(data->block[i], SMBBLKDAT);
566 size = PIIX4_BLOCK_DATA;
569 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
573 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
575 status = piix4_transaction(adap);
579 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
585 case PIIX4_BYTE_DATA:
586 data->byte = inb_p(SMBHSTDAT0);
588 case PIIX4_WORD_DATA:
589 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
591 case PIIX4_BLOCK_DATA:
592 data->block[0] = inb_p(SMBHSTDAT0);
593 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
595 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
596 for (i = 1; i <= data->block[0]; i++)
597 data->block[i] = inb_p(SMBBLKDAT);
603 static uint8_t piix4_imc_read(uint8_t idx)
605 outb_p(idx, KERNCZ_IMC_IDX);
606 return inb_p(KERNCZ_IMC_DATA);
609 static void piix4_imc_write(uint8_t idx, uint8_t value)
611 outb_p(idx, KERNCZ_IMC_IDX);
612 outb_p(value, KERNCZ_IMC_DATA);
615 static int piix4_imc_sleep(void)
617 int timeout = MAX_TIMEOUT;
619 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
622 /* clear response register */
623 piix4_imc_write(0x82, 0x00);
624 /* request ownership flag */
625 piix4_imc_write(0x83, 0xB4);
626 /* kick off IMC Mailbox command 96 */
627 piix4_imc_write(0x80, 0x96);
630 if (piix4_imc_read(0x82) == 0xfa) {
631 release_region(KERNCZ_IMC_IDX, 2);
634 usleep_range(1000, 2000);
637 release_region(KERNCZ_IMC_IDX, 2);
641 static void piix4_imc_wakeup(void)
643 int timeout = MAX_TIMEOUT;
645 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
648 /* clear response register */
649 piix4_imc_write(0x82, 0x00);
650 /* release ownership flag */
651 piix4_imc_write(0x83, 0xB5);
652 /* kick off IMC Mailbox command 96 */
653 piix4_imc_write(0x80, 0x96);
656 if (piix4_imc_read(0x82) == 0xfa)
658 usleep_range(1000, 2000);
661 release_region(KERNCZ_IMC_IDX, 2);
665 * Handles access to multiple SMBus ports on the SB800.
666 * The port is selected by bits 2:1 of the smb_en register (0x2c).
667 * Returns negative errno on error.
669 * Note: The selected port must be returned to the initial selection to avoid
670 * problems on certain systems.
672 static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
673 unsigned short flags, char read_write,
674 u8 command, int size, union i2c_smbus_data *data)
676 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
677 unsigned short piix4_smba = adapdata->smba;
678 int retries = MAX_TIMEOUT;
684 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb"))
687 /* Request the SMBUS semaphore, avoid conflicts with the IMC */
688 smbslvcnt = inb_p(SMBSLVCNT);
690 outb_p(smbslvcnt | 0x10, SMBSLVCNT);
692 /* Check the semaphore status */
693 smbslvcnt = inb_p(SMBSLVCNT);
694 if (smbslvcnt & 0x10)
697 usleep_range(1000, 2000);
699 /* SMBus is still owned by the IMC, we give up */
706 * Notify the IMC (Integrated Micro Controller) if required.
707 * Among other responsibilities, the IMC is in charge of monitoring
708 * the System fans and temperature sensors, and act accordingly.
709 * All this is done through SMBus and can/will collide
710 * with our transactions if they are long (BLOCK_DATA).
711 * Therefore we need to request the ownership flag during those
714 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
717 ret = piix4_imc_sleep();
721 "IMC base address index region 0x%x already in use.\n",
726 "Failed to communicate with the IMC.\n");
732 /* If IMC communication fails do not retry */
735 "Continuing without IMC notification.\n");
736 adapdata->notify_imc = false;
740 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
741 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
743 port = adapdata->port;
744 if ((smba_en_lo & piix4_port_mask_sb800) != port)
745 outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port,
746 SB800_PIIX4_SMB_IDX + 1);
748 retval = piix4_access(adap, addr, flags, read_write,
749 command, size, data);
751 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1);
753 /* Release the semaphore */
754 outb_p(smbslvcnt | 0x20, SMBSLVCNT);
756 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
760 release_region(SB800_PIIX4_SMB_IDX, 2);
764 static u32 piix4_func(struct i2c_adapter *adapter)
766 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
767 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
768 I2C_FUNC_SMBUS_BLOCK_DATA;
771 static const struct i2c_algorithm smbus_algorithm = {
772 .smbus_xfer = piix4_access,
773 .functionality = piix4_func,
776 static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
777 .smbus_xfer = piix4_access_sb800,
778 .functionality = piix4_func,
781 static const struct pci_device_id piix4_ids[] = {
782 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
783 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
784 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
785 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
786 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
787 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
788 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
789 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
790 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
791 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
792 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
793 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
794 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
795 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
796 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
797 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
798 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
799 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
800 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
801 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
805 MODULE_DEVICE_TABLE (pci, piix4_ids);
807 static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
808 static struct i2c_adapter *piix4_aux_adapter;
810 static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
811 bool sb800_main, u8 port, bool notify_imc,
812 const char *name, struct i2c_adapter **padap)
814 struct i2c_adapter *adap;
815 struct i2c_piix4_adapdata *adapdata;
818 adap = kzalloc(sizeof(*adap), GFP_KERNEL);
820 release_region(smba, SMBIOSIZE);
824 adap->owner = THIS_MODULE;
825 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
826 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
829 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
830 if (adapdata == NULL) {
832 release_region(smba, SMBIOSIZE);
836 adapdata->smba = smba;
837 adapdata->sb800_main = sb800_main;
838 adapdata->port = port << piix4_port_shift_sb800;
839 adapdata->notify_imc = notify_imc;
841 /* set up the sysfs linkage to our parent device */
842 adap->dev.parent = &dev->dev;
844 snprintf(adap->name, sizeof(adap->name),
845 "SMBus PIIX4 adapter%s at %04x", name, smba);
847 i2c_set_adapdata(adap, adapdata);
849 retval = i2c_add_adapter(adap);
853 release_region(smba, SMBIOSIZE);
861 static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
864 struct i2c_piix4_adapdata *adapdata;
868 for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) {
869 retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
870 piix4_main_port_names_sb800[port],
871 &piix4_main_adapters[port]);
880 "Error setting up SB800 adapters. Unregistering!\n");
881 while (--port >= 0) {
882 adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
883 if (adapdata->smba) {
884 i2c_del_adapter(piix4_main_adapters[port]);
886 kfree(piix4_main_adapters[port]);
887 piix4_main_adapters[port] = NULL;
894 static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
897 bool is_sb800 = false;
899 if ((dev->vendor == PCI_VENDOR_ID_ATI &&
900 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
901 dev->revision >= 0x40) ||
902 dev->vendor == PCI_VENDOR_ID_AMD ||
903 dev->vendor == PCI_VENDOR_ID_HYGON) {
904 bool notify_imc = false;
907 if ((dev->vendor == PCI_VENDOR_ID_AMD ||
908 dev->vendor == PCI_VENDOR_ID_HYGON) &&
909 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
913 * Detect if IMC is active or not, this method is
914 * described on coreboot's AMD IMC notes
916 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
922 /* base address location etc changed in SB800 */
923 retval = piix4_setup_sb800(dev, id, 0);
928 * Try to register multiplexed main SMBus adapter,
929 * give up if we can't
931 retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
935 retval = piix4_setup(dev, id);
939 /* Try to register main SMBus adapter, give up if we can't */
940 retval = piix4_add_adapter(dev, retval, false, 0, false, "",
941 &piix4_main_adapters[0]);
946 /* Check for auxiliary SMBus on some AMD chipsets */
949 if (dev->vendor == PCI_VENDOR_ID_ATI &&
950 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
951 if (dev->revision < 0x40) {
952 retval = piix4_setup_aux(dev, id, 0x58);
954 /* SB800 added aux bus too */
955 retval = piix4_setup_sb800(dev, id, 1);
959 if (dev->vendor == PCI_VENDOR_ID_AMD &&
960 dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) {
961 retval = piix4_setup_sb800(dev, id, 1);
965 /* Try to add the aux adapter if it exists,
966 * piix4_add_adapter will clean up if this fails */
967 piix4_add_adapter(dev, retval, false, 0, false,
968 is_sb800 ? piix4_aux_port_name_sb800 : "",
975 static void piix4_adap_remove(struct i2c_adapter *adap)
977 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
979 if (adapdata->smba) {
980 i2c_del_adapter(adap);
981 if (adapdata->port == (0 << piix4_port_shift_sb800))
982 release_region(adapdata->smba, SMBIOSIZE);
988 static void piix4_remove(struct pci_dev *dev)
990 int port = PIIX4_MAX_ADAPTERS;
992 while (--port >= 0) {
993 if (piix4_main_adapters[port]) {
994 piix4_adap_remove(piix4_main_adapters[port]);
995 piix4_main_adapters[port] = NULL;
999 if (piix4_aux_adapter) {
1000 piix4_adap_remove(piix4_aux_adapter);
1001 piix4_aux_adapter = NULL;
1005 static struct pci_driver piix4_driver = {
1006 .name = "piix4_smbus",
1007 .id_table = piix4_ids,
1008 .probe = piix4_probe,
1009 .remove = piix4_remove,
1012 module_pci_driver(piix4_driver);
1014 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
1015 "Philip Edelbrock <phil@netroedge.com>");
1016 MODULE_DESCRIPTION("PIIX4 SMBus driver");
1017 MODULE_LICENSE("GPL");