1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
13 * Supports the following Intel I/O Controller Hubs (ICH):
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
58 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
59 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
60 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
61 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
62 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
63 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
64 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
65 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
66 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
67 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
68 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
70 * Features supported by this driver:
74 * Block process call transaction yes
75 * I2C block read transaction yes (doesn't use the block buffer)
77 * SMBus Host Notify yes
78 * Interrupt processing yes
80 * See the file Documentation/i2c/busses/i2c-i801 for details.
83 #include <linux/interrupt.h>
84 #include <linux/module.h>
85 #include <linux/pci.h>
86 #include <linux/kernel.h>
87 #include <linux/stddef.h>
88 #include <linux/delay.h>
89 #include <linux/ioport.h>
90 #include <linux/init.h>
91 #include <linux/i2c.h>
92 #include <linux/i2c-smbus.h>
93 #include <linux/acpi.h>
95 #include <linux/dmi.h>
96 #include <linux/slab.h>
97 #include <linux/string.h>
98 #include <linux/wait.h>
99 #include <linux/err.h>
100 #include <linux/platform_device.h>
101 #include <linux/platform_data/itco_wdt.h>
102 #include <linux/pm_runtime.h>
104 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
105 #include <linux/gpio/machine.h>
106 #include <linux/platform_data/i2c-mux-gpio.h>
109 /* I801 SMBus address offsets */
110 #define SMBHSTSTS(p) (0 + (p)->smba)
111 #define SMBHSTCNT(p) (2 + (p)->smba)
112 #define SMBHSTCMD(p) (3 + (p)->smba)
113 #define SMBHSTADD(p) (4 + (p)->smba)
114 #define SMBHSTDAT0(p) (5 + (p)->smba)
115 #define SMBHSTDAT1(p) (6 + (p)->smba)
116 #define SMBBLKDAT(p) (7 + (p)->smba)
117 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
118 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
119 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
120 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
121 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
122 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
124 /* PCI Address Constants */
126 #define SMBPCICTL 0x004
127 #define SMBPCISTS 0x006
128 #define SMBHSTCFG 0x040
129 #define TCOBASE 0x050
132 #define ACPIBASE 0x040
133 #define ACPIBASE_SMI_OFF 0x030
134 #define ACPICTRL 0x044
135 #define ACPICTRL_EN 0x080
137 #define SBREG_BAR 0x10
138 #define SBREG_SMBCTRL 0xc6000c
139 #define SBREG_SMBCTRL_DNV 0xcf000c
141 /* Host status bits for SMBPCISTS */
142 #define SMBPCISTS_INTS BIT(3)
144 /* Control bits for SMBPCICTL */
145 #define SMBPCICTL_INTDIS BIT(10)
147 /* Host configuration bits for SMBHSTCFG */
148 #define SMBHSTCFG_HST_EN BIT(0)
149 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
150 #define SMBHSTCFG_I2C_EN BIT(2)
151 #define SMBHSTCFG_SPD_WD BIT(4)
153 /* TCO configuration bits for TCOCTL */
154 #define TCOCTL_EN BIT(8)
156 /* Auxiliary status register bits, ICH4+ only */
157 #define SMBAUXSTS_CRCE BIT(0)
158 #define SMBAUXSTS_STCO BIT(1)
160 /* Auxiliary control register bits, ICH4+ only */
161 #define SMBAUXCTL_CRC BIT(0)
162 #define SMBAUXCTL_E32B BIT(1)
165 #define MAX_RETRIES 400
167 /* I801 command constants */
168 #define I801_QUICK 0x00
169 #define I801_BYTE 0x04
170 #define I801_BYTE_DATA 0x08
171 #define I801_WORD_DATA 0x0C
172 #define I801_PROC_CALL 0x10 /* unimplemented */
173 #define I801_BLOCK_DATA 0x14
174 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
175 #define I801_BLOCK_PROC_CALL 0x1C
177 /* I801 Host Control register bits */
178 #define SMBHSTCNT_INTREN BIT(0)
179 #define SMBHSTCNT_KILL BIT(1)
180 #define SMBHSTCNT_LAST_BYTE BIT(5)
181 #define SMBHSTCNT_START BIT(6)
182 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
184 /* I801 Hosts Status register bits */
185 #define SMBHSTSTS_BYTE_DONE BIT(7)
186 #define SMBHSTSTS_INUSE_STS BIT(6)
187 #define SMBHSTSTS_SMBALERT_STS BIT(5)
188 #define SMBHSTSTS_FAILED BIT(4)
189 #define SMBHSTSTS_BUS_ERR BIT(3)
190 #define SMBHSTSTS_DEV_ERR BIT(2)
191 #define SMBHSTSTS_INTR BIT(1)
192 #define SMBHSTSTS_HOST_BUSY BIT(0)
194 /* Host Notify Status register bits */
195 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
197 /* Host Notify Command register bits */
198 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
200 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
203 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
206 /* Older devices have their ID defined in <linux/pci_ids.h> */
207 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
211 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
213 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
217 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
218 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
219 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
220 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
221 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
222 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
223 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
224 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
225 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
226 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
227 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
228 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
233 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
234 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
235 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
236 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
237 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
238 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
239 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
241 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
242 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
244 struct i801_mux_config {
249 unsigned gpios[2]; /* Relative to gpio_chip->base */
254 struct i2c_adapter adapter;
256 unsigned char original_hstcfg;
257 unsigned char original_slvcmd;
258 struct pci_dev *pci_dev;
259 unsigned int features;
262 wait_queue_head_t waitq;
265 /* Command state used by isr for byte-by-byte block transactions */
272 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
273 const struct i801_mux_config *mux_drvdata;
274 struct platform_device *mux_pdev;
275 struct gpiod_lookup_table *lookup;
277 struct platform_device *tco_pdev;
280 * If set to true the host controller registers are reserved for
281 * ACPI AML use. Protected by acpi_lock.
284 struct mutex acpi_lock;
287 #define FEATURE_SMBUS_PEC BIT(0)
288 #define FEATURE_BLOCK_BUFFER BIT(1)
289 #define FEATURE_BLOCK_PROC BIT(2)
290 #define FEATURE_I2C_BLOCK_READ BIT(3)
291 #define FEATURE_IRQ BIT(4)
292 #define FEATURE_HOST_NOTIFY BIT(5)
293 /* Not really a feature, but it's convenient to handle it as such */
294 #define FEATURE_IDF BIT(15)
295 #define FEATURE_TCO BIT(16)
297 static const char *i801_feature_names[] = {
300 "Block process call",
306 static unsigned int disable_features;
307 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
308 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
309 "\t\t 0x01 disable SMBus PEC\n"
310 "\t\t 0x02 disable the block buffer\n"
311 "\t\t 0x08 disable the I2C block read functionality\n"
312 "\t\t 0x10 don't use interrupts\n"
313 "\t\t 0x20 disable SMBus Host Notify ");
315 /* Make sure the SMBus host is ready to start transmitting.
316 Return 0 if it is, -EBUSY if it is not. */
317 static int i801_check_pre(struct i801_priv *priv)
321 status = inb_p(SMBHSTSTS(priv));
322 if (status & SMBHSTSTS_HOST_BUSY) {
323 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
327 status &= STATUS_FLAGS;
329 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
331 outb_p(status, SMBHSTSTS(priv));
332 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
334 dev_err(&priv->pci_dev->dev,
335 "Failed clearing status flags (%02x)\n",
342 * Clear CRC status if needed.
343 * During normal operation, i801_check_post() takes care
344 * of it after every operation. We do it here only in case
345 * the hardware was already in this state when the driver
348 if (priv->features & FEATURE_SMBUS_PEC) {
349 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
351 dev_dbg(&priv->pci_dev->dev,
352 "Clearing aux status flags (%02x)\n", status);
353 outb_p(status, SMBAUXSTS(priv));
354 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
356 dev_err(&priv->pci_dev->dev,
357 "Failed clearing aux status flags (%02x)\n",
368 * Convert the status register to an error code, and clear it.
369 * Note that status only contains the bits we want to clear, not the
370 * actual register value.
372 static int i801_check_post(struct i801_priv *priv, int status)
377 * If the SMBus is still busy, we give up
378 * Note: This timeout condition only happens when using polling
379 * transactions. For interrupt operation, NAK/timeout is indicated by
382 if (unlikely(status < 0)) {
383 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
384 /* try to stop the current command */
385 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
386 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
388 usleep_range(1000, 2000);
389 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
392 /* Check if it worked */
393 status = inb_p(SMBHSTSTS(priv));
394 if ((status & SMBHSTSTS_HOST_BUSY) ||
395 !(status & SMBHSTSTS_FAILED))
396 dev_err(&priv->pci_dev->dev,
397 "Failed terminating the transaction\n");
398 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
402 if (status & SMBHSTSTS_FAILED) {
404 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
406 if (status & SMBHSTSTS_DEV_ERR) {
408 * This may be a PEC error, check and clear it.
410 * AUXSTS is handled differently from HSTSTS.
411 * For HSTSTS, i801_isr() or i801_wait_intr()
412 * has already cleared the error bits in hardware,
413 * and we are passed a copy of the original value
415 * For AUXSTS, the hardware register is left
416 * for us to handle here.
417 * This is asymmetric, slightly iffy, but safe,
418 * since all this code is serialized and the CRCE
419 * bit is harmless as long as it's cleared before
420 * the next operation.
422 if ((priv->features & FEATURE_SMBUS_PEC) &&
423 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
424 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
426 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
429 dev_dbg(&priv->pci_dev->dev, "No response\n");
432 if (status & SMBHSTSTS_BUS_ERR) {
434 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
437 /* Clear status flags except BYTE_DONE, to be cleared by caller */
438 outb_p(status, SMBHSTSTS(priv));
443 /* Wait for BUSY being cleared and either INTR or an error flag being set */
444 static int i801_wait_intr(struct i801_priv *priv)
449 /* We will always wait for a fraction of a second! */
451 usleep_range(250, 500);
452 status = inb_p(SMBHSTSTS(priv));
453 } while (((status & SMBHSTSTS_HOST_BUSY) ||
454 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
455 (timeout++ < MAX_RETRIES));
457 if (timeout > MAX_RETRIES) {
458 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
461 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
464 /* Wait for either BYTE_DONE or an error flag being set */
465 static int i801_wait_byte_done(struct i801_priv *priv)
470 /* We will always wait for a fraction of a second! */
472 usleep_range(250, 500);
473 status = inb_p(SMBHSTSTS(priv));
474 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
475 (timeout++ < MAX_RETRIES));
477 if (timeout > MAX_RETRIES) {
478 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
481 return status & STATUS_ERROR_FLAGS;
484 static int i801_transaction(struct i801_priv *priv, int xact)
488 const struct i2c_adapter *adap = &priv->adapter;
490 result = i801_check_pre(priv);
494 if (priv->features & FEATURE_IRQ) {
495 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
497 result = wait_event_timeout(priv->waitq,
498 (status = priv->status),
502 dev_warn(&priv->pci_dev->dev,
503 "Timeout waiting for interrupt!\n");
506 return i801_check_post(priv, status);
509 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
510 * SMBSCMD are passed in xact */
511 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
513 status = i801_wait_intr(priv);
514 return i801_check_post(priv, status);
517 static int i801_block_transaction_by_block(struct i801_priv *priv,
518 union i2c_smbus_data *data,
519 char read_write, int command,
524 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
527 case I2C_SMBUS_BLOCK_PROC_CALL:
528 xact |= I801_BLOCK_PROC_CALL;
530 case I2C_SMBUS_BLOCK_DATA:
531 xact |= I801_BLOCK_DATA;
537 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
539 /* Use 32-byte buffer to process this transaction */
540 if (read_write == I2C_SMBUS_WRITE) {
541 len = data->block[0];
542 outb_p(len, SMBHSTDAT0(priv));
543 for (i = 0; i < len; i++)
544 outb_p(data->block[i+1], SMBBLKDAT(priv));
547 status = i801_transaction(priv, xact);
551 if (read_write == I2C_SMBUS_READ ||
552 command == I2C_SMBUS_BLOCK_PROC_CALL) {
553 len = inb_p(SMBHSTDAT0(priv));
554 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
557 data->block[0] = len;
558 for (i = 0; i < len; i++)
559 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
564 static void i801_isr_byte_done(struct i801_priv *priv)
567 /* For SMBus block reads, length is received with first byte */
568 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
569 (priv->count == 0)) {
570 priv->len = inb_p(SMBHSTDAT0(priv));
571 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
572 dev_err(&priv->pci_dev->dev,
573 "Illegal SMBus block read size %d\n",
576 priv->len = I2C_SMBUS_BLOCK_MAX;
578 dev_dbg(&priv->pci_dev->dev,
579 "SMBus block read size is %d\n",
582 priv->data[-1] = priv->len;
586 if (priv->count < priv->len)
587 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
589 dev_dbg(&priv->pci_dev->dev,
590 "Discarding extra byte on block read\n");
592 /* Set LAST_BYTE for last byte of read transaction */
593 if (priv->count == priv->len - 1)
594 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
596 } else if (priv->count < priv->len - 1) {
597 /* Write next byte, except for IRQ after last byte */
598 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
601 /* Clear BYTE_DONE to continue with next byte */
602 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
605 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
609 addr = inb_p(SMBNTFDADD(priv)) >> 1;
612 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
613 * always returns 0. Our current implementation doesn't provide
614 * data, so we just ignore it.
616 i2c_handle_smbus_host_notify(&priv->adapter, addr);
618 /* clear Host Notify bit and return */
619 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
624 * There are three kinds of interrupts:
626 * 1) i801 signals transaction completion with one of these interrupts:
628 * DEV_ERR - Invalid command, NAK or communication timeout
629 * BUS_ERR - SMI# transaction collision
630 * FAILED - transaction was canceled due to a KILL request
631 * When any of these occur, update ->status and wake up the waitq.
632 * ->status must be cleared before kicking off the next transaction.
634 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
635 * occurs for each byte of a byte-by-byte to prepare the next byte.
637 * 3) Host Notify interrupts
639 static irqreturn_t i801_isr(int irq, void *dev_id)
641 struct i801_priv *priv = dev_id;
645 /* Confirm this is our interrupt */
646 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
647 if (!(pcists & SMBPCISTS_INTS))
650 if (priv->features & FEATURE_HOST_NOTIFY) {
651 status = inb_p(SMBSLVSTS(priv));
652 if (status & SMBSLVSTS_HST_NTFY_STS)
653 return i801_host_notify_isr(priv);
656 status = inb_p(SMBHSTSTS(priv));
657 if (status & SMBHSTSTS_BYTE_DONE)
658 i801_isr_byte_done(priv);
661 * Clear irq sources and report transaction result.
662 * ->status must be cleared before the next transaction is started.
664 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
666 outb_p(status, SMBHSTSTS(priv));
667 priv->status = status;
668 wake_up(&priv->waitq);
675 * For "byte-by-byte" block transactions:
676 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
677 * I2C read uses cmd=I801_I2C_BLOCK_DATA
679 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
680 union i2c_smbus_data *data,
681 char read_write, int command,
688 const struct i2c_adapter *adap = &priv->adapter;
690 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
693 result = i801_check_pre(priv);
697 len = data->block[0];
699 if (read_write == I2C_SMBUS_WRITE) {
700 outb_p(len, SMBHSTDAT0(priv));
701 outb_p(data->block[1], SMBBLKDAT(priv));
704 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
705 read_write == I2C_SMBUS_READ)
706 smbcmd = I801_I2C_BLOCK_DATA;
708 smbcmd = I801_BLOCK_DATA;
710 if (priv->features & FEATURE_IRQ) {
711 priv->is_read = (read_write == I2C_SMBUS_READ);
712 if (len == 1 && priv->is_read)
713 smbcmd |= SMBHSTCNT_LAST_BYTE;
714 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
717 priv->data = &data->block[1];
719 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
720 result = wait_event_timeout(priv->waitq,
721 (status = priv->status),
725 dev_warn(&priv->pci_dev->dev,
726 "Timeout waiting for interrupt!\n");
729 return i801_check_post(priv, status);
732 for (i = 1; i <= len; i++) {
733 if (i == len && read_write == I2C_SMBUS_READ)
734 smbcmd |= SMBHSTCNT_LAST_BYTE;
735 outb_p(smbcmd, SMBHSTCNT(priv));
738 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
741 status = i801_wait_byte_done(priv);
745 if (i == 1 && read_write == I2C_SMBUS_READ
746 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
747 len = inb_p(SMBHSTDAT0(priv));
748 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
749 dev_err(&priv->pci_dev->dev,
750 "Illegal SMBus block read size %d\n",
753 while (inb_p(SMBHSTSTS(priv)) &
755 outb_p(SMBHSTSTS_BYTE_DONE,
757 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
760 data->block[0] = len;
763 /* Retrieve/store value in SMBBLKDAT */
764 if (read_write == I2C_SMBUS_READ)
765 data->block[i] = inb_p(SMBBLKDAT(priv));
766 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
767 outb_p(data->block[i+1], SMBBLKDAT(priv));
769 /* signals SMBBLKDAT ready */
770 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
773 status = i801_wait_intr(priv);
775 return i801_check_post(priv, status);
778 static int i801_set_block_buffer_mode(struct i801_priv *priv)
780 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
781 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
786 /* Block transaction function */
787 static int i801_block_transaction(struct i801_priv *priv,
788 union i2c_smbus_data *data, char read_write,
789 int command, int hwpec)
794 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
795 if (read_write == I2C_SMBUS_WRITE) {
796 /* set I2C_EN bit in configuration register */
797 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
798 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
799 hostc | SMBHSTCFG_I2C_EN);
800 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
801 dev_err(&priv->pci_dev->dev,
802 "I2C block read is unsupported!\n");
807 if (read_write == I2C_SMBUS_WRITE
808 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
809 if (data->block[0] < 1)
811 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
812 data->block[0] = I2C_SMBUS_BLOCK_MAX;
814 data->block[0] = 32; /* max for SMBus block reads */
817 /* Experience has shown that the block buffer can only be used for
818 SMBus (not I2C) block transactions, even though the datasheet
819 doesn't mention this limitation. */
820 if ((priv->features & FEATURE_BLOCK_BUFFER)
821 && command != I2C_SMBUS_I2C_BLOCK_DATA
822 && i801_set_block_buffer_mode(priv) == 0)
823 result = i801_block_transaction_by_block(priv, data,
827 result = i801_block_transaction_byte_by_byte(priv, data,
831 if (command == I2C_SMBUS_I2C_BLOCK_DATA
832 && read_write == I2C_SMBUS_WRITE) {
833 /* restore saved configuration register value */
834 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
839 /* Return negative errno on error. */
840 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
841 unsigned short flags, char read_write, u8 command,
842 int size, union i2c_smbus_data *data)
846 int ret = 0, xact = 0;
847 struct i801_priv *priv = i2c_get_adapdata(adap);
849 mutex_lock(&priv->acpi_lock);
850 if (priv->acpi_reserved) {
851 mutex_unlock(&priv->acpi_lock);
855 pm_runtime_get_sync(&priv->pci_dev->dev);
857 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
858 && size != I2C_SMBUS_QUICK
859 && size != I2C_SMBUS_I2C_BLOCK_DATA;
862 case I2C_SMBUS_QUICK:
863 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
868 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
870 if (read_write == I2C_SMBUS_WRITE)
871 outb_p(command, SMBHSTCMD(priv));
874 case I2C_SMBUS_BYTE_DATA:
875 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
877 outb_p(command, SMBHSTCMD(priv));
878 if (read_write == I2C_SMBUS_WRITE)
879 outb_p(data->byte, SMBHSTDAT0(priv));
880 xact = I801_BYTE_DATA;
882 case I2C_SMBUS_WORD_DATA:
883 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
885 outb_p(command, SMBHSTCMD(priv));
886 if (read_write == I2C_SMBUS_WRITE) {
887 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
888 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
890 xact = I801_WORD_DATA;
892 case I2C_SMBUS_BLOCK_DATA:
893 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
895 outb_p(command, SMBHSTCMD(priv));
898 case I2C_SMBUS_I2C_BLOCK_DATA:
900 * NB: page 240 of ICH5 datasheet shows that the R/#W
901 * bit should be cleared here, even when reading.
902 * However if SPD Write Disable is set (Lynx Point and later),
903 * the read will fail if we don't set the R/#W bit.
905 outb_p(((addr & 0x7f) << 1) |
906 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
907 (read_write & 0x01) : 0),
909 if (read_write == I2C_SMBUS_READ) {
910 /* NB: page 240 of ICH5 datasheet also shows
911 * that DATA1 is the cmd field when reading */
912 outb_p(command, SMBHSTDAT1(priv));
914 outb_p(command, SMBHSTCMD(priv));
917 case I2C_SMBUS_BLOCK_PROC_CALL:
919 * Bit 0 of the slave address register always indicate a write
922 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
923 outb_p(command, SMBHSTCMD(priv));
927 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
933 if (hwpec) /* enable/disable hardware PEC */
934 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
936 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
940 ret = i801_block_transaction(priv, data, read_write, size,
943 ret = i801_transaction(priv, xact);
945 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
946 time, so we forcibly disable it after every transaction. Turn off
947 E32B for the same reason. */
949 outb_p(inb_p(SMBAUXCTL(priv)) &
950 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
956 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
959 switch (xact & 0x7f) {
960 case I801_BYTE: /* Result put in SMBHSTDAT0 */
962 data->byte = inb_p(SMBHSTDAT0(priv));
965 data->word = inb_p(SMBHSTDAT0(priv)) +
966 (inb_p(SMBHSTDAT1(priv)) << 8);
971 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
972 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
973 mutex_unlock(&priv->acpi_lock);
978 static u32 i801_func(struct i2c_adapter *adapter)
980 struct i801_priv *priv = i2c_get_adapdata(adapter);
982 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
983 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
984 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
985 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
986 ((priv->features & FEATURE_BLOCK_PROC) ?
987 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
988 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
989 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
990 ((priv->features & FEATURE_HOST_NOTIFY) ?
991 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
994 static void i801_enable_host_notify(struct i2c_adapter *adapter)
996 struct i801_priv *priv = i2c_get_adapdata(adapter);
998 if (!(priv->features & FEATURE_HOST_NOTIFY))
1001 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1002 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1005 /* clear Host Notify bit to allow a new notification */
1006 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1009 static void i801_disable_host_notify(struct i801_priv *priv)
1011 if (!(priv->features & FEATURE_HOST_NOTIFY))
1014 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1017 static const struct i2c_algorithm smbus_algorithm = {
1018 .smbus_xfer = i801_access,
1019 .functionality = i801_func,
1022 static const struct pci_device_id i801_ids[] = {
1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1076 MODULE_DEVICE_TABLE(pci, i801_ids);
1078 #if defined CONFIG_X86 && defined CONFIG_DMI
1079 static unsigned char apanel_addr;
1081 /* Scan the system ROM for the signature "FJKEYINF" */
1082 static __init const void __iomem *bios_signature(const void __iomem *bios)
1085 const unsigned char signature[] = "FJKEYINF";
1087 for (offset = 0; offset < 0x10000; offset += 0x10) {
1088 if (check_signature(bios + offset, signature,
1089 sizeof(signature)-1))
1090 return bios + offset;
1095 static void __init input_apanel_init(void)
1098 const void __iomem *p;
1100 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1101 p = bios_signature(bios);
1103 /* just use the first address */
1104 apanel_addr = readb(p + 8 + 3) >> 1;
1109 struct dmi_onboard_device_info {
1112 unsigned short i2c_addr;
1113 const char *i2c_type;
1116 static const struct dmi_onboard_device_info dmi_devices[] = {
1117 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1118 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1119 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1122 static void dmi_check_onboard_device(u8 type, const char *name,
1123 struct i2c_adapter *adap)
1126 struct i2c_board_info info;
1128 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1129 /* & ~0x80, ignore enabled/disabled bit */
1130 if ((type & ~0x80) != dmi_devices[i].type)
1132 if (strcasecmp(name, dmi_devices[i].name))
1135 memset(&info, 0, sizeof(struct i2c_board_info));
1136 info.addr = dmi_devices[i].i2c_addr;
1137 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1138 i2c_new_device(adap, &info);
1143 /* We use our own function to check for onboard devices instead of
1144 dmi_find_device() as some buggy BIOS's have the devices we are interested
1145 in marked as disabled */
1146 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1153 count = (dm->length - sizeof(struct dmi_header)) / 2;
1154 for (i = 0; i < count; i++) {
1155 const u8 *d = (char *)(dm + 1) + (i * 2);
1156 const char *name = ((char *) dm) + dm->length;
1163 while (s > 0 && name[0]) {
1164 name += strlen(name) + 1;
1167 if (name[0] == 0) /* Bogus string reference */
1170 dmi_check_onboard_device(type, name, adap);
1174 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1175 static const char *const acpi_smo8800_ids[] = {
1186 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1189 void **return_value)
1191 struct acpi_device_info *info;
1196 status = acpi_get_object_info(obj_handle, &info);
1197 if (ACPI_FAILURE(status))
1200 if (!(info->valid & ACPI_VALID_HID))
1201 goto smo88xx_not_found;
1203 hid = info->hardware_id.string;
1205 goto smo88xx_not_found;
1207 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1209 goto smo88xx_not_found;
1213 *((bool *)return_value) = true;
1214 return AE_CTRL_TERMINATE;
1221 static bool is_dell_system_with_lis3lv02d(void)
1226 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1227 if (!vendor || strcmp(vendor, "Dell Inc."))
1231 * Check that ACPI device SMO88xx is present and is functioning.
1232 * Function acpi_get_devices() already filters all ACPI devices
1233 * which are not present or are not functioning.
1234 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1235 * accelerometer but unfortunately ACPI does not provide any other
1236 * information (like I2C address).
1239 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1246 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1247 * so it is needed to define mapping table based on DMI product names.
1249 static const struct {
1250 const char *dmi_product_name;
1251 unsigned short i2c_addr;
1252 } dell_lis3lv02d_devices[] = {
1254 * Dell platform team told us that these Latitude devices have
1255 * ST microelectronics accelerometer at I2C address 0x29.
1257 { "Latitude E5250", 0x29 },
1258 { "Latitude E5450", 0x29 },
1259 { "Latitude E5550", 0x29 },
1260 { "Latitude E6440", 0x29 },
1261 { "Latitude E6440 ATG", 0x29 },
1262 { "Latitude E6540", 0x29 },
1264 * Additional individual entries were added after verification.
1266 { "Vostro V131", 0x1d },
1269 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1271 struct i2c_board_info info;
1272 const char *dmi_product_name;
1275 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1276 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1277 if (strcmp(dmi_product_name,
1278 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1282 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1283 dev_warn(&priv->pci_dev->dev,
1284 "Accelerometer lis3lv02d is present on SMBus but its"
1285 " address is unknown, skipping registration\n");
1289 memset(&info, 0, sizeof(struct i2c_board_info));
1290 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1291 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1292 i2c_new_device(&priv->adapter, &info);
1295 /* Register optional slaves */
1296 static void i801_probe_optional_slaves(struct i801_priv *priv)
1298 /* Only register slaves on main SMBus channel */
1299 if (priv->features & FEATURE_IDF)
1303 struct i2c_board_info info;
1305 memset(&info, 0, sizeof(struct i2c_board_info));
1306 info.addr = apanel_addr;
1307 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1308 i2c_new_device(&priv->adapter, &info);
1311 if (dmi_name_in_vendors("FUJITSU"))
1312 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1314 if (is_dell_system_with_lis3lv02d())
1315 register_dell_lis3lv02d_i2c_device(priv);
1318 static void __init input_apanel_init(void) {}
1319 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1320 #endif /* CONFIG_X86 && CONFIG_DMI */
1322 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1323 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1324 .gpio_chip = "gpio_ich",
1325 .values = { 0x02, 0x03 },
1327 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1328 .gpios = { 52, 53 },
1332 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1333 .gpio_chip = "gpio_ich",
1334 .values = { 0x02, 0x03, 0x01 },
1336 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1337 .gpios = { 52, 53 },
1341 static const struct dmi_system_id mux_dmi_table[] = {
1344 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1345 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1347 .driver_data = &i801_mux_config_asus_z8_d12,
1351 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1352 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1354 .driver_data = &i801_mux_config_asus_z8_d12,
1358 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1359 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1361 .driver_data = &i801_mux_config_asus_z8_d12,
1365 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1366 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1368 .driver_data = &i801_mux_config_asus_z8_d12,
1372 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1373 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1375 .driver_data = &i801_mux_config_asus_z8_d12,
1379 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1380 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1382 .driver_data = &i801_mux_config_asus_z8_d12,
1386 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1387 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1389 .driver_data = &i801_mux_config_asus_z8_d18,
1393 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1394 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1396 .driver_data = &i801_mux_config_asus_z8_d18,
1400 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1401 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1403 .driver_data = &i801_mux_config_asus_z8_d12,
1408 /* Setup multiplexing if needed */
1409 static int i801_add_mux(struct i801_priv *priv)
1411 struct device *dev = &priv->adapter.dev;
1412 const struct i801_mux_config *mux_config;
1413 struct i2c_mux_gpio_platform_data gpio_data;
1414 struct gpiod_lookup_table *lookup;
1417 if (!priv->mux_drvdata)
1419 mux_config = priv->mux_drvdata;
1421 /* Prepare the platform data */
1422 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1423 gpio_data.parent = priv->adapter.nr;
1424 gpio_data.values = mux_config->values;
1425 gpio_data.n_values = mux_config->n_values;
1426 gpio_data.classes = mux_config->classes;
1427 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1429 /* Register GPIO descriptor lookup table */
1430 lookup = devm_kzalloc(dev,
1431 struct_size(lookup, table, mux_config->n_gpios),
1435 lookup->dev_id = "i2c-mux-gpio";
1436 for (i = 0; i < mux_config->n_gpios; i++) {
1437 lookup->table[i].chip_label = mux_config->gpio_chip;
1438 lookup->table[i].chip_hwnum = mux_config->gpios[i];
1439 lookup->table[i].con_id = "mux";
1441 gpiod_add_lookup_table(lookup);
1442 priv->lookup = lookup;
1445 * Register the mux device, we use PLATFORM_DEVID_NONE here
1446 * because since we are referring to the GPIO chip by name we are
1447 * anyways in deep trouble if there is more than one of these
1448 * devices, and there should likely only be one platform controller
1451 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1452 PLATFORM_DEVID_NONE, &gpio_data,
1453 sizeof(struct i2c_mux_gpio_platform_data));
1454 if (IS_ERR(priv->mux_pdev)) {
1455 err = PTR_ERR(priv->mux_pdev);
1456 gpiod_remove_lookup_table(lookup);
1457 priv->mux_pdev = NULL;
1458 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1465 static void i801_del_mux(struct i801_priv *priv)
1468 platform_device_unregister(priv->mux_pdev);
1470 gpiod_remove_lookup_table(priv->lookup);
1473 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1475 const struct dmi_system_id *id;
1476 const struct i801_mux_config *mux_config;
1477 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1480 id = dmi_first_match(mux_dmi_table);
1482 /* Remove branch classes from trunk */
1483 mux_config = id->driver_data;
1484 for (i = 0; i < mux_config->n_values; i++)
1485 class &= ~mux_config->classes[i];
1487 /* Remember for later */
1488 priv->mux_drvdata = mux_config;
1494 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1495 static inline void i801_del_mux(struct i801_priv *priv) { }
1497 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1499 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1503 static const struct itco_wdt_platform_data tco_platform_data = {
1504 .name = "Intel PCH",
1508 static DEFINE_SPINLOCK(p2sb_spinlock);
1510 static void i801_add_tco(struct i801_priv *priv)
1512 struct pci_dev *pci_dev = priv->pci_dev;
1513 struct resource tco_res[3], *res;
1514 struct platform_device *pdev;
1516 u32 tco_base, tco_ctl;
1517 u32 base_addr, ctrl_val;
1521 if (!(priv->features & FEATURE_TCO))
1524 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1525 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1526 if (!(tco_ctl & TCOCTL_EN))
1529 memset(tco_res, 0, sizeof(tco_res));
1531 res = &tco_res[ICH_RES_IO_TCO];
1532 res->start = tco_base & ~1;
1533 res->end = res->start + 32 - 1;
1534 res->flags = IORESOURCE_IO;
1537 * Power Management registers.
1539 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1540 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1542 res = &tco_res[ICH_RES_IO_SMI];
1543 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1544 res->end = res->start + 3;
1545 res->flags = IORESOURCE_IO;
1548 * Enable the ACPI I/O space.
1550 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1551 ctrl_val |= ACPICTRL_EN;
1552 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1555 * We must access the NO_REBOOT bit over the Primary to Sideband
1556 * bridge (P2SB). The BIOS prevents the P2SB device from being
1557 * enumerated by the PCI subsystem, so we need to unhide/hide it
1558 * to lookup the P2SB BAR.
1560 spin_lock(&p2sb_spinlock);
1562 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1564 /* Unhide the P2SB device, if it is hidden */
1565 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1567 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1569 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1570 base64_addr = base_addr & 0xfffffff0;
1572 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1573 base64_addr |= (u64)base_addr << 32;
1575 /* Hide the P2SB device, if it was hidden before */
1577 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1578 spin_unlock(&p2sb_spinlock);
1580 res = &tco_res[ICH_RES_MEM_OFF];
1581 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1582 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1584 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1586 res->end = res->start + 3;
1587 res->flags = IORESOURCE_MEM;
1589 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1590 tco_res, 3, &tco_platform_data,
1591 sizeof(tco_platform_data));
1593 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1597 priv->tco_pdev = pdev;
1601 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1602 acpi_physical_address address)
1604 return address >= priv->smba &&
1605 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1609 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1610 u64 *value, void *handler_context, void *region_context)
1612 struct i801_priv *priv = handler_context;
1613 struct pci_dev *pdev = priv->pci_dev;
1617 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1618 * further access from the driver itself. This device is now owned
1619 * by the system firmware.
1621 mutex_lock(&priv->acpi_lock);
1623 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1624 priv->acpi_reserved = true;
1626 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1627 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1630 * BIOS is accessing the host controller so prevent it from
1631 * suspending automatically from now on.
1633 pm_runtime_get_sync(&pdev->dev);
1636 if ((function & ACPI_IO_MASK) == ACPI_READ)
1637 status = acpi_os_read_port(address, (u32 *)value, bits);
1639 status = acpi_os_write_port(address, (u32)*value, bits);
1641 mutex_unlock(&priv->acpi_lock);
1646 static int i801_acpi_probe(struct i801_priv *priv)
1648 struct acpi_device *adev;
1651 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1653 status = acpi_install_address_space_handler(adev->handle,
1654 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1656 if (ACPI_SUCCESS(status))
1660 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1663 static void i801_acpi_remove(struct i801_priv *priv)
1665 struct acpi_device *adev;
1667 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1671 acpi_remove_address_space_handler(adev->handle,
1672 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1674 mutex_lock(&priv->acpi_lock);
1675 if (priv->acpi_reserved)
1676 pm_runtime_put(&priv->pci_dev->dev);
1677 mutex_unlock(&priv->acpi_lock);
1680 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1681 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1684 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1688 struct i801_priv *priv;
1690 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1694 i2c_set_adapdata(&priv->adapter, priv);
1695 priv->adapter.owner = THIS_MODULE;
1696 priv->adapter.class = i801_get_adapter_class(priv);
1697 priv->adapter.algo = &smbus_algorithm;
1698 priv->adapter.dev.parent = &dev->dev;
1699 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1700 priv->adapter.retries = 3;
1701 mutex_init(&priv->acpi_lock);
1703 priv->pci_dev = dev;
1704 switch (dev->device) {
1705 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1706 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1707 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1708 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1709 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1710 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1711 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1712 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1713 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1714 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1715 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1716 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1717 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1718 priv->features |= FEATURE_BLOCK_PROC;
1719 priv->features |= FEATURE_I2C_BLOCK_READ;
1720 priv->features |= FEATURE_IRQ;
1721 priv->features |= FEATURE_SMBUS_PEC;
1722 priv->features |= FEATURE_BLOCK_BUFFER;
1723 /* If we have ACPI based watchdog use that instead */
1724 if (!acpi_has_watchdog())
1725 priv->features |= FEATURE_TCO;
1726 priv->features |= FEATURE_HOST_NOTIFY;
1729 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1730 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1731 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1732 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1733 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1734 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1735 priv->features |= FEATURE_IDF;
1738 priv->features |= FEATURE_BLOCK_PROC;
1739 priv->features |= FEATURE_I2C_BLOCK_READ;
1740 priv->features |= FEATURE_IRQ;
1742 case PCI_DEVICE_ID_INTEL_82801DB_3:
1743 priv->features |= FEATURE_SMBUS_PEC;
1744 priv->features |= FEATURE_BLOCK_BUFFER;
1746 case PCI_DEVICE_ID_INTEL_82801CA_3:
1747 priv->features |= FEATURE_HOST_NOTIFY;
1749 case PCI_DEVICE_ID_INTEL_82801BA_2:
1750 case PCI_DEVICE_ID_INTEL_82801AB_3:
1751 case PCI_DEVICE_ID_INTEL_82801AA_3:
1755 /* Disable features on user request */
1756 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1757 if (priv->features & disable_features & (1 << i))
1758 dev_notice(&dev->dev, "%s disabled by user\n",
1759 i801_feature_names[i]);
1761 priv->features &= ~disable_features;
1763 err = pcim_enable_device(dev);
1765 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1769 pcim_pin_device(dev);
1771 /* Determine the address of the SMBus area */
1772 priv->smba = pci_resource_start(dev, SMBBAR);
1775 "SMBus base address uninitialized, upgrade BIOS\n");
1779 if (i801_acpi_probe(priv))
1782 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1783 dev_driver_string(&dev->dev));
1786 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1788 (unsigned long long)pci_resource_end(dev, SMBBAR));
1789 i801_acpi_remove(priv);
1793 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1794 priv->original_hstcfg = temp;
1795 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1796 if (!(temp & SMBHSTCFG_HST_EN)) {
1797 dev_info(&dev->dev, "Enabling SMBus device\n");
1798 temp |= SMBHSTCFG_HST_EN;
1800 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1802 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1803 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1804 /* Disable SMBus interrupt feature if SMBus using SMI# */
1805 priv->features &= ~FEATURE_IRQ;
1807 if (temp & SMBHSTCFG_SPD_WD)
1808 dev_info(&dev->dev, "SPD Write Disable is set\n");
1810 /* Clear special mode bits */
1811 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1812 outb_p(inb_p(SMBAUXCTL(priv)) &
1813 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1815 /* Remember original Host Notify setting */
1816 if (priv->features & FEATURE_HOST_NOTIFY)
1817 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1819 /* Default timeout in interrupt mode: 200 ms */
1820 priv->adapter.timeout = HZ / 5;
1822 if (dev->irq == IRQ_NOTCONNECTED)
1823 priv->features &= ~FEATURE_IRQ;
1825 if (priv->features & FEATURE_IRQ) {
1828 /* Complain if an interrupt is already pending */
1829 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1830 if (pcists & SMBPCISTS_INTS)
1831 dev_warn(&dev->dev, "An interrupt is pending!\n");
1833 /* Check if interrupts have been disabled */
1834 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1835 if (pcictl & SMBPCICTL_INTDIS) {
1836 dev_info(&dev->dev, "Interrupts are disabled\n");
1837 priv->features &= ~FEATURE_IRQ;
1841 if (priv->features & FEATURE_IRQ) {
1842 init_waitqueue_head(&priv->waitq);
1844 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1846 dev_driver_string(&dev->dev), priv);
1848 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1850 priv->features &= ~FEATURE_IRQ;
1853 dev_info(&dev->dev, "SMBus using %s\n",
1854 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1858 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1859 "SMBus I801 adapter at %04lx", priv->smba);
1860 err = i2c_add_adapter(&priv->adapter);
1862 i801_acpi_remove(priv);
1866 i801_enable_host_notify(&priv->adapter);
1868 i801_probe_optional_slaves(priv);
1869 /* We ignore errors - multiplexing is optional */
1872 pci_set_drvdata(dev, priv);
1874 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1875 pm_runtime_use_autosuspend(&dev->dev);
1876 pm_runtime_put_autosuspend(&dev->dev);
1877 pm_runtime_allow(&dev->dev);
1882 static void i801_remove(struct pci_dev *dev)
1884 struct i801_priv *priv = pci_get_drvdata(dev);
1886 pm_runtime_forbid(&dev->dev);
1887 pm_runtime_get_noresume(&dev->dev);
1889 i801_disable_host_notify(priv);
1891 i2c_del_adapter(&priv->adapter);
1892 i801_acpi_remove(priv);
1893 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1895 platform_device_unregister(priv->tco_pdev);
1898 * do not call pci_disable_device(dev) since it can cause hard hangs on
1899 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1903 static void i801_shutdown(struct pci_dev *dev)
1905 struct i801_priv *priv = pci_get_drvdata(dev);
1907 /* Restore config registers to avoid hard hang on some systems */
1908 i801_disable_host_notify(priv);
1909 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1912 #ifdef CONFIG_PM_SLEEP
1913 static int i801_suspend(struct device *dev)
1915 struct pci_dev *pci_dev = to_pci_dev(dev);
1916 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1918 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1922 static int i801_resume(struct device *dev)
1924 struct pci_dev *pci_dev = to_pci_dev(dev);
1925 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1927 i801_enable_host_notify(&priv->adapter);
1933 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1935 static struct pci_driver i801_driver = {
1936 .name = "i801_smbus",
1937 .id_table = i801_ids,
1938 .probe = i801_probe,
1939 .remove = i801_remove,
1940 .shutdown = i801_shutdown,
1946 static int __init i2c_i801_init(void)
1948 if (dmi_name_in_vendors("FUJITSU"))
1949 input_apanel_init();
1950 return pci_register_driver(&i801_driver);
1953 static void __exit i2c_i801_exit(void)
1955 pci_unregister_driver(&i801_driver);
1958 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1959 MODULE_DESCRIPTION("I801 SMBus driver");
1960 MODULE_LICENSE("GPL");
1962 module_init(i2c_i801_init);
1963 module_exit(i2c_i801_exit);