1 // SPDX-License-Identifier: GPL-2.0-only
3 * This driver implements I2C master functionality using the LSI API2C
6 * NOTE: The controller has a limitation in that it can only do transfers of
7 * maximum 255 bytes at a time. If a larger transfer is attempted, error code
8 * (-EINVAL) is returned.
10 #include <linux/clk.h>
11 #include <linux/clkdev.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/platform_device.h>
22 #define SCL_WAIT_TIMEOUT_NS 25000000
23 #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
24 #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100))
28 #define GLOBAL_CONTROL 0x00
29 #define GLOBAL_MST_EN BIT(0)
30 #define GLOBAL_SLV_EN BIT(1)
31 #define GLOBAL_IBML_EN BIT(2)
32 #define INTERRUPT_STATUS 0x04
33 #define INTERRUPT_ENABLE 0x08
34 #define INT_SLV BIT(1)
35 #define INT_MST BIT(0)
36 #define WAIT_TIMER_CONTROL 0x0c
38 #define WT_VALUE(_x) ((_x) & 0x7fff)
39 #define IBML_TIMEOUT 0x10
40 #define IBML_LOW_MEXT 0x14
41 #define IBML_LOW_SEXT 0x18
42 #define TIMER_CLOCK_DIV 0x1c
43 #define I2C_BUS_MONITOR 0x20
44 #define BM_SDAC BIT(3)
45 #define BM_SCLC BIT(2)
46 #define BM_SDAS BIT(1)
47 #define BM_SCLS BIT(0)
48 #define SOFT_RESET 0x24
49 #define MST_COMMAND 0x28
50 #define CMD_BUSY (1<<3)
51 #define CMD_MANUAL (0x00 | CMD_BUSY)
52 #define CMD_AUTO (0x01 | CMD_BUSY)
53 #define CMD_SEQUENCE (0x02 | CMD_BUSY)
54 #define MST_RX_XFER 0x2c
55 #define MST_TX_XFER 0x30
56 #define MST_ADDR_1 0x34
57 #define MST_ADDR_2 0x38
59 #define MST_TX_FIFO 0x40
60 #define MST_RX_FIFO 0x44
61 #define MST_INT_ENABLE 0x48
62 #define MST_INT_STATUS 0x4c
63 #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */
64 #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */
65 #define MST_STATUS_SNS (1 << 11) /* Manual mode done */
66 #define MST_STATUS_SS (1 << 10) /* Automatic mode done */
67 #define MST_STATUS_SCC (1 << 9) /* Stop complete */
68 #define MST_STATUS_IP (1 << 8) /* Invalid parameter */
69 #define MST_STATUS_TSS (1 << 7) /* Timeout */
70 #define MST_STATUS_AL (1 << 6) /* Arbitration lost */
71 #define MST_STATUS_ND (1 << 5) /* NAK on data phase */
72 #define MST_STATUS_NA (1 << 4) /* NAK on address phase */
73 #define MST_STATUS_NAK (MST_STATUS_NA | \
75 #define MST_STATUS_ERR (MST_STATUS_NAK | \
78 #define MST_TX_BYTES_XFRD 0x50
79 #define MST_RX_BYTES_XFRD 0x54
80 #define SCL_HIGH_PERIOD 0x80
81 #define SCL_LOW_PERIOD 0x84
82 #define SPIKE_FLTR_LEN 0x88
83 #define SDA_SETUP_TIME 0x8c
84 #define SDA_HOLD_TIME 0x90
87 * axxia_i2c_dev - I2C device context
88 * @base: pointer to register struct
89 * @msg: pointer to current message
90 * @msg_r: pointer to current read message (sequence transfer)
91 * @msg_xfrd: number of bytes transferred in tx_fifo
92 * @msg_xfrd_r: number of bytes transferred in rx_fifo
93 * @msg_err: error code for completed message
94 * @msg_complete: xfer completion object
95 * @dev: device reference
96 * @adapter: core i2c abstraction
97 * @i2c_clk: clock reference for i2c input clock
98 * @bus_clk_rate: current i2c bus clock rate
99 * @last: a flag indicating is this is last message in transfer
101 struct axxia_i2c_dev {
104 struct i2c_msg *msg_r;
108 struct completion msg_complete;
110 struct i2c_adapter adapter;
116 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
120 int_en = readl(idev->base + MST_INT_ENABLE);
121 writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
124 static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask)
128 int_en = readl(idev->base + MST_INT_ENABLE);
129 writel(int_en | mask, idev->base + MST_INT_ENABLE);
133 * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency.
135 static u32 ns_to_clk(u64 ns, u32 clk_mhz)
137 return div_u64(ns * clk_mhz, 1000);
140 static int axxia_i2c_init(struct axxia_i2c_dev *idev)
142 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
143 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
148 unsigned long timeout;
150 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
151 idev->bus_clk_rate, clk_mhz, divisor);
153 /* Reset controller */
154 writel(0x01, idev->base + SOFT_RESET);
155 timeout = jiffies + msecs_to_jiffies(100);
156 while (readl(idev->base + SOFT_RESET) & 1) {
157 if (time_after(jiffies, timeout)) {
158 dev_warn(idev->dev, "Soft reset failed\n");
163 /* Enable Master Mode */
164 writel(0x1, idev->base + GLOBAL_CONTROL);
166 if (idev->bus_clk_rate <= 100000) {
167 /* Standard mode SCL 50/50, tSU:DAT = 250 ns */
168 t_high = divisor * 1 / 2;
169 t_low = divisor * 1 / 2;
170 t_setup = ns_to_clk(250, clk_mhz);
172 /* Fast mode SCL 33/66, tSU:DAT = 100 ns */
173 t_high = divisor * 1 / 3;
174 t_low = divisor * 2 / 3;
175 t_setup = ns_to_clk(100, clk_mhz);
179 writel(t_high, idev->base + SCL_HIGH_PERIOD);
181 writel(t_low, idev->base + SCL_LOW_PERIOD);
183 writel(t_setup, idev->base + SDA_SETUP_TIME);
184 /* SDA Hold Time, 300ns */
185 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
186 /* Filter <50ns spikes */
187 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
189 /* Configure Time-Out Registers */
190 tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz);
192 /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */
193 for (prescale = 0; prescale < 15; ++prescale) {
194 if (tmo_clk <= 0x7fff)
198 if (tmo_clk > 0x7fff)
201 /* Prescale divider (log2) */
202 writel(prescale, idev->base + TIMER_CLOCK_DIV);
203 /* Timeout in divided clocks */
204 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
206 /* Mask all master interrupt bits */
207 i2c_int_disable(idev, ~0);
209 /* Interrupt enable */
210 writel(0x01, idev->base + INTERRUPT_ENABLE);
215 static int i2c_m_rd(const struct i2c_msg *msg)
217 return (msg->flags & I2C_M_RD) != 0;
220 static int i2c_m_ten(const struct i2c_msg *msg)
222 return (msg->flags & I2C_M_TEN) != 0;
225 static int i2c_m_recv_len(const struct i2c_msg *msg)
227 return (msg->flags & I2C_M_RECV_LEN) != 0;
231 * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block
232 * transfer length if this is the first byte of such a transfer.
234 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
236 struct i2c_msg *msg = idev->msg_r;
237 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
238 int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r);
240 while (bytes_to_transfer-- > 0) {
241 int c = readl(idev->base + MST_DATA);
243 if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) {
245 * Check length byte for SMBus block read
247 if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) {
248 idev->msg_err = -EPROTO;
249 i2c_int_disable(idev, ~MST_STATUS_TSS);
250 complete(&idev->msg_complete);
254 writel(msg->len, idev->base + MST_RX_XFER);
256 msg->buf[idev->msg_xfrd_r++] = c;
263 * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
264 * @return: Number of bytes left to transfer.
266 static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev)
268 struct i2c_msg *msg = idev->msg;
269 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
270 int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd);
271 int ret = msg->len - idev->msg_xfrd - bytes_to_transfer;
273 while (bytes_to_transfer-- > 0)
274 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
279 static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
281 struct axxia_i2c_dev *idev = _dev;
284 if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST))
287 /* Read interrupt status bits */
288 status = readl(idev->base + MST_INT_STATUS);
291 dev_warn(idev->dev, "unexpected interrupt\n");
295 /* RX FIFO needs service? */
296 if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL))
297 axxia_i2c_empty_rx_fifo(idev);
299 /* TX FIFO needs service? */
300 if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) {
301 if (axxia_i2c_fill_tx_fifo(idev) == 0)
302 i2c_int_disable(idev, MST_STATUS_TFL);
305 if (unlikely(status & MST_STATUS_ERR)) {
307 i2c_int_disable(idev, ~0);
308 if (status & MST_STATUS_AL)
309 idev->msg_err = -EAGAIN;
310 else if (status & MST_STATUS_NAK)
311 idev->msg_err = -ENXIO;
313 idev->msg_err = -EIO;
314 dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n",
317 readl(idev->base + MST_RX_BYTES_XFRD),
318 readl(idev->base + MST_RX_XFER),
319 readl(idev->base + MST_TX_BYTES_XFRD),
320 readl(idev->base + MST_TX_XFER));
321 complete(&idev->msg_complete);
322 } else if (status & MST_STATUS_SCC) {
324 i2c_int_disable(idev, ~MST_STATUS_TSS);
325 complete(&idev->msg_complete);
326 } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) {
328 int mask = idev->last ? ~0 : ~MST_STATUS_TSS;
330 i2c_int_disable(idev, mask);
331 if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
332 axxia_i2c_empty_rx_fifo(idev);
333 complete(&idev->msg_complete);
334 } else if (status & MST_STATUS_TSS) {
335 /* Transfer timeout */
336 idev->msg_err = -ETIMEDOUT;
337 i2c_int_disable(idev, ~MST_STATUS_TSS);
338 complete(&idev->msg_complete);
342 /* Clear interrupt */
343 writel(INT_MST, idev->base + INTERRUPT_STATUS);
348 static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
352 if (i2c_m_ten(msg)) {
354 * addr_1: 5'b11110 | addr[9:8] | (R/nW)
357 addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06);
359 addr_1 |= 1; /* Set the R/nW bit of the address */
360 addr_2 = msg->addr & 0xFF;
363 * addr_1: addr[6:0] | (R/nW)
366 addr_1 = i2c_8bit_addr_from_msg(msg);
370 writel(addr_1, idev->base + MST_ADDR_1);
371 writel(addr_2, idev->base + MST_ADDR_2);
374 /* The NAK interrupt will be sent _before_ issuing STOP command
375 * so the controller might still be busy processing it. No
376 * interrupt will be sent at the end so we have to poll for it
378 static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev)
380 unsigned long timeout = jiffies + I2C_XFER_TIMEOUT;
383 if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
385 usleep_range(1, 100);
386 } while (time_before(jiffies, timeout));
391 static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
393 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;
394 u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;
395 unsigned long time_left;
397 axxia_i2c_set_addr(idev, &msgs[0]);
399 writel(msgs[0].len, idev->base + MST_TX_XFER);
400 writel(rlen, idev->base + MST_RX_XFER);
402 idev->msg = &msgs[0];
403 idev->msg_r = &msgs[1];
405 idev->msg_xfrd_r = 0;
407 axxia_i2c_fill_tx_fifo(idev);
409 writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
411 reinit_completion(&idev->msg_complete);
412 i2c_int_enable(idev, int_mask);
414 time_left = wait_for_completion_timeout(&idev->msg_complete,
417 if (idev->msg_err == -ENXIO) {
418 if (axxia_i2c_handle_seq_nak(idev))
419 axxia_i2c_init(idev);
420 } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
421 dev_warn(idev->dev, "busy after xfer\n");
424 if (time_left == 0) {
425 idev->msg_err = -ETIMEDOUT;
426 i2c_recover_bus(&idev->adapter);
427 axxia_i2c_init(idev);
430 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
431 axxia_i2c_init(idev);
433 return idev->msg_err;
436 static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg,
439 u32 int_mask = MST_STATUS_ERR;
440 u32 rx_xfer, tx_xfer;
441 unsigned long time_left;
442 unsigned int wt_value;
447 idev->msg_xfrd_r = 0;
449 reinit_completion(&idev->msg_complete);
451 axxia_i2c_set_addr(idev, msg);
454 /* I2C read transfer */
455 rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
458 /* I2C write transfer */
463 writel(rx_xfer, idev->base + MST_RX_XFER);
464 writel(tx_xfer, idev->base + MST_TX_XFER);
467 int_mask |= MST_STATUS_RFL;
468 else if (axxia_i2c_fill_tx_fifo(idev) != 0)
469 int_mask |= MST_STATUS_TFL;
471 wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL));
472 /* Disable wait timer temporarly */
473 writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
474 /* Check if timeout error happened */
479 writel(CMD_MANUAL, idev->base + MST_COMMAND);
480 int_mask |= MST_STATUS_SNS;
482 writel(CMD_AUTO, idev->base + MST_COMMAND);
483 int_mask |= MST_STATUS_SS;
486 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
488 i2c_int_enable(idev, int_mask);
490 time_left = wait_for_completion_timeout(&idev->msg_complete,
493 i2c_int_disable(idev, int_mask);
495 if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
496 dev_warn(idev->dev, "busy after xfer\n");
498 if (time_left == 0) {
499 idev->msg_err = -ETIMEDOUT;
500 i2c_recover_bus(&idev->adapter);
501 axxia_i2c_init(idev);
505 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO &&
506 idev->msg_err != -ETIMEDOUT)
507 axxia_i2c_init(idev);
509 return idev->msg_err;
512 /* This function checks if the msgs[] array contains messages compatible with
513 * Sequence mode of operation. This mode assumes there will be exactly one
514 * write of non-zero length followed by exactly one read of non-zero length,
515 * both targeted at the same client device.
517 static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num)
519 return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) &&
520 msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE &&
521 msgs[1].len > 0 && msgs[0].addr == msgs[1].addr;
525 axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
527 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
533 if (axxia_i2c_sequence_ok(msgs, num)) {
534 ret = axxia_i2c_xfer_seq(idev, msgs);
535 return ret ? : SEQ_LEN;
538 i2c_int_enable(idev, MST_STATUS_TSS);
540 for (i = 0; ret == 0 && i < num; ++i)
541 ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1));
546 static int axxia_i2c_get_scl(struct i2c_adapter *adap)
548 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
550 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
553 static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
555 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
558 /* Preserve SDA Control */
559 tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
562 writel(tmp, idev->base + I2C_BUS_MONITOR);
565 static int axxia_i2c_get_sda(struct i2c_adapter *adap)
567 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
569 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
572 static struct i2c_bus_recovery_info axxia_i2c_recovery_info = {
573 .recover_bus = i2c_generic_scl_recovery,
574 .get_scl = axxia_i2c_get_scl,
575 .set_scl = axxia_i2c_set_scl,
576 .get_sda = axxia_i2c_get_sda,
579 static u32 axxia_i2c_func(struct i2c_adapter *adap)
581 u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
582 I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA);
586 static const struct i2c_algorithm axxia_i2c_algo = {
587 .master_xfer = axxia_i2c_xfer,
588 .functionality = axxia_i2c_func,
591 static const struct i2c_adapter_quirks axxia_i2c_quirks = {
593 .max_write_len = 255,
596 static int axxia_i2c_probe(struct platform_device *pdev)
598 struct device_node *np = pdev->dev.of_node;
599 struct axxia_i2c_dev *idev = NULL;
600 struct resource *res;
605 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
609 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
610 base = devm_ioremap_resource(&pdev->dev, res);
612 return PTR_ERR(base);
614 irq = platform_get_irq(pdev, 0);
616 dev_err(&pdev->dev, "missing interrupt resource\n");
620 idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
621 if (IS_ERR(idev->i2c_clk)) {
622 dev_err(&pdev->dev, "missing clock\n");
623 return PTR_ERR(idev->i2c_clk);
627 idev->dev = &pdev->dev;
628 init_completion(&idev->msg_complete);
630 of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
631 if (idev->bus_clk_rate == 0)
632 idev->bus_clk_rate = 100000; /* default clock rate */
634 ret = clk_prepare_enable(idev->i2c_clk);
636 dev_err(&pdev->dev, "failed to enable clock\n");
640 ret = axxia_i2c_init(idev);
642 dev_err(&pdev->dev, "failed to initialize\n");
643 goto error_disable_clk;
646 ret = devm_request_irq(&pdev->dev, irq, axxia_i2c_isr, 0,
649 dev_err(&pdev->dev, "failed to claim IRQ%d\n", irq);
650 goto error_disable_clk;
653 i2c_set_adapdata(&idev->adapter, idev);
654 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
655 idev->adapter.owner = THIS_MODULE;
656 idev->adapter.algo = &axxia_i2c_algo;
657 idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
658 idev->adapter.quirks = &axxia_i2c_quirks;
659 idev->adapter.dev.parent = &pdev->dev;
660 idev->adapter.dev.of_node = pdev->dev.of_node;
662 platform_set_drvdata(pdev, idev);
664 ret = i2c_add_adapter(&idev->adapter);
666 goto error_disable_clk;
671 clk_disable_unprepare(idev->i2c_clk);
675 static int axxia_i2c_remove(struct platform_device *pdev)
677 struct axxia_i2c_dev *idev = platform_get_drvdata(pdev);
679 clk_disable_unprepare(idev->i2c_clk);
680 i2c_del_adapter(&idev->adapter);
685 /* Match table for of_platform binding */
686 static const struct of_device_id axxia_i2c_of_match[] = {
687 { .compatible = "lsi,api2c", },
691 MODULE_DEVICE_TABLE(of, axxia_i2c_of_match);
693 static struct platform_driver axxia_i2c_driver = {
694 .probe = axxia_i2c_probe,
695 .remove = axxia_i2c_remove,
698 .of_match_table = axxia_i2c_of_match,
702 module_platform_driver(axxia_i2c_driver);
704 MODULE_DESCRIPTION("Axxia I2C Bus driver");
705 MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>");
706 MODULE_LICENSE("GPL v2");