1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 * Copyright 2016 IBM Corporation
5 * Copyright 2017 Google, Inc.
15 #include <asm/arch/scu_ast2500.h>
16 #include <linux/err.h>
20 #define I2C_TIMEOUT_US 100000
21 #define I2C_SLEEP_STEP_US 20
23 #define HIGHSPEED_TTIMEOUT 3
29 /* This device's clock */
31 /* Device registers */
32 struct ast_i2c_regs *regs;
38 * Given desired divider ratio, return the value that needs to be set
39 * in Clock and AC Timing Control register
41 static u32 get_clk_reg_val(ulong divider_ratio)
44 ulong scl_low, scl_high, data;
46 for (div = 0; divider_ratio >= 16; div++) {
47 inc |= (divider_ratio & 1);
51 scl_low = (divider_ratio >> 1) - 1;
52 scl_high = divider_ratio - scl_low - 2;
53 data = I2CD_CACTC_BASE
54 | (scl_high << I2CD_TCKHIGH_SHIFT)
55 | (scl_low << I2CD_TCKLOW_SHIFT)
56 | (div << I2CD_BASE_DIV_SHIFT);
61 static void ast_i2c_clear_interrupts(struct udevice *dev)
63 struct ast_i2c_priv *priv = dev_get_priv(dev);
65 writel(~0, &priv->regs->isr);
68 static void ast_i2c_init_bus(struct udevice *dev)
70 struct ast_i2c_priv *priv = dev_get_priv(dev);
73 writel(0, &priv->regs->fcr);
74 /* Enable Master Mode. Assuming single-master */
77 | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
79 /* Enable Interrupts */
80 writel(I2CD_INTR_TX_ACK
83 | I2CD_INTR_BUS_RECOVER_DONE
84 | I2CD_INTR_NORMAL_STOP
85 | I2CD_INTR_ABNORMAL, &priv->regs->icr);
88 static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
90 struct ast_i2c_priv *priv = dev_get_priv(dev);
93 priv->regs = devfdt_get_addr_ptr(dev);
94 if (IS_ERR(priv->regs))
95 return PTR_ERR(priv->regs);
97 ret = clk_get_by_index(dev, 0, &priv->clk);
99 debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
107 static int ast_i2c_probe(struct udevice *dev)
109 struct ast2500_scu *scu;
111 debug("Enabling I2C%u\n", dev->seq);
114 * Get all I2C devices out of Reset.
115 * Only needs to be done once, but doing it for every
116 * device does not hurt.
120 clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
123 ast_i2c_init_bus(dev);
128 static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
130 struct ast_i2c_priv *priv = dev_get_priv(dev);
131 int timeout = I2C_TIMEOUT_US;
133 while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
134 udelay(I2C_SLEEP_STEP_US);
135 timeout -= I2C_SLEEP_STEP_US;
138 ast_i2c_clear_interrupts(dev);
145 static int ast_i2c_send_stop(struct udevice *dev)
147 struct ast_i2c_priv *priv = dev_get_priv(dev);
149 writel(I2CD_M_STOP_CMD, &priv->regs->csr);
151 return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
154 static int ast_i2c_wait_tx(struct udevice *dev)
156 struct ast_i2c_priv *priv = dev_get_priv(dev);
157 int timeout = I2C_TIMEOUT_US;
158 u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
159 u32 status = readl(&priv->regs->isr) & flag;
162 while (!status && timeout > 0) {
163 status = readl(&priv->regs->isr) & flag;
164 udelay(I2C_SLEEP_STEP_US);
165 timeout -= I2C_SLEEP_STEP_US;
168 if (status == I2CD_INTR_TX_NAK)
174 ast_i2c_clear_interrupts(dev);
179 static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
181 struct ast_i2c_priv *priv = dev_get_priv(dev);
183 /* Start and Send Device Address */
184 writel(devaddr, &priv->regs->trbbr);
185 writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
187 return ast_i2c_wait_tx(dev);
190 static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
191 size_t len, bool send_stop)
193 struct ast_i2c_priv *priv = dev_get_priv(dev);
194 u32 i2c_cmd = I2CD_M_RX_CMD;
197 ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
201 for (; len > 0; len--, buffer++) {
203 i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
204 writel(i2c_cmd, &priv->regs->csr);
205 ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
208 *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
209 >> I2CD_RX_DATA_SHIFT;
211 ast_i2c_clear_interrupts(dev);
214 return ast_i2c_send_stop(dev);
219 static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
220 *buffer, size_t len, bool send_stop)
222 struct ast_i2c_priv *priv = dev_get_priv(dev);
225 ret = ast_i2c_start_txn(dev, (chip_addr << 1));
229 for (; len > 0; len--, buffer++) {
230 writel(*buffer, &priv->regs->trbbr);
231 writel(I2CD_M_TX_CMD, &priv->regs->csr);
232 ret = ast_i2c_wait_tx(dev);
238 return ast_i2c_send_stop(dev);
243 static int ast_i2c_deblock(struct udevice *dev)
245 struct ast_i2c_priv *priv = dev_get_priv(dev);
246 struct ast_i2c_regs *regs = priv->regs;
247 u32 csr = readl(®s->csr);
248 bool sda_high = csr & I2CD_SDA_LINE_STS;
249 bool scl_high = csr & I2CD_SCL_LINE_STS;
252 if (sda_high && scl_high) {
253 /* Bus is idle, no deblocking needed. */
255 } else if (sda_high) {
256 /* Send stop command */
257 debug("Unterminated TXN in (%x), sending stop\n", csr);
258 ret = ast_i2c_send_stop(dev);
259 } else if (scl_high) {
260 /* Possibly stuck slave */
261 debug("Bus stuck (%x), attempting recovery\n", csr);
262 writel(I2CD_BUS_RECOVER_CMD, ®s->csr);
263 ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
265 /* Just try to reinit the device. */
266 ast_i2c_init_bus(dev);
272 static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
276 ret = ast_i2c_deblock(dev);
280 debug("i2c_xfer: %d messages\n", nmsgs);
281 for (; nmsgs > 0; nmsgs--, msg++) {
282 if (msg->flags & I2C_M_RD) {
283 debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
284 msg->addr, msg->len, msg->flags);
285 ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
286 msg->len, (nmsgs == 1));
288 debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
289 msg->addr, msg->len, msg->flags);
290 ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
291 msg->len, (nmsgs == 1));
294 debug("%s: error (%d)\n", __func__, ret);
302 static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
304 struct ast_i2c_priv *priv = dev_get_priv(dev);
305 struct ast_i2c_regs *regs = priv->regs;
306 ulong i2c_rate, divider;
308 debug("Setting speed for I2C%d to <%u>\n", dev->seq, speed);
310 debug("No valid speed specified\n");
314 i2c_rate = clk_get_rate(&priv->clk);
315 divider = i2c_rate / speed;
318 if (speed > I2C_SPEED_FAST_RATE) {
319 debug("Enable High Speed\n");
320 setbits_le32(®s->fcr, I2CD_M_HIGH_SPEED_EN
321 | I2CD_M_SDA_DRIVE_1T_EN
322 | I2CD_SDA_DRIVE_1T_EN);
323 writel(HIGHSPEED_TTIMEOUT, ®s->cactcr2);
325 debug("Enabling Normal Speed\n");
326 writel(I2CD_NO_TIMEOUT_CTRL, ®s->cactcr2);
329 writel(get_clk_reg_val(divider), ®s->cactcr1);
330 ast_i2c_clear_interrupts(dev);
335 static const struct dm_i2c_ops ast_i2c_ops = {
336 .xfer = ast_i2c_xfer,
337 .set_bus_speed = ast_i2c_set_speed,
338 .deblock = ast_i2c_deblock,
341 static const struct udevice_id ast_i2c_ids[] = {
342 { .compatible = "aspeed,ast2400-i2c-bus" },
343 { .compatible = "aspeed,ast2500-i2c-bus" },
347 U_BOOT_DRIVER(ast_i2c) = {
350 .of_match = ast_i2c_ids,
351 .probe = ast_i2c_probe,
352 .ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
353 .priv_auto_alloc_size = sizeof(struct ast_i2c_priv),