drivers/gpu/drm/tegra/sor.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/gpio.h>
  10 #include <linux/io.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/reset.h>
  16
  17 #include <soc/tegra/pmc.h>
  18
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_dp_helper.h>
  21 #include <drm/drm_panel.h>
  22 #include <drm/drm_scdc_helper.h>
  23
  24 #include "dc.h"
  25 #include "drm.h"
  26 #include "hda.h"
  27 #include "sor.h"
  28 #include "trace.h"
  29
  30 #define SOR_REKEY 0x38
  31
  32 struct tegra_sor_hdmi_settings {
  33         unsigned long frequency;
  34
  35         u8 vcocap;
  36         u8 filter;
  37         u8 ichpmp;
  38         u8 loadadj;
  39         u8 tmds_termadj;
  40         u8 tx_pu_value;
  41         u8 bg_temp_coef;
  42         u8 bg_vref_level;
  43         u8 avdd10_level;
  44         u8 avdd14_level;
  45         u8 sparepll;
  46
  47         u8 drive_current[4];
  48         u8 preemphasis[4];
  49 };
  50
  51 #if 1
  52 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  53         {
  54                 .frequency = 54000000,
  55                 .vcocap = 0x0,
  56                 .filter = 0x0,
  57                 .ichpmp = 0x1,
  58                 .loadadj = 0x3,
  59                 .tmds_termadj = 0x9,
  60                 .tx_pu_value = 0x10,
  61                 .bg_temp_coef = 0x3,
  62                 .bg_vref_level = 0x8,
  63                 .avdd10_level = 0x4,
  64                 .avdd14_level = 0x4,
  65                 .sparepll = 0x0,
  66                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  67                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  68         }, {
  69                 .frequency = 75000000,
  70                 .vcocap = 0x3,
  71                 .filter = 0x0,
  72                 .ichpmp = 0x1,
  73                 .loadadj = 0x3,
  74                 .tmds_termadj = 0x9,
  75                 .tx_pu_value = 0x40,
  76                 .bg_temp_coef = 0x3,
  77                 .bg_vref_level = 0x8,
  78                 .avdd10_level = 0x4,
  79                 .avdd14_level = 0x4,
  80                 .sparepll = 0x0,
  81                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  82                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  83         }, {
  84                 .frequency = 150000000,
  85                 .vcocap = 0x3,
  86                 .filter = 0x0,
  87                 .ichpmp = 0x1,
  88                 .loadadj = 0x3,
  89                 .tmds_termadj = 0x9,
  90                 .tx_pu_value = 0x66,
  91                 .bg_temp_coef = 0x3,
  92                 .bg_vref_level = 0x8,
  93                 .avdd10_level = 0x4,
  94                 .avdd14_level = 0x4,
  95                 .sparepll = 0x0,
  96                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  97                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  98         }, {
  99                 .frequency = 300000000,
 100                 .vcocap = 0x3,
 101                 .filter = 0x0,
 102                 .ichpmp = 0x1,
 103                 .loadadj = 0x3,
 104                 .tmds_termadj = 0x9,
 105                 .tx_pu_value = 0x66,
 106                 .bg_temp_coef = 0x3,
 107                 .bg_vref_level = 0xa,
 108                 .avdd10_level = 0x4,
 109                 .avdd14_level = 0x4,
 110                 .sparepll = 0x0,
 111                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 112                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 113         }, {
 114                 .frequency = 600000000,
 115                 .vcocap = 0x3,
 116                 .filter = 0x0,
 117                 .ichpmp = 0x1,
 118                 .loadadj = 0x3,
 119                 .tmds_termadj = 0x9,
 120                 .tx_pu_value = 0x66,
 121                 .bg_temp_coef = 0x3,
 122                 .bg_vref_level = 0x8,
 123                 .avdd10_level = 0x4,
 124                 .avdd14_level = 0x4,
 125                 .sparepll = 0x0,
 126                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 127                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 128         },
 129 };
 130 #else
 131 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 132         {
 133                 .frequency = 75000000,
 134                 .vcocap = 0x3,
 135                 .filter = 0x0,
 136                 .ichpmp = 0x1,
 137                 .loadadj = 0x3,
 138                 .tmds_termadj = 0x9,
 139                 .tx_pu_value = 0x40,
 140                 .bg_temp_coef = 0x3,
 141                 .bg_vref_level = 0x8,
 142                 .avdd10_level = 0x4,
 143                 .avdd14_level = 0x4,
 144                 .sparepll = 0x0,
 145                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 146                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 147         }, {
 148                 .frequency = 150000000,
 149                 .vcocap = 0x3,
 150                 .filter = 0x0,
 151                 .ichpmp = 0x1,
 152                 .loadadj = 0x3,
 153                 .tmds_termadj = 0x9,
 154                 .tx_pu_value = 0x66,
 155                 .bg_temp_coef = 0x3,
 156                 .bg_vref_level = 0x8,
 157                 .avdd10_level = 0x4,
 158                 .avdd14_level = 0x4,
 159                 .sparepll = 0x0,
 160                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 161                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 162         }, {
 163                 .frequency = 300000000,
 164                 .vcocap = 0x3,
 165                 .filter = 0x0,
 166                 .ichpmp = 0x6,
 167                 .loadadj = 0x3,
 168                 .tmds_termadj = 0x9,
 169                 .tx_pu_value = 0x66,
 170                 .bg_temp_coef = 0x3,
 171                 .bg_vref_level = 0xf,
 172                 .avdd10_level = 0x4,
 173                 .avdd14_level = 0x4,
 174                 .sparepll = 0x0,
 175                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 176                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 177         }, {
 178                 .frequency = 600000000,
 179                 .vcocap = 0x3,
 180                 .filter = 0x0,
 181                 .ichpmp = 0xa,
 182                 .loadadj = 0x3,
 183                 .tmds_termadj = 0xb,
 184                 .tx_pu_value = 0x66,
 185                 .bg_temp_coef = 0x3,
 186                 .bg_vref_level = 0xe,
 187                 .avdd10_level = 0x4,
 188                 .avdd14_level = 0x4,
 189                 .sparepll = 0x0,
 190                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 191                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 192         },
 193 };
 194 #endif
 195
 196 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 197         {
 198                 .frequency = 54000000,
 199                 .vcocap = 0,
 200                 .filter = 5,
 201                 .ichpmp = 5,
 202                 .loadadj = 3,
 203                 .tmds_termadj = 0xf,
 204                 .tx_pu_value = 0,
 205                 .bg_temp_coef = 3,
 206                 .bg_vref_level = 8,
 207                 .avdd10_level = 4,
 208                 .avdd14_level = 4,
 209                 .sparepll = 0x54,
 210                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 211                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 212         }, {
 213                 .frequency = 75000000,
 214                 .vcocap = 1,
 215                 .filter = 5,
 216                 .ichpmp = 5,
 217                 .loadadj = 3,
 218                 .tmds_termadj = 0xf,
 219                 .tx_pu_value = 0,
 220                 .bg_temp_coef = 3,
 221                 .bg_vref_level = 8,
 222                 .avdd10_level = 4,
 223                 .avdd14_level = 4,
 224                 .sparepll = 0x44,
 225                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 226                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 227         }, {
 228                 .frequency = 150000000,
 229                 .vcocap = 3,
 230                 .filter = 5,
 231                 .ichpmp = 5,
 232                 .loadadj = 3,
 233                 .tmds_termadj = 15,
 234                 .tx_pu_value = 0x66 /* 0 */,
 235                 .bg_temp_coef = 3,
 236                 .bg_vref_level = 8,
 237                 .avdd10_level = 4,
 238                 .avdd14_level = 4,
 239                 .sparepll = 0x00, /* 0x34 */
 240                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 241                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 242         }, {
 243                 .frequency = 300000000,
 244                 .vcocap = 3,
 245                 .filter = 5,
 246                 .ichpmp = 5,
 247                 .loadadj = 3,
 248                 .tmds_termadj = 15,
 249                 .tx_pu_value = 64,
 250                 .bg_temp_coef = 3,
 251                 .bg_vref_level = 8,
 252                 .avdd10_level = 4,
 253                 .avdd14_level = 4,
 254                 .sparepll = 0x34,
 255                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 256                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 257         }, {
 258                 .frequency = 600000000,
 259                 .vcocap = 3,
 260                 .filter = 5,
 261                 .ichpmp = 5,
 262                 .loadadj = 3,
 263                 .tmds_termadj = 12,
 264                 .tx_pu_value = 96,
 265                 .bg_temp_coef = 3,
 266                 .bg_vref_level = 8,
 267                 .avdd10_level = 4,
 268                 .avdd14_level = 4,
 269                 .sparepll = 0x34,
 270                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 271                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 272         }
 273 };
 274
 275 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
 276         {
 277                 .frequency = 54000000,
 278                 .vcocap = 0,
 279                 .filter = 5,
 280                 .ichpmp = 5,
 281                 .loadadj = 3,
 282                 .tmds_termadj = 0xf,
 283                 .tx_pu_value = 0,
 284                 .bg_temp_coef = 3,
 285                 .bg_vref_level = 8,
 286                 .avdd10_level = 4,
 287                 .avdd14_level = 4,
 288                 .sparepll = 0x54,
 289                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 290                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 291         }, {
 292                 .frequency = 75000000,
 293                 .vcocap = 1,
 294                 .filter = 5,
 295                 .ichpmp = 5,
 296                 .loadadj = 3,
 297                 .tmds_termadj = 0xf,
 298                 .tx_pu_value = 0,
 299                 .bg_temp_coef = 3,
 300                 .bg_vref_level = 8,
 301                 .avdd10_level = 4,
 302                 .avdd14_level = 4,
 303                 .sparepll = 0x44,
 304                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 305                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 306         }, {
 307                 .frequency = 150000000,
 308                 .vcocap = 3,
 309                 .filter = 5,
 310                 .ichpmp = 5,
 311                 .loadadj = 3,
 312                 .tmds_termadj = 15,
 313                 .tx_pu_value = 0x66 /* 0 */,
 314                 .bg_temp_coef = 3,
 315                 .bg_vref_level = 8,
 316                 .avdd10_level = 4,
 317                 .avdd14_level = 4,
 318                 .sparepll = 0x00, /* 0x34 */
 319                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 320                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 321         }, {
 322                 .frequency = 300000000,
 323                 .vcocap = 3,
 324                 .filter = 5,
 325                 .ichpmp = 5,
 326                 .loadadj = 3,
 327                 .tmds_termadj = 15,
 328                 .tx_pu_value = 64,
 329                 .bg_temp_coef = 3,
 330                 .bg_vref_level = 8,
 331                 .avdd10_level = 4,
 332                 .avdd14_level = 4,
 333                 .sparepll = 0x34,
 334                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 335                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 336         }, {
 337                 .frequency = 600000000,
 338                 .vcocap = 3,
 339                 .filter = 5,
 340                 .ichpmp = 5,
 341                 .loadadj = 3,
 342                 .tmds_termadj = 12,
 343                 .tx_pu_value = 96,
 344                 .bg_temp_coef = 3,
 345                 .bg_vref_level = 8,
 346                 .avdd10_level = 4,
 347                 .avdd14_level = 4,
 348                 .sparepll = 0x34,
 349                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 350                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 351         }
 352 };
 353
 354 struct tegra_sor_regs {
 355         unsigned int head_state0;
 356         unsigned int head_state1;
 357         unsigned int head_state2;
 358         unsigned int head_state3;
 359         unsigned int head_state4;
 360         unsigned int head_state5;
 361         unsigned int pll0;
 362         unsigned int pll1;
 363         unsigned int pll2;
 364         unsigned int pll3;
 365         unsigned int dp_padctl0;
 366         unsigned int dp_padctl2;
 367 };
 368
 369 struct tegra_sor_soc {
 370         bool supports_edp;
 371         bool supports_lvds;
 372         bool supports_hdmi;
 373         bool supports_dp;
 374
 375         const struct tegra_sor_regs *regs;
 376         bool has_nvdisplay;
 377
 378         const struct tegra_sor_hdmi_settings *settings;
 379         unsigned int num_settings;
 380
 381         const u8 *xbar_cfg;
 382 };
 383
 384 struct tegra_sor;
 385
 386 struct tegra_sor_ops {
 387         const char *name;
 388         int (*probe)(struct tegra_sor *sor);
 389         int (*remove)(struct tegra_sor *sor);
 390 };
 391
 392 struct tegra_sor {
 393         struct host1x_client client;
 394         struct tegra_output output;
 395         struct device *dev;
 396
 397         const struct tegra_sor_soc *soc;
 398         void __iomem *regs;
 399         unsigned int index;
 400         unsigned int irq;
 401
 402         struct reset_control *rst;
 403         struct clk *clk_parent;
 404         struct clk *clk_safe;
 405         struct clk *clk_out;
 406         struct clk *clk_pad;
 407         struct clk *clk_dp;
 408         struct clk *clk;
 409
 410         u8 xbar_cfg[5];
 411
 412         struct drm_dp_aux *aux;
 413
 414         struct drm_info_list *debugfs_files;
 415
 416         const struct tegra_sor_ops *ops;
 417         enum tegra_io_pad pad;
 418
 419         /* for HDMI 2.0 */
 420         struct tegra_sor_hdmi_settings *settings;
 421         unsigned int num_settings;
 422
 423         struct regulator *avdd_io_supply;
 424         struct regulator *vdd_pll_supply;
 425         struct regulator *hdmi_supply;
 426
 427         struct delayed_work scdc;
 428         bool scdc_enabled;
 429
 430         struct tegra_hda_format format;
 431 };
 432
 433 struct tegra_sor_state {
 434         struct drm_connector_state base;
 435
 436         unsigned int link_speed;
 437         unsigned long pclk;
 438         unsigned int bpc;
 439 };
 440
 441 static inline struct tegra_sor_state *
 442 to_sor_state(struct drm_connector_state *state)
 443 {
 444         return container_of(state, struct tegra_sor_state, base);
 445 }
 446
 447 struct tegra_sor_config {
 448         u32 bits_per_pixel;
 449
 450         u32 active_polarity;
 451         u32 active_count;
 452         u32 tu_size;
 453         u32 active_frac;
 454         u32 watermark;
 455
 456         u32 hblank_symbols;
 457         u32 vblank_symbols;
 458 };
 459
 460 static inline struct tegra_sor *
 461 host1x_client_to_sor(struct host1x_client *client)
 462 {
 463         return container_of(client, struct tegra_sor, client);
 464 }
 465
 466 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 467 {
 468         return container_of(output, struct tegra_sor, output);
 469 }
 470
 471 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 472 {
 473         u32 value = readl(sor->regs + (offset << 2));
 474
 475         trace_sor_readl(sor->dev, offset, value);
 476
 477         return value;
 478 }
 479
 480 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 481                                     unsigned int offset)
 482 {
 483         trace_sor_writel(sor->dev, offset, value);
 484         writel(value, sor->regs + (offset << 2));
 485 }
 486
 487 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 488 {
 489         int err;
 490
 491         clk_disable_unprepare(sor->clk);
 492
 493         err = clk_set_parent(sor->clk_out, parent);
 494         if (err < 0)
 495                 return err;
 496
 497         err = clk_prepare_enable(sor->clk);
 498         if (err < 0)
 499                 return err;
 500
 501         return 0;
 502 }
 503
 504 struct tegra_clk_sor_pad {
 505         struct clk_hw hw;
 506         struct tegra_sor *sor;
 507 };
 508
 509 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 510 {
 511         return container_of(hw, struct tegra_clk_sor_pad, hw);
 512 }
 513
 514 static const char * const tegra_clk_sor_pad_parents[] = {
 515         "pll_d2_out0", "pll_dp"
 516 };
 517
 518 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 519 {
 520         struct tegra_clk_sor_pad *pad = to_pad(hw);
 521         struct tegra_sor *sor = pad->sor;
 522         u32 value;
 523
 524         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 525         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 526
 527         switch (index) {
 528         case 0:
 529                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 530                 break;
 531
 532         case 1:
 533                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 534                 break;
 535         }
 536
 537         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 538
 539         return 0;
 540 }
 541
 542 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 543 {
 544         struct tegra_clk_sor_pad *pad = to_pad(hw);
 545         struct tegra_sor *sor = pad->sor;
 546         u8 parent = U8_MAX;
 547         u32 value;
 548
 549         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 550
 551         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 552         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 553         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 554                 parent = 0;
 555                 break;
 556
 557         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 558         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 559                 parent = 1;
 560                 break;
 561         }
 562
 563         return parent;
 564 }
 565
 566 static const struct clk_ops tegra_clk_sor_pad_ops = {
 567         .set_parent = tegra_clk_sor_pad_set_parent,
 568         .get_parent = tegra_clk_sor_pad_get_parent,
 569 };
 570
 571 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 572                                               const char *name)
 573 {
 574         struct tegra_clk_sor_pad *pad;
 575         struct clk_init_data init;
 576         struct clk *clk;
 577
 578         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 579         if (!pad)
 580                 return ERR_PTR(-ENOMEM);
 581
 582         pad->sor = sor;
 583
 584         init.name = name;
 585         init.flags = 0;
 586         init.parent_names = tegra_clk_sor_pad_parents;
 587         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
 588         init.ops = &tegra_clk_sor_pad_ops;
 589
 590         pad->hw.init = &init;
 591
 592         clk = devm_clk_register(sor->dev, &pad->hw);
 593
 594         return clk;
 595 }
 596
 597 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
 598                                    struct drm_dp_link *link)
 599 {
 600         unsigned int i;
 601         u8 pattern;
 602         u32 value;
 603         int err;
 604
 605         /* setup lane parameters */
 606         value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
 607                 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
 608                 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
 609                 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
 610         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
 611
 612         value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
 613                 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
 614                 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
 615                 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
 616         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
 617
 618         value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
 619                 SOR_LANE_POSTCURSOR_LANE2(0x00) |
 620                 SOR_LANE_POSTCURSOR_LANE1(0x00) |
 621                 SOR_LANE_POSTCURSOR_LANE0(0x00);
 622         tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
 623
 624         /* disable LVDS mode */
 625         tegra_sor_writel(sor, 0, SOR_LVDS);
 626
 627         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 628         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 629         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 630         value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
 631         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 632
 633         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 634         value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 635                  SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
 636         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 637
 638         usleep_range(10, 100);
 639
 640         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 641         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 642                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 643         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 644
 645         err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
 646         if (err < 0)
 647                 return err;
 648
 649         for (i = 0, value = 0; i < link->num_lanes; i++) {
 650                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 651                                      SOR_DP_TPG_SCRAMBLER_NONE |
 652                                      SOR_DP_TPG_PATTERN_TRAIN1;
 653                 value = (value << 8) | lane;
 654         }
 655
 656         tegra_sor_writel(sor, value, SOR_DP_TPG);
 657
 658         pattern = DP_TRAINING_PATTERN_1;
 659
 660         err = drm_dp_aux_train(sor->aux, link, pattern);
 661         if (err < 0)
 662                 return err;
 663
 664         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 665         value |= SOR_DP_SPARE_SEQ_ENABLE;
 666         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 667         value |= SOR_DP_SPARE_MACRO_SOR_CLK;
 668         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 669
 670         for (i = 0, value = 0; i < link->num_lanes; i++) {
 671                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 672                                      SOR_DP_TPG_SCRAMBLER_NONE |
 673                                      SOR_DP_TPG_PATTERN_TRAIN2;
 674                 value = (value << 8) | lane;
 675         }
 676
 677         tegra_sor_writel(sor, value, SOR_DP_TPG);
 678
 679         pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
 680
 681         err = drm_dp_aux_train(sor->aux, link, pattern);
 682         if (err < 0)
 683                 return err;
 684
 685         for (i = 0, value = 0; i < link->num_lanes; i++) {
 686                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 687                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 688                                      SOR_DP_TPG_PATTERN_NONE;
 689                 value = (value << 8) | lane;
 690         }
 691
 692         tegra_sor_writel(sor, value, SOR_DP_TPG);
 693
 694         pattern = DP_TRAINING_PATTERN_DISABLE;
 695
 696         err = drm_dp_aux_train(sor->aux, link, pattern);
 697         if (err < 0)
 698                 return err;
 699
 700         return 0;
 701 }
 702
 703 static void tegra_sor_super_update(struct tegra_sor *sor)
 704 {
 705         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 706         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 707         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 708 }
 709
 710 static void tegra_sor_update(struct tegra_sor *sor)
 711 {
 712         tegra_sor_writel(sor, 0, SOR_STATE0);
 713         tegra_sor_writel(sor, 1, SOR_STATE0);
 714         tegra_sor_writel(sor, 0, SOR_STATE0);
 715 }
 716
 717 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 718 {
 719         u32 value;
 720
 721         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 722         value &= ~SOR_PWM_DIV_MASK;
 723         value |= 0x400; /* period */
 724         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 725
 726         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 727         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 728         value |= 0x400; /* duty cycle */
 729         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 730         value |= SOR_PWM_CTL_TRIGGER;
 731         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 732
 733         timeout = jiffies + msecs_to_jiffies(timeout);
 734
 735         while (time_before(jiffies, timeout)) {
 736                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 737                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 738                         return 0;
 739
 740                 usleep_range(25, 100);
 741         }
 742
 743         return -ETIMEDOUT;
 744 }
 745
 746 static int tegra_sor_attach(struct tegra_sor *sor)
 747 {
 748         unsigned long value, timeout;
 749
 750         /* wake up in normal mode */
 751         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 752         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 753         value |= SOR_SUPER_STATE_MODE_NORMAL;
 754         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 755         tegra_sor_super_update(sor);
 756
 757         /* attach */
 758         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 759         value |= SOR_SUPER_STATE_ATTACHED;
 760         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 761         tegra_sor_super_update(sor);
 762
 763         timeout = jiffies + msecs_to_jiffies(250);
 764
 765         while (time_before(jiffies, timeout)) {
 766                 value = tegra_sor_readl(sor, SOR_TEST);
 767                 if ((value & SOR_TEST_ATTACHED) != 0)
 768                         return 0;
 769
 770                 usleep_range(25, 100);
 771         }
 772
 773         return -ETIMEDOUT;
 774 }
 775
 776 static int tegra_sor_wakeup(struct tegra_sor *sor)
 777 {
 778         unsigned long value, timeout;
 779
 780         timeout = jiffies + msecs_to_jiffies(250);
 781
 782         /* wait for head to wake up */
 783         while (time_before(jiffies, timeout)) {
 784                 value = tegra_sor_readl(sor, SOR_TEST);
 785                 value &= SOR_TEST_HEAD_MODE_MASK;
 786
 787                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
 788                         return 0;
 789
 790                 usleep_range(25, 100);
 791         }
 792
 793         return -ETIMEDOUT;
 794 }
 795
 796 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
 797 {
 798         u32 value;
 799
 800         value = tegra_sor_readl(sor, SOR_PWR);
 801         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
 802         tegra_sor_writel(sor, value, SOR_PWR);
 803
 804         timeout = jiffies + msecs_to_jiffies(timeout);
 805
 806         while (time_before(jiffies, timeout)) {
 807                 value = tegra_sor_readl(sor, SOR_PWR);
 808                 if ((value & SOR_PWR_TRIGGER) == 0)
 809                         return 0;
 810
 811                 usleep_range(25, 100);
 812         }
 813
 814         return -ETIMEDOUT;
 815 }
 816
 817 struct tegra_sor_params {
 818         /* number of link clocks per line */
 819         unsigned int num_clocks;
 820         /* ratio between input and output */
 821         u64 ratio;
 822         /* precision factor */
 823         u64 precision;
 824
 825         unsigned int active_polarity;
 826         unsigned int active_count;
 827         unsigned int active_frac;
 828         unsigned int tu_size;
 829         unsigned int error;
 830 };
 831
 832 static int tegra_sor_compute_params(struct tegra_sor *sor,
 833                                     struct tegra_sor_params *params,
 834                                     unsigned int tu_size)
 835 {
 836         u64 active_sym, active_count, frac, approx;
 837         u32 active_polarity, active_frac = 0;
 838         const u64 f = params->precision;
 839         s64 error;
 840
 841         active_sym = params->ratio * tu_size;
 842         active_count = div_u64(active_sym, f) * f;
 843         frac = active_sym - active_count;
 844
 845         /* fraction < 0.5 */
 846         if (frac >= (f / 2)) {
 847                 active_polarity = 1;
 848                 frac = f - frac;
 849         } else {
 850                 active_polarity = 0;
 851         }
 852
 853         if (frac != 0) {
 854                 frac = div_u64(f * f,  frac); /* 1/fraction */
 855                 if (frac <= (15 * f)) {
 856                         active_frac = div_u64(frac, f);
 857
 858                         /* round up */
 859                         if (active_polarity)
 860                                 active_frac++;
 861                 } else {
 862                         active_frac = active_polarity ? 1 : 15;
 863                 }
 864         }
 865
 866         if (active_frac == 1)
 867                 active_polarity = 0;
 868
 869         if (active_polarity == 1) {
 870                 if (active_frac) {
 871                         approx = active_count + (active_frac * (f - 1)) * f;
 872                         approx = div_u64(approx, active_frac * f);
 873                 } else {
 874                         approx = active_count + f;
 875                 }
 876         } else {
 877                 if (active_frac)
 878                         approx = active_count + div_u64(f, active_frac);
 879                 else
 880                         approx = active_count;
 881         }
 882
 883         error = div_s64(active_sym - approx, tu_size);
 884         error *= params->num_clocks;
 885
 886         if (error <= 0 && abs(error) < params->error) {
 887                 params->active_count = div_u64(active_count, f);
 888                 params->active_polarity = active_polarity;
 889                 params->active_frac = active_frac;
 890                 params->error = abs(error);
 891                 params->tu_size = tu_size;
 892
 893                 if (error == 0)
 894                         return true;
 895         }
 896
 897         return false;
 898 }
 899
 900 static int tegra_sor_compute_config(struct tegra_sor *sor,
 901                                     const struct drm_display_mode *mode,
 902                                     struct tegra_sor_config *config,
 903                                     struct drm_dp_link *link)
 904 {
 905         const u64 f = 100000, link_rate = link->rate * 1000;
 906         const u64 pclk = mode->clock * 1000;
 907         u64 input, output, watermark, num;
 908         struct tegra_sor_params params;
 909         u32 num_syms_per_line;
 910         unsigned int i;
 911
 912         if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
 913                 return -EINVAL;
 914
 915         output = link_rate * 8 * link->num_lanes;
 916         input = pclk * config->bits_per_pixel;
 917
 918         if (input >= output)
 919                 return -ERANGE;
 920
 921         memset(&params, 0, sizeof(params));
 922         params.ratio = div64_u64(input * f, output);
 923         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
 924         params.precision = f;
 925         params.error = 64 * f;
 926         params.tu_size = 64;
 927
 928         for (i = params.tu_size; i >= 32; i--)
 929                 if (tegra_sor_compute_params(sor, &params, i))
 930                         break;
 931
 932         if (params.active_frac == 0) {
 933                 config->active_polarity = 0;
 934                 config->active_count = params.active_count;
 935
 936                 if (!params.active_polarity)
 937                         config->active_count--;
 938
 939                 config->tu_size = params.tu_size;
 940                 config->active_frac = 1;
 941         } else {
 942                 config->active_polarity = params.active_polarity;
 943                 config->active_count = params.active_count;
 944                 config->active_frac = params.active_frac;
 945                 config->tu_size = params.tu_size;
 946         }
 947
 948         dev_dbg(sor->dev,
 949                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
 950                 config->active_polarity, config->active_count,
 951                 config->tu_size, config->active_frac);
 952
 953         watermark = params.ratio * config->tu_size * (f - params.ratio);
 954         watermark = div_u64(watermark, f);
 955
 956         watermark = div_u64(watermark + params.error, f);
 957         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
 958         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
 959                             (link->num_lanes * 8);
 960
 961         if (config->watermark > 30) {
 962                 config->watermark = 30;
 963                 dev_err(sor->dev,
 964                         "unable to compute TU size, forcing watermark to %u\n",
 965                         config->watermark);
 966         } else if (config->watermark > num_syms_per_line) {
 967                 config->watermark = num_syms_per_line;
 968                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
 969                         config->watermark);
 970         }
 971
 972         /* compute the number of symbols per horizontal blanking interval */
 973         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
 974         config->hblank_symbols = div_u64(num, pclk);
 975
 976         if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 977                 config->hblank_symbols -= 3;
 978
 979         config->hblank_symbols -= 12 / link->num_lanes;
 980
 981         /* compute the number of symbols per vertical blanking interval */
 982         num = (mode->hdisplay - 25) * link_rate;
 983         config->vblank_symbols = div_u64(num, pclk);
 984         config->vblank_symbols -= 36 / link->num_lanes + 4;
 985
 986         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
 987                 config->vblank_symbols);
 988
 989         return 0;
 990 }
 991
 992 static void tegra_sor_apply_config(struct tegra_sor *sor,
 993                                    const struct tegra_sor_config *config)
 994 {
 995         u32 value;
 996
 997         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 998         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
 999         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1000         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1001
1002         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1003         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1004         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1005
1006         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1007         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1008
1009         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1010         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1011
1012         if (config->active_polarity)
1013                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1014         else
1015                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1016
1017         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1018         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1019         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1020
1021         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1022         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1023         value |= config->hblank_symbols & 0xffff;
1024         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1025
1026         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1027         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1028         value |= config->vblank_symbols & 0xffff;
1029         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1030 }
1031
1032 static void tegra_sor_mode_set(struct tegra_sor *sor,
1033                                const struct drm_display_mode *mode,
1034                                struct tegra_sor_state *state)
1035 {
1036         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1037         unsigned int vbe, vse, hbe, hse, vbs, hbs;
1038         u32 value;
1039
1040         value = tegra_sor_readl(sor, SOR_STATE1);
1041         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1042         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1043         value &= ~SOR_STATE_ASY_OWNER_MASK;
1044
1045         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1046                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
1047
1048         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1049                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1050
1051         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1052                 value |= SOR_STATE_ASY_HSYNCPOL;
1053
1054         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1055                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1056
1057         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1058                 value |= SOR_STATE_ASY_VSYNCPOL;
1059
1060         switch (state->bpc) {
1061         case 16:
1062                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1063                 break;
1064
1065         case 12:
1066                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1067                 break;
1068
1069         case 10:
1070                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1071                 break;
1072
1073         case 8:
1074                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1075                 break;
1076
1077         case 6:
1078                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1079                 break;
1080
1081         default:
1082                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1083                 break;
1084         }
1085
1086         tegra_sor_writel(sor, value, SOR_STATE1);
1087
1088         /*
1089          * TODO: The video timing programming below doesn't seem to match the
1090          * register definitions.
1091          */
1092
1093         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1094         tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1095
1096         /* sync end = sync width - 1 */
1097         vse = mode->vsync_end - mode->vsync_start - 1;
1098         hse = mode->hsync_end - mode->hsync_start - 1;
1099
1100         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1101         tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1102
1103         /* blank end = sync end + back porch */
1104         vbe = vse + (mode->vtotal - mode->vsync_end);
1105         hbe = hse + (mode->htotal - mode->hsync_end);
1106
1107         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1108         tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1109
1110         /* blank start = blank end + active */
1111         vbs = vbe + mode->vdisplay;
1112         hbs = hbe + mode->hdisplay;
1113
1114         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1115         tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1116
1117         /* XXX interlacing support */
1118         tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1119 }
1120
1121 static int tegra_sor_detach(struct tegra_sor *sor)
1122 {
1123         unsigned long value, timeout;
1124
1125         /* switch to safe mode */
1126         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1127         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1128         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1129         tegra_sor_super_update(sor);
1130
1131         timeout = jiffies + msecs_to_jiffies(250);
1132
1133         while (time_before(jiffies, timeout)) {
1134                 value = tegra_sor_readl(sor, SOR_PWR);
1135                 if (value & SOR_PWR_MODE_SAFE)
1136                         break;
1137         }
1138
1139         if ((value & SOR_PWR_MODE_SAFE) == 0)
1140                 return -ETIMEDOUT;
1141
1142         /* go to sleep */
1143         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1144         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1145         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1146         tegra_sor_super_update(sor);
1147
1148         /* detach */
1149         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1150         value &= ~SOR_SUPER_STATE_ATTACHED;
1151         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1152         tegra_sor_super_update(sor);
1153
1154         timeout = jiffies + msecs_to_jiffies(250);
1155
1156         while (time_before(jiffies, timeout)) {
1157                 value = tegra_sor_readl(sor, SOR_TEST);
1158                 if ((value & SOR_TEST_ATTACHED) == 0)
1159                         break;
1160
1161                 usleep_range(25, 100);
1162         }
1163
1164         if ((value & SOR_TEST_ATTACHED) != 0)
1165                 return -ETIMEDOUT;
1166
1167         return 0;
1168 }
1169
1170 static int tegra_sor_power_down(struct tegra_sor *sor)
1171 {
1172         unsigned long value, timeout;
1173         int err;
1174
1175         value = tegra_sor_readl(sor, SOR_PWR);
1176         value &= ~SOR_PWR_NORMAL_STATE_PU;
1177         value |= SOR_PWR_TRIGGER;
1178         tegra_sor_writel(sor, value, SOR_PWR);
1179
1180         timeout = jiffies + msecs_to_jiffies(250);
1181
1182         while (time_before(jiffies, timeout)) {
1183                 value = tegra_sor_readl(sor, SOR_PWR);
1184                 if ((value & SOR_PWR_TRIGGER) == 0)
1185                         return 0;
1186
1187                 usleep_range(25, 100);
1188         }
1189
1190         if ((value & SOR_PWR_TRIGGER) != 0)
1191                 return -ETIMEDOUT;
1192
1193         /* switch to safe parent clock */
1194         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1195         if (err < 0) {
1196                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1197                 return err;
1198         }
1199
1200         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1201         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1202                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1203         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1204
1205         /* stop lane sequencer */
1206         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1207                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1208         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1209
1210         timeout = jiffies + msecs_to_jiffies(250);
1211
1212         while (time_before(jiffies, timeout)) {
1213                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1214                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1215                         break;
1216
1217                 usleep_range(25, 100);
1218         }
1219
1220         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1221                 return -ETIMEDOUT;
1222
1223         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1224         value |= SOR_PLL2_PORT_POWERDOWN;
1225         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1226
1227         usleep_range(20, 100);
1228
1229         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1230         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1231         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1232
1233         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1234         value |= SOR_PLL2_SEQ_PLLCAPPD;
1235         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1236         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1237
1238         usleep_range(20, 100);
1239
1240         return 0;
1241 }
1242
1243 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1244 {
1245         u32 value;
1246
1247         timeout = jiffies + msecs_to_jiffies(timeout);
1248
1249         while (time_before(jiffies, timeout)) {
1250                 value = tegra_sor_readl(sor, SOR_CRCA);
1251                 if (value & SOR_CRCA_VALID)
1252                         return 0;
1253
1254                 usleep_range(100, 200);
1255         }
1256
1257         return -ETIMEDOUT;
1258 }
1259
1260 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1261 {
1262         struct drm_info_node *node = s->private;
1263         struct tegra_sor *sor = node->info_ent->data;
1264         struct drm_crtc *crtc = sor->output.encoder.crtc;
1265         struct drm_device *drm = node->minor->dev;
1266         int err = 0;
1267         u32 value;
1268
1269         drm_modeset_lock_all(drm);
1270
1271         if (!crtc || !crtc->state->active) {
1272                 err = -EBUSY;
1273                 goto unlock;
1274         }
1275
1276         value = tegra_sor_readl(sor, SOR_STATE1);
1277         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1278         tegra_sor_writel(sor, value, SOR_STATE1);
1279
1280         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1281         value |= SOR_CRC_CNTRL_ENABLE;
1282         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1283
1284         value = tegra_sor_readl(sor, SOR_TEST);
1285         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1286         tegra_sor_writel(sor, value, SOR_TEST);
1287
1288         err = tegra_sor_crc_wait(sor, 100);
1289         if (err < 0)
1290                 goto unlock;
1291
1292         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1293         value = tegra_sor_readl(sor, SOR_CRCB);
1294
1295         seq_printf(s, "%08x\n", value);
1296
1297 unlock:
1298         drm_modeset_unlock_all(drm);
1299         return err;
1300 }
1301
1302 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1303
1304 static const struct debugfs_reg32 tegra_sor_regs[] = {
1305         DEBUGFS_REG32(SOR_CTXSW),
1306         DEBUGFS_REG32(SOR_SUPER_STATE0),
1307         DEBUGFS_REG32(SOR_SUPER_STATE1),
1308         DEBUGFS_REG32(SOR_STATE0),
1309         DEBUGFS_REG32(SOR_STATE1),
1310         DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1311         DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1312         DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1313         DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1314         DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1315         DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1316         DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1317         DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1318         DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1319         DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1320         DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1321         DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1322         DEBUGFS_REG32(SOR_CRC_CNTRL),
1323         DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1324         DEBUGFS_REG32(SOR_CLK_CNTRL),
1325         DEBUGFS_REG32(SOR_CAP),
1326         DEBUGFS_REG32(SOR_PWR),
1327         DEBUGFS_REG32(SOR_TEST),
1328         DEBUGFS_REG32(SOR_PLL0),
1329         DEBUGFS_REG32(SOR_PLL1),
1330         DEBUGFS_REG32(SOR_PLL2),
1331         DEBUGFS_REG32(SOR_PLL3),
1332         DEBUGFS_REG32(SOR_CSTM),
1333         DEBUGFS_REG32(SOR_LVDS),
1334         DEBUGFS_REG32(SOR_CRCA),
1335         DEBUGFS_REG32(SOR_CRCB),
1336         DEBUGFS_REG32(SOR_BLANK),
1337         DEBUGFS_REG32(SOR_SEQ_CTL),
1338         DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1339         DEBUGFS_REG32(SOR_SEQ_INST(0)),
1340         DEBUGFS_REG32(SOR_SEQ_INST(1)),
1341         DEBUGFS_REG32(SOR_SEQ_INST(2)),
1342         DEBUGFS_REG32(SOR_SEQ_INST(3)),
1343         DEBUGFS_REG32(SOR_SEQ_INST(4)),
1344         DEBUGFS_REG32(SOR_SEQ_INST(5)),
1345         DEBUGFS_REG32(SOR_SEQ_INST(6)),
1346         DEBUGFS_REG32(SOR_SEQ_INST(7)),
1347         DEBUGFS_REG32(SOR_SEQ_INST(8)),
1348         DEBUGFS_REG32(SOR_SEQ_INST(9)),
1349         DEBUGFS_REG32(SOR_SEQ_INST(10)),
1350         DEBUGFS_REG32(SOR_SEQ_INST(11)),
1351         DEBUGFS_REG32(SOR_SEQ_INST(12)),
1352         DEBUGFS_REG32(SOR_SEQ_INST(13)),
1353         DEBUGFS_REG32(SOR_SEQ_INST(14)),
1354         DEBUGFS_REG32(SOR_SEQ_INST(15)),
1355         DEBUGFS_REG32(SOR_PWM_DIV),
1356         DEBUGFS_REG32(SOR_PWM_CTL),
1357         DEBUGFS_REG32(SOR_VCRC_A0),
1358         DEBUGFS_REG32(SOR_VCRC_A1),
1359         DEBUGFS_REG32(SOR_VCRC_B0),
1360         DEBUGFS_REG32(SOR_VCRC_B1),
1361         DEBUGFS_REG32(SOR_CCRC_A0),
1362         DEBUGFS_REG32(SOR_CCRC_A1),
1363         DEBUGFS_REG32(SOR_CCRC_B0),
1364         DEBUGFS_REG32(SOR_CCRC_B1),
1365         DEBUGFS_REG32(SOR_EDATA_A0),
1366         DEBUGFS_REG32(SOR_EDATA_A1),
1367         DEBUGFS_REG32(SOR_EDATA_B0),
1368         DEBUGFS_REG32(SOR_EDATA_B1),
1369         DEBUGFS_REG32(SOR_COUNT_A0),
1370         DEBUGFS_REG32(SOR_COUNT_A1),
1371         DEBUGFS_REG32(SOR_COUNT_B0),
1372         DEBUGFS_REG32(SOR_COUNT_B1),
1373         DEBUGFS_REG32(SOR_DEBUG_A0),
1374         DEBUGFS_REG32(SOR_DEBUG_A1),
1375         DEBUGFS_REG32(SOR_DEBUG_B0),
1376         DEBUGFS_REG32(SOR_DEBUG_B1),
1377         DEBUGFS_REG32(SOR_TRIG),
1378         DEBUGFS_REG32(SOR_MSCHECK),
1379         DEBUGFS_REG32(SOR_XBAR_CTRL),
1380         DEBUGFS_REG32(SOR_XBAR_POL),
1381         DEBUGFS_REG32(SOR_DP_LINKCTL0),
1382         DEBUGFS_REG32(SOR_DP_LINKCTL1),
1383         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1384         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1385         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1386         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1387         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1388         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1389         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1390         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1391         DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1392         DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1393         DEBUGFS_REG32(SOR_DP_CONFIG0),
1394         DEBUGFS_REG32(SOR_DP_CONFIG1),
1395         DEBUGFS_REG32(SOR_DP_MN0),
1396         DEBUGFS_REG32(SOR_DP_MN1),
1397         DEBUGFS_REG32(SOR_DP_PADCTL0),
1398         DEBUGFS_REG32(SOR_DP_PADCTL1),
1399         DEBUGFS_REG32(SOR_DP_PADCTL2),
1400         DEBUGFS_REG32(SOR_DP_DEBUG0),
1401         DEBUGFS_REG32(SOR_DP_DEBUG1),
1402         DEBUGFS_REG32(SOR_DP_SPARE0),
1403         DEBUGFS_REG32(SOR_DP_SPARE1),
1404         DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1405         DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1406         DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1407         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1408         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1409         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1410         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1411         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1412         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1413         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1414         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1415         DEBUGFS_REG32(SOR_DP_TPG),
1416         DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1417         DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1418         DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1419         DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1420 };
1421
1422 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1423 {
1424         struct drm_info_node *node = s->private;
1425         struct tegra_sor *sor = node->info_ent->data;
1426         struct drm_crtc *crtc = sor->output.encoder.crtc;
1427         struct drm_device *drm = node->minor->dev;
1428         unsigned int i;
1429         int err = 0;
1430
1431         drm_modeset_lock_all(drm);
1432
1433         if (!crtc || !crtc->state->active) {
1434                 err = -EBUSY;
1435                 goto unlock;
1436         }
1437
1438         for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1439                 unsigned int offset = tegra_sor_regs[i].offset;
1440
1441                 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1442                            offset, tegra_sor_readl(sor, offset));
1443         }
1444
1445 unlock:
1446         drm_modeset_unlock_all(drm);
1447         return err;
1448 }
1449
1450 static const struct drm_info_list debugfs_files[] = {
1451         { "crc", tegra_sor_show_crc, 0, NULL },
1452         { "regs", tegra_sor_show_regs, 0, NULL },
1453 };
1454
1455 static int tegra_sor_late_register(struct drm_connector *connector)
1456 {
1457         struct tegra_output *output = connector_to_output(connector);
1458         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1459         struct drm_minor *minor = connector->dev->primary;
1460         struct dentry *root = connector->debugfs_entry;
1461         struct tegra_sor *sor = to_sor(output);
1462         int err;
1463
1464         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1465                                      GFP_KERNEL);
1466         if (!sor->debugfs_files)
1467                 return -ENOMEM;
1468
1469         for (i = 0; i < count; i++)
1470                 sor->debugfs_files[i].data = sor;
1471
1472         err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1473         if (err < 0)
1474                 goto free;
1475
1476         return 0;
1477
1478 free:
1479         kfree(sor->debugfs_files);
1480         sor->debugfs_files = NULL;
1481
1482         return err;
1483 }
1484
1485 static void tegra_sor_early_unregister(struct drm_connector *connector)
1486 {
1487         struct tegra_output *output = connector_to_output(connector);
1488         unsigned int count = ARRAY_SIZE(debugfs_files);
1489         struct tegra_sor *sor = to_sor(output);
1490
1491         drm_debugfs_remove_files(sor->debugfs_files, count,
1492                                  connector->dev->primary);
1493         kfree(sor->debugfs_files);
1494         sor->debugfs_files = NULL;
1495 }
1496
1497 static void tegra_sor_connector_reset(struct drm_connector *connector)
1498 {
1499         struct tegra_sor_state *state;
1500
1501         state = kzalloc(sizeof(*state), GFP_KERNEL);
1502         if (!state)
1503                 return;
1504
1505         if (connector->state) {
1506                 __drm_atomic_helper_connector_destroy_state(connector->state);
1507                 kfree(connector->state);
1508         }
1509
1510         __drm_atomic_helper_connector_reset(connector, &state->base);
1511 }
1512
1513 static enum drm_connector_status
1514 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1515 {
1516         struct tegra_output *output = connector_to_output(connector);
1517         struct tegra_sor *sor = to_sor(output);
1518
1519         if (sor->aux)
1520                 return drm_dp_aux_detect(sor->aux);
1521
1522         return tegra_output_connector_detect(connector, force);
1523 }
1524
1525 static struct drm_connector_state *
1526 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1527 {
1528         struct tegra_sor_state *state = to_sor_state(connector->state);
1529         struct tegra_sor_state *copy;
1530
1531         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1532         if (!copy)
1533                 return NULL;
1534
1535         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1536
1537         return &copy->base;
1538 }
1539
1540 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1541         .reset = tegra_sor_connector_reset,
1542         .detect = tegra_sor_connector_detect,
1543         .fill_modes = drm_helper_probe_single_connector_modes,
1544         .destroy = tegra_output_connector_destroy,
1545         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1546         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1547         .late_register = tegra_sor_late_register,
1548         .early_unregister = tegra_sor_early_unregister,
1549 };
1550
1551 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1552 {
1553         struct tegra_output *output = connector_to_output(connector);
1554         struct tegra_sor *sor = to_sor(output);
1555         int err;
1556
1557         if (sor->aux)
1558                 drm_dp_aux_enable(sor->aux);
1559
1560         err = tegra_output_connector_get_modes(connector);
1561
1562         if (sor->aux)
1563                 drm_dp_aux_disable(sor->aux);
1564
1565         return err;
1566 }
1567
1568 static enum drm_mode_status
1569 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1570                                struct drm_display_mode *mode)
1571 {
1572         return MODE_OK;
1573 }
1574
1575 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1576         .get_modes = tegra_sor_connector_get_modes,
1577         .mode_valid = tegra_sor_connector_mode_valid,
1578 };
1579
1580 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1581         .destroy = tegra_output_encoder_destroy,
1582 };
1583
1584 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1585 {
1586         struct tegra_output *output = encoder_to_output(encoder);
1587         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1588         struct tegra_sor *sor = to_sor(output);
1589         u32 value;
1590         int err;
1591
1592         if (output->panel)
1593                 drm_panel_disable(output->panel);
1594
1595         err = tegra_sor_detach(sor);
1596         if (err < 0)
1597                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1598
1599         tegra_sor_writel(sor, 0, SOR_STATE1);
1600         tegra_sor_update(sor);
1601
1602         /*
1603          * The following accesses registers of the display controller, so make
1604          * sure it's only executed when the output is attached to one.
1605          */
1606         if (dc) {
1607                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1608                 value &= ~SOR_ENABLE(0);
1609                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1610
1611                 tegra_dc_commit(dc);
1612         }
1613
1614         err = tegra_sor_power_down(sor);
1615         if (err < 0)
1616                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1617
1618         if (sor->aux) {
1619                 err = drm_dp_aux_disable(sor->aux);
1620                 if (err < 0)
1621                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1622         }
1623
1624         err = tegra_io_pad_power_disable(sor->pad);
1625         if (err < 0)
1626                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1627
1628         if (output->panel)
1629                 drm_panel_unprepare(output->panel);
1630
1631         pm_runtime_put(sor->dev);
1632 }
1633
1634 #if 0
1635 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1636                               unsigned int *value)
1637 {
1638         unsigned int hfp, hsw, hbp, a = 0, b;
1639
1640         hfp = mode->hsync_start - mode->hdisplay;
1641         hsw = mode->hsync_end - mode->hsync_start;
1642         hbp = mode->htotal - mode->hsync_end;
1643
1644         pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1645
1646         b = hfp - 1;
1647
1648         pr_info("a: %u, b: %u\n", a, b);
1649         pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1650
1651         if (a + hsw + hbp <= 11) {
1652                 a = 1 + 11 - hsw - hbp;
1653                 pr_info("a: %u\n", a);
1654         }
1655
1656         if (a > b)
1657                 return -EINVAL;
1658
1659         if (hsw < 1)
1660                 return -EINVAL;
1661
1662         if (mode->hdisplay < 16)
1663                 return -EINVAL;
1664
1665         if (value) {
1666                 if (b > a && a % 2)
1667                         *value = a + 1;
1668                 else
1669                         *value = a;
1670         }
1671
1672         return 0;
1673 }
1674 #endif
1675
1676 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1677 {
1678         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1679         struct tegra_output *output = encoder_to_output(encoder);
1680         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1681         struct tegra_sor *sor = to_sor(output);
1682         struct tegra_sor_config config;
1683         struct tegra_sor_state *state;
1684         struct drm_dp_link link;
1685         u8 rate, lanes;
1686         unsigned int i;
1687         int err = 0;
1688         u32 value;
1689
1690         state = to_sor_state(output->connector.state);
1691
1692         pm_runtime_get_sync(sor->dev);
1693
1694         if (output->panel)
1695                 drm_panel_prepare(output->panel);
1696
1697         err = drm_dp_aux_enable(sor->aux);
1698         if (err < 0)
1699                 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1700
1701         err = drm_dp_link_probe(sor->aux, &link);
1702         if (err < 0) {
1703                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1704                 return;
1705         }
1706
1707         /* switch to safe parent clock */
1708         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1709         if (err < 0)
1710                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1711
1712         memset(&config, 0, sizeof(config));
1713         config.bits_per_pixel = state->bpc * 3;
1714
1715         err = tegra_sor_compute_config(sor, mode, &config, &link);
1716         if (err < 0)
1717                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1718
1719         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1720         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1721         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1722         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1723
1724         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1725         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1726         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1727         usleep_range(20, 100);
1728
1729         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1730         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1731         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1732
1733         value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1734                 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1735         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1736
1737         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1738         value |= SOR_PLL2_SEQ_PLLCAPPD;
1739         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1740         value |= SOR_PLL2_LVDS_ENABLE;
1741         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1742
1743         value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1744         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
1745
1746         while (true) {
1747                 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1748                 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1749                         break;
1750
1751                 usleep_range(250, 1000);
1752         }
1753
1754         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1755         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1756         value &= ~SOR_PLL2_PORT_POWERDOWN;
1757         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1758
1759         /*
1760          * power up
1761          */
1762
1763         /* set safe link bandwidth (1.62 Gbps) */
1764         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1765         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1766         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1767         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1768
1769         /* step 1 */
1770         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1771         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1772                  SOR_PLL2_BANDGAP_POWERDOWN;
1773         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1774
1775         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1776         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1777         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1778
1779         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1780         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1781         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1782
1783         /* step 2 */
1784         err = tegra_io_pad_power_enable(sor->pad);
1785         if (err < 0)
1786                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
1787
1788         usleep_range(5, 100);
1789
1790         /* step 3 */
1791         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1792         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1793         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1794
1795         usleep_range(20, 100);
1796
1797         /* step 4 */
1798         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1799         value &= ~SOR_PLL0_VCOPD;
1800         value &= ~SOR_PLL0_PWR;
1801         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1802
1803         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1804         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1805         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1806
1807         usleep_range(200, 1000);
1808
1809         /* step 5 */
1810         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1811         value &= ~SOR_PLL2_PORT_POWERDOWN;
1812         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1813
1814         /* XXX not in TRM */
1815         for (value = 0, i = 0; i < 5; i++)
1816                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
1817                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1818
1819         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1820         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1821
1822         /* switch to DP parent clock */
1823         err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1824         if (err < 0)
1825                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1826
1827         /* power DP lanes */
1828         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1829
1830         if (link.num_lanes <= 2)
1831                 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1832         else
1833                 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1834
1835         if (link.num_lanes <= 1)
1836                 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1837         else
1838                 value |= SOR_DP_PADCTL_PD_TXD_1;
1839
1840         if (link.num_lanes == 0)
1841                 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1842         else
1843                 value |= SOR_DP_PADCTL_PD_TXD_0;
1844
1845         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1846
1847         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1848         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1849         value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1850         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1851
1852         /* start lane sequencer */
1853         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1854                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1855         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1856
1857         while (true) {
1858                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1859                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1860                         break;
1861
1862                 usleep_range(250, 1000);
1863         }
1864
1865         /* set link bandwidth */
1866         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1867         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1868         value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1869         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1870
1871         tegra_sor_apply_config(sor, &config);
1872
1873         /* enable link */
1874         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1875         value |= SOR_DP_LINKCTL_ENABLE;
1876         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1877         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1878
1879         for (i = 0, value = 0; i < 4; i++) {
1880                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1881                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1882                                      SOR_DP_TPG_PATTERN_NONE;
1883                 value = (value << 8) | lane;
1884         }
1885
1886         tegra_sor_writel(sor, value, SOR_DP_TPG);
1887
1888         /* enable pad calibration logic */
1889         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1890         value |= SOR_DP_PADCTL_PAD_CAL_PD;
1891         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1892
1893         err = drm_dp_link_probe(sor->aux, &link);
1894         if (err < 0)
1895                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1896
1897         err = drm_dp_link_power_up(sor->aux, &link);
1898         if (err < 0)
1899                 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1900
1901         err = drm_dp_link_configure(sor->aux, &link);
1902         if (err < 0)
1903                 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1904
1905         rate = drm_dp_link_rate_to_bw_code(link.rate);
1906         lanes = link.num_lanes;
1907
1908         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1909         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1910         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1911         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1912
1913         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1914         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1915         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1916
1917         if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1918                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1919
1920         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1921
1922         /* disable training pattern generator */
1923
1924         for (i = 0; i < link.num_lanes; i++) {
1925                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1926                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1927                                      SOR_DP_TPG_PATTERN_NONE;
1928                 value = (value << 8) | lane;
1929         }
1930
1931         tegra_sor_writel(sor, value, SOR_DP_TPG);
1932
1933         err = tegra_sor_dp_train_fast(sor, &link);
1934         if (err < 0)
1935                 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1936
1937         dev_dbg(sor->dev, "fast link training succeeded\n");
1938
1939         err = tegra_sor_power_up(sor, 250);
1940         if (err < 0)
1941                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1942
1943         /* CSTM (LVDS, link A/B, upper) */
1944         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1945                 SOR_CSTM_UPPER;
1946         tegra_sor_writel(sor, value, SOR_CSTM);
1947
1948         /* use DP-A protocol */
1949         value = tegra_sor_readl(sor, SOR_STATE1);
1950         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1951         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1952         tegra_sor_writel(sor, value, SOR_STATE1);
1953
1954         tegra_sor_mode_set(sor, mode, state);
1955
1956         /* PWM setup */
1957         err = tegra_sor_setup_pwm(sor, 250);
1958         if (err < 0)
1959                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1960
1961         tegra_sor_update(sor);
1962
1963         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1964         value |= SOR_ENABLE(0);
1965         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1966
1967         tegra_dc_commit(dc);
1968
1969         err = tegra_sor_attach(sor);
1970         if (err < 0)
1971                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1972
1973         err = tegra_sor_wakeup(sor);
1974         if (err < 0)
1975                 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1976
1977         if (output->panel)
1978                 drm_panel_enable(output->panel);
1979 }
1980
1981 static int
1982 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1983                                struct drm_crtc_state *crtc_state,
1984                                struct drm_connector_state *conn_state)
1985 {
1986         struct tegra_output *output = encoder_to_output(encoder);
1987         struct tegra_sor_state *state = to_sor_state(conn_state);
1988         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1989         unsigned long pclk = crtc_state->mode.clock * 1000;
1990         struct tegra_sor *sor = to_sor(output);
1991         struct drm_display_info *info;
1992         int err;
1993
1994         info = &output->connector.display_info;
1995
1996         /*
1997          * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1998          * the pixel clock must be corrected accordingly.
1999          */
2000         if (pclk >= 340000000) {
2001                 state->link_speed = 20;
2002                 state->pclk = pclk / 2;
2003         } else {
2004                 state->link_speed = 10;
2005                 state->pclk = pclk;
2006         }
2007
2008         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
2009                                          pclk, 0);
2010         if (err < 0) {
2011                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
2012                 return err;
2013         }
2014
2015         switch (info->bpc) {
2016         case 8:
2017         case 6:
2018                 state->bpc = info->bpc;
2019                 break;
2020
2021         default:
2022                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
2023                 state->bpc = 8;
2024                 break;
2025         }
2026
2027         return 0;
2028 }
2029
2030 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
2031         .disable = tegra_sor_edp_disable,
2032         .enable = tegra_sor_edp_enable,
2033         .atomic_check = tegra_sor_encoder_atomic_check,
2034 };
2035
2036 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
2037 {
2038         u32 value = 0;
2039         size_t i;
2040
2041         for (i = size; i > 0; i--)
2042                 value = (value << 8) | ptr[i - 1];
2043
2044         return value;
2045 }
2046
2047 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
2048                                           const void *data, size_t size)
2049 {
2050         const u8 *ptr = data;
2051         unsigned long offset;
2052         size_t i, j;
2053         u32 value;
2054
2055         switch (ptr[0]) {
2056         case HDMI_INFOFRAME_TYPE_AVI:
2057                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
2058                 break;
2059
2060         case HDMI_INFOFRAME_TYPE_AUDIO:
2061                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
2062                 break;
2063
2064         case HDMI_INFOFRAME_TYPE_VENDOR:
2065                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
2066                 break;
2067
2068         default:
2069                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
2070                         ptr[0]);
2071                 return;
2072         }
2073
2074         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2075                 INFOFRAME_HEADER_VERSION(ptr[1]) |
2076                 INFOFRAME_HEADER_LEN(ptr[2]);
2077         tegra_sor_writel(sor, value, offset);
2078         offset++;
2079
2080         /*
2081          * Each subpack contains 7 bytes, divided into:
2082          * - subpack_low: bytes 0 - 3
2083          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2084          */
2085         for (i = 3, j = 0; i < size; i += 7, j += 8) {
2086                 size_t rem = size - i, num = min_t(size_t, rem, 4);
2087
2088                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2089                 tegra_sor_writel(sor, value, offset++);
2090
2091                 num = min_t(size_t, rem - num, 3);
2092
2093                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2094                 tegra_sor_writel(sor, value, offset++);
2095         }
2096 }
2097
2098 static int
2099 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2100                                    const struct drm_display_mode *mode)
2101 {
2102         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2103         struct hdmi_avi_infoframe frame;
2104         u32 value;
2105         int err;
2106
2107         /* disable AVI infoframe */
2108         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2109         value &= ~INFOFRAME_CTRL_SINGLE;
2110         value &= ~INFOFRAME_CTRL_OTHER;
2111         value &= ~INFOFRAME_CTRL_ENABLE;
2112         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2113
2114         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2115                                                        &sor->output.connector, mode);
2116         if (err < 0) {
2117                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2118                 return err;
2119         }
2120
2121         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2122         if (err < 0) {
2123                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2124                 return err;
2125         }
2126
2127         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2128
2129         /* enable AVI infoframe */
2130         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2131         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2132         value |= INFOFRAME_CTRL_ENABLE;
2133         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2134
2135         return 0;
2136 }
2137
2138 static void tegra_sor_write_eld(struct tegra_sor *sor)
2139 {
2140         size_t length = drm_eld_size(sor->output.connector.eld), i;
2141
2142         for (i = 0; i < length; i++)
2143                 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2144                                  SOR_AUDIO_HDA_ELD_BUFWR);
2145
2146         /*
2147          * The HDA codec will always report an ELD buffer size of 96 bytes and
2148          * the HDA codec driver will check that each byte read from the buffer
2149          * is valid. Therefore every byte must be written, even if no 96 bytes
2150          * were parsed from EDID.
2151          */
2152         for (i = length; i < 96; i++)
2153                 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2154 }
2155
2156 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2157 {
2158         u32 value;
2159
2160         tegra_sor_write_eld(sor);
2161
2162         value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2163         tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2164 }
2165
2166 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2167 {
2168         tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2169 }
2170
2171 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2172 {
2173         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2174         struct hdmi_audio_infoframe frame;
2175         u32 value;
2176         int err;
2177
2178         err = hdmi_audio_infoframe_init(&frame);
2179         if (err < 0) {
2180                 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2181                 return err;
2182         }
2183
2184         frame.channels = sor->format.channels;
2185
2186         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2187         if (err < 0) {
2188                 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2189                 return err;
2190         }
2191
2192         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2193
2194         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2195         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2196         value |= INFOFRAME_CTRL_ENABLE;
2197         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2198
2199         return 0;
2200 }
2201
2202 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2203 {
2204         u32 value;
2205
2206         value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2207
2208         /* select HDA audio input */
2209         value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2210         value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2211
2212         /* inject null samples */
2213         if (sor->format.channels != 2)
2214                 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2215         else
2216                 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2217
2218         value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2219
2220         tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2221
2222         /* enable advertising HBR capability */
2223         tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2224
2225         tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2226
2227         value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2228                 SOR_HDMI_SPARE_CTS_RESET(1) |
2229                 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2230         tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2231
2232         /* enable HW CTS */
2233         value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2234         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2235
2236         /* allow packet to be sent */
2237         value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2238         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2239
2240         /* reset N counter and enable lookup */
2241         value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2242         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2243
2244         value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2245         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2246         tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2247
2248         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2249         tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2250
2251         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2252         tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2253
2254         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2255         tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2256
2257         value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2258         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2259         tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2260
2261         value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2262         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2263         tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2264
2265         value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2266         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2267         tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2268
2269         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2270         value &= ~SOR_HDMI_AUDIO_N_RESET;
2271         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2272
2273         tegra_sor_hdmi_enable_audio_infoframe(sor);
2274 }
2275
2276 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2277 {
2278         u32 value;
2279
2280         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2281         value &= ~INFOFRAME_CTRL_ENABLE;
2282         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2283 }
2284
2285 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2286 {
2287         tegra_sor_hdmi_disable_audio_infoframe(sor);
2288 }
2289
2290 static struct tegra_sor_hdmi_settings *
2291 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2292 {
2293         unsigned int i;
2294
2295         for (i = 0; i < sor->num_settings; i++)
2296                 if (frequency <= sor->settings[i].frequency)
2297                         return &sor->settings[i];
2298
2299         return NULL;
2300 }
2301
2302 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2303 {
2304         u32 value;
2305
2306         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2307         value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2308         value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2309         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2310 }
2311
2312 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2313 {
2314         struct i2c_adapter *ddc = sor->output.ddc;
2315
2316         drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2317         drm_scdc_set_scrambling(ddc, false);
2318
2319         tegra_sor_hdmi_disable_scrambling(sor);
2320 }
2321
2322 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2323 {
2324         if (sor->scdc_enabled) {
2325                 cancel_delayed_work_sync(&sor->scdc);
2326                 tegra_sor_hdmi_scdc_disable(sor);
2327         }
2328 }
2329
2330 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2331 {
2332         u32 value;
2333
2334         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2335         value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2336         value |= SOR_HDMI2_CTRL_SCRAMBLE;
2337         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2338 }
2339
2340 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2341 {
2342         struct i2c_adapter *ddc = sor->output.ddc;
2343
2344         drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2345         drm_scdc_set_scrambling(ddc, true);
2346
2347         tegra_sor_hdmi_enable_scrambling(sor);
2348 }
2349
2350 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2351 {
2352         struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2353         struct i2c_adapter *ddc = sor->output.ddc;
2354
2355         if (!drm_scdc_get_scrambling_status(ddc)) {
2356                 DRM_DEBUG_KMS("SCDC not scrambled\n");
2357                 tegra_sor_hdmi_scdc_enable(sor);
2358         }
2359
2360         schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2361 }
2362
2363 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2364 {
2365         struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2366         struct drm_display_mode *mode;
2367
2368         mode = &sor->output.encoder.crtc->state->adjusted_mode;
2369
2370         if (mode->clock >= 340000 && scdc->supported) {
2371                 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2372                 tegra_sor_hdmi_scdc_enable(sor);
2373                 sor->scdc_enabled = true;
2374         }
2375 }
2376
2377 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2378 {
2379         struct tegra_output *output = encoder_to_output(encoder);
2380         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2381         struct tegra_sor *sor = to_sor(output);
2382         u32 value;
2383         int err;
2384
2385         tegra_sor_audio_unprepare(sor);
2386         tegra_sor_hdmi_scdc_stop(sor);
2387
2388         err = tegra_sor_detach(sor);
2389         if (err < 0)
2390                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2391
2392         tegra_sor_writel(sor, 0, SOR_STATE1);
2393         tegra_sor_update(sor);
2394
2395         /* disable display to SOR clock */
2396         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2397
2398         if (!sor->soc->has_nvdisplay)
2399                 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2400         else
2401                 value &= ~SOR_ENABLE(sor->index);
2402
2403         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2404
2405         tegra_dc_commit(dc);
2406
2407         err = tegra_sor_power_down(sor);
2408         if (err < 0)
2409                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2410
2411         err = tegra_io_pad_power_disable(sor->pad);
2412         if (err < 0)
2413                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2414
2415         pm_runtime_put(sor->dev);
2416 }
2417
2418 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2419 {
2420         struct tegra_output *output = encoder_to_output(encoder);
2421         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2422         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2423         struct tegra_sor_hdmi_settings *settings;
2424         struct tegra_sor *sor = to_sor(output);
2425         struct tegra_sor_state *state;
2426         struct drm_display_mode *mode;
2427         unsigned long rate, pclk;
2428         unsigned int div, i;
2429         u32 value;
2430         int err;
2431
2432         state = to_sor_state(output->connector.state);
2433         mode = &encoder->crtc->state->adjusted_mode;
2434         pclk = mode->clock * 1000;
2435
2436         pm_runtime_get_sync(sor->dev);
2437
2438         /* switch to safe parent clock */
2439         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2440         if (err < 0) {
2441                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2442                 return;
2443         }
2444
2445         div = clk_get_rate(sor->clk) / 1000000 * 4;
2446
2447         err = tegra_io_pad_power_enable(sor->pad);
2448         if (err < 0)
2449                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2450
2451         usleep_range(20, 100);
2452
2453         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2454         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2455         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2456
2457         usleep_range(20, 100);
2458
2459         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2460         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2461         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2462
2463         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2464         value &= ~SOR_PLL0_VCOPD;
2465         value &= ~SOR_PLL0_PWR;
2466         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2467
2468         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2469         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2470         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2471
2472         usleep_range(200, 400);
2473
2474         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2475         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2476         value &= ~SOR_PLL2_PORT_POWERDOWN;
2477         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2478
2479         usleep_range(20, 100);
2480
2481         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2482         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2483                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2484         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2485
2486         while (true) {
2487                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2488                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2489                         break;
2490
2491                 usleep_range(250, 1000);
2492         }
2493
2494         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2495                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2496         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2497
2498         while (true) {
2499                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2500                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2501                         break;
2502
2503                 usleep_range(250, 1000);
2504         }
2505
2506         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2507         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2508         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2509
2510         if (mode->clock < 340000) {
2511                 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2512                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2513         } else {
2514                 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2515                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2516         }
2517
2518         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2519         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2520
2521         /* SOR pad PLL stabilization time */
2522         usleep_range(250, 1000);
2523
2524         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2525         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2526         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2527         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2528
2529         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2530         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2531         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2532         value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2533         value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2534         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2535
2536         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2537                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2538         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2539
2540         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2541                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2542         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2543         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2544
2545         if (!sor->soc->has_nvdisplay) {
2546                 /* program the reference clock */
2547                 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2548                 tegra_sor_writel(sor, value, SOR_REFCLK);
2549         }
2550
2551         /* XXX not in TRM */
2552         for (value = 0, i = 0; i < 5; i++)
2553                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2554                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2555
2556         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2557         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2558
2559         /* switch to parent clock */
2560         err = clk_set_parent(sor->clk, sor->clk_parent);
2561         if (err < 0) {
2562                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2563                 return;
2564         }
2565
2566         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2567         if (err < 0) {
2568                 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2569                 return;
2570         }
2571
2572         /* adjust clock rate for HDMI 2.0 modes */
2573         rate = clk_get_rate(sor->clk_parent);
2574
2575         if (mode->clock >= 340000)
2576                 rate /= 2;
2577
2578         DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2579
2580         clk_set_rate(sor->clk, rate);
2581
2582         if (!sor->soc->has_nvdisplay) {
2583                 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2584
2585                 /* XXX is this the proper check? */
2586                 if (mode->clock < 75000)
2587                         value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2588
2589                 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2590         }
2591
2592         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2593
2594         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2595                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2596         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2597
2598         if (!dc->soc->has_nvdisplay) {
2599                 /* H_PULSE2 setup */
2600                 pulse_start = h_ref_to_sync +
2601                               (mode->hsync_end - mode->hsync_start) +
2602                               (mode->htotal - mode->hsync_end) - 10;
2603
2604                 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2605                         PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2606                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2607
2608                 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2609                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2610
2611                 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2612                 value |= H_PULSE2_ENABLE;
2613                 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2614         }
2615
2616         /* infoframe setup */
2617         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2618         if (err < 0)
2619                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2620
2621         /* XXX HDMI audio support not implemented yet */
2622         tegra_sor_hdmi_disable_audio_infoframe(sor);
2623
2624         /* use single TMDS protocol */
2625         value = tegra_sor_readl(sor, SOR_STATE1);
2626         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2627         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2628         tegra_sor_writel(sor, value, SOR_STATE1);
2629
2630         /* power up pad calibration */
2631         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2632         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2633         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2634
2635         /* production settings */
2636         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2637         if (!settings) {
2638                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2639                         mode->clock * 1000);
2640                 return;
2641         }
2642
2643         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2644         value &= ~SOR_PLL0_ICHPMP_MASK;
2645         value &= ~SOR_PLL0_FILTER_MASK;
2646         value &= ~SOR_PLL0_VCOCAP_MASK;
2647         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2648         value |= SOR_PLL0_FILTER(settings->filter);
2649         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2650         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2651
2652         /* XXX not in TRM */
2653         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2654         value &= ~SOR_PLL1_LOADADJ_MASK;
2655         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2656         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2657         value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2658         value |= SOR_PLL1_TMDS_TERM;
2659         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2660
2661         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2662         value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2663         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2664         value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2665         value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2666         value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2667         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2668         value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2669         value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2670         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2671
2672         value = settings->drive_current[3] << 24 |
2673                 settings->drive_current[2] << 16 |
2674                 settings->drive_current[1] <<  8 |
2675                 settings->drive_current[0] <<  0;
2676         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2677
2678         value = settings->preemphasis[3] << 24 |
2679                 settings->preemphasis[2] << 16 |
2680                 settings->preemphasis[1] <<  8 |
2681                 settings->preemphasis[0] <<  0;
2682         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2683
2684         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2685         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2686         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2687         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2688         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2689
2690         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2691         value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2692         value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2693         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2694
2695         /* power down pad calibration */
2696         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2697         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2698         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2699
2700         if (!dc->soc->has_nvdisplay) {
2701                 /* miscellaneous display controller settings */
2702                 value = VSYNC_H_POSITION(1);
2703                 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2704         }
2705
2706         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2707         value &= ~DITHER_CONTROL_MASK;
2708         value &= ~BASE_COLOR_SIZE_MASK;
2709
2710         switch (state->bpc) {
2711         case 6:
2712                 value |= BASE_COLOR_SIZE_666;
2713                 break;
2714
2715         case 8:
2716                 value |= BASE_COLOR_SIZE_888;
2717                 break;
2718
2719         case 10:
2720                 value |= BASE_COLOR_SIZE_101010;
2721                 break;
2722
2723         case 12:
2724                 value |= BASE_COLOR_SIZE_121212;
2725                 break;
2726
2727         default:
2728                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2729                 value |= BASE_COLOR_SIZE_888;
2730                 break;
2731         }
2732
2733         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2734
2735         /* XXX set display head owner */
2736         value = tegra_sor_readl(sor, SOR_STATE1);
2737         value &= ~SOR_STATE_ASY_OWNER_MASK;
2738         value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2739         tegra_sor_writel(sor, value, SOR_STATE1);
2740
2741         err = tegra_sor_power_up(sor, 250);
2742         if (err < 0)
2743                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2744
2745         /* configure dynamic range of output */
2746         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2747         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2748         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2749         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2750
2751         /* configure colorspace */
2752         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2753         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2754         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2755         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2756
2757         tegra_sor_mode_set(sor, mode, state);
2758
2759         tegra_sor_update(sor);
2760
2761         /* program preamble timing in SOR (XXX) */
2762         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2763         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2764         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2765
2766         err = tegra_sor_attach(sor);
2767         if (err < 0)
2768                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2769
2770         /* enable display to SOR clock and generate HDMI preamble */
2771         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2772
2773         if (!sor->soc->has_nvdisplay)
2774                 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2775         else
2776                 value |= SOR_ENABLE(sor->index);
2777
2778         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2779
2780         if (dc->soc->has_nvdisplay) {
2781                 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2782                 value &= ~PROTOCOL_MASK;
2783                 value |= PROTOCOL_SINGLE_TMDS_A;
2784                 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2785         }
2786
2787         tegra_dc_commit(dc);
2788
2789         err = tegra_sor_wakeup(sor);
2790         if (err < 0)
2791                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2792
2793         tegra_sor_hdmi_scdc_start(sor);
2794         tegra_sor_audio_prepare(sor);
2795 }
2796
2797 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2798         .disable = tegra_sor_hdmi_disable,
2799         .enable = tegra_sor_hdmi_enable,
2800         .atomic_check = tegra_sor_encoder_atomic_check,
2801 };
2802
2803 static int tegra_sor_init(struct host1x_client *client)
2804 {
2805         struct drm_device *drm = dev_get_drvdata(client->parent);
2806         const struct drm_encoder_helper_funcs *helpers = NULL;
2807         struct tegra_sor *sor = host1x_client_to_sor(client);
2808         int connector = DRM_MODE_CONNECTOR_Unknown;
2809         int encoder = DRM_MODE_ENCODER_NONE;
2810         u32 value;
2811         int err;
2812
2813         if (!sor->aux) {
2814                 if (sor->soc->supports_hdmi) {
2815                         connector = DRM_MODE_CONNECTOR_HDMIA;
2816                         encoder = DRM_MODE_ENCODER_TMDS;
2817                         helpers = &tegra_sor_hdmi_helpers;
2818                 } else if (sor->soc->supports_lvds) {
2819                         connector = DRM_MODE_CONNECTOR_LVDS;
2820                         encoder = DRM_MODE_ENCODER_LVDS;
2821                 }
2822         } else {
2823                 if (sor->soc->supports_edp) {
2824                         connector = DRM_MODE_CONNECTOR_eDP;
2825                         encoder = DRM_MODE_ENCODER_TMDS;
2826                         helpers = &tegra_sor_edp_helpers;
2827                 } else if (sor->soc->supports_dp) {
2828                         connector = DRM_MODE_CONNECTOR_DisplayPort;
2829                         encoder = DRM_MODE_ENCODER_TMDS;
2830                 }
2831         }
2832
2833         sor->output.dev = sor->dev;
2834
2835         drm_connector_init(drm, &sor->output.connector,
2836                            &tegra_sor_connector_funcs,
2837                            connector);
2838         drm_connector_helper_add(&sor->output.connector,
2839                                  &tegra_sor_connector_helper_funcs);
2840         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2841
2842         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2843                          encoder, NULL);
2844         drm_encoder_helper_add(&sor->output.encoder, helpers);
2845
2846         drm_connector_attach_encoder(&sor->output.connector,
2847                                           &sor->output.encoder);
2848         drm_connector_register(&sor->output.connector);
2849
2850         err = tegra_output_init(drm, &sor->output);
2851         if (err < 0) {
2852                 dev_err(client->dev, "failed to initialize output: %d\n", err);
2853                 return err;
2854         }
2855
2856         tegra_output_find_possible_crtcs(&sor->output, drm);
2857
2858         if (sor->aux) {
2859                 err = drm_dp_aux_attach(sor->aux, &sor->output);
2860                 if (err < 0) {
2861                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
2862                         return err;
2863                 }
2864         }
2865
2866         /*
2867          * XXX: Remove this reset once proper hand-over from firmware to
2868          * kernel is possible.
2869          */
2870         if (sor->rst) {
2871                 err = reset_control_acquire(sor->rst);
2872                 if (err < 0) {
2873                         dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
2874                                 err);
2875                         return err;
2876                 }
2877
2878                 err = reset_control_assert(sor->rst);
2879                 if (err < 0) {
2880                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2881                                 err);
2882                         return err;
2883                 }
2884         }
2885
2886         err = clk_prepare_enable(sor->clk);
2887         if (err < 0) {
2888                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2889                 return err;
2890         }
2891
2892         usleep_range(1000, 3000);
2893
2894         if (sor->rst) {
2895                 err = reset_control_deassert(sor->rst);
2896                 if (err < 0) {
2897                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2898                                 err);
2899                         return err;
2900                 }
2901
2902                 reset_control_release(sor->rst);
2903         }
2904
2905         err = clk_prepare_enable(sor->clk_safe);
2906         if (err < 0)
2907                 return err;
2908
2909         err = clk_prepare_enable(sor->clk_dp);
2910         if (err < 0)
2911                 return err;
2912
2913         /*
2914          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2915          * is used for interoperability between the HDA codec driver and the
2916          * HDMI/DP driver.
2917          */
2918         value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2919         tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2920         tegra_sor_writel(sor, value, SOR_INT_MASK);
2921
2922         return 0;
2923 }
2924
2925 static int tegra_sor_exit(struct host1x_client *client)
2926 {
2927         struct tegra_sor *sor = host1x_client_to_sor(client);
2928         int err;
2929
2930         tegra_sor_writel(sor, 0, SOR_INT_MASK);
2931         tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2932
2933         tegra_output_exit(&sor->output);
2934
2935         if (sor->aux) {
2936                 err = drm_dp_aux_detach(sor->aux);
2937                 if (err < 0) {
2938                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
2939                         return err;
2940                 }
2941         }
2942
2943         clk_disable_unprepare(sor->clk_safe);
2944         clk_disable_unprepare(sor->clk_dp);
2945         clk_disable_unprepare(sor->clk);
2946
2947         return 0;
2948 }
2949
2950 static const struct host1x_client_ops sor_client_ops = {
2951         .init = tegra_sor_init,
2952         .exit = tegra_sor_exit,
2953 };
2954
2955 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2956         .name = "eDP",
2957 };
2958
2959 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2960 {
2961         int err;
2962
2963         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2964         if (IS_ERR(sor->avdd_io_supply)) {
2965                 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2966                         PTR_ERR(sor->avdd_io_supply));
2967                 return PTR_ERR(sor->avdd_io_supply);
2968         }
2969
2970         err = regulator_enable(sor->avdd_io_supply);
2971         if (err < 0) {
2972                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2973                         err);
2974                 return err;
2975         }
2976
2977         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2978         if (IS_ERR(sor->vdd_pll_supply)) {
2979                 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2980                         PTR_ERR(sor->vdd_pll_supply));
2981                 return PTR_ERR(sor->vdd_pll_supply);
2982         }
2983
2984         err = regulator_enable(sor->vdd_pll_supply);
2985         if (err < 0) {
2986                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2987                         err);
2988                 return err;
2989         }
2990
2991         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2992         if (IS_ERR(sor->hdmi_supply)) {
2993                 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2994                         PTR_ERR(sor->hdmi_supply));
2995                 return PTR_ERR(sor->hdmi_supply);
2996         }
2997
2998         err = regulator_enable(sor->hdmi_supply);
2999         if (err < 0) {
3000                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3001                 return err;
3002         }
3003
3004         INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3005
3006         return 0;
3007 }
3008
3009 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3010 {
3011         regulator_disable(sor->hdmi_supply);
3012         regulator_disable(sor->vdd_pll_supply);
3013         regulator_disable(sor->avdd_io_supply);
3014
3015         return 0;
3016 }
3017
3018 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3019         .name = "HDMI",
3020         .probe = tegra_sor_hdmi_probe,
3021         .remove = tegra_sor_hdmi_remove,
3022 };
3023
3024 static const u8 tegra124_sor_xbar_cfg[5] = {
3025         0, 1, 2, 3, 4
3026 };
3027
3028 static const struct tegra_sor_regs tegra124_sor_regs = {
3029         .head_state0 = 0x05,
3030         .head_state1 = 0x07,
3031         .head_state2 = 0x09,
3032         .head_state3 = 0x0b,
3033         .head_state4 = 0x0d,
3034         .head_state5 = 0x0f,
3035         .pll0 = 0x17,
3036         .pll1 = 0x18,
3037         .pll2 = 0x19,
3038         .pll3 = 0x1a,
3039         .dp_padctl0 = 0x5c,
3040         .dp_padctl2 = 0x73,
3041 };
3042
3043 static const struct tegra_sor_soc tegra124_sor = {
3044         .supports_edp = true,
3045         .supports_lvds = true,
3046         .supports_hdmi = false,
3047         .supports_dp = false,
3048         .regs = &tegra124_sor_regs,
3049         .has_nvdisplay = false,
3050         .xbar_cfg = tegra124_sor_xbar_cfg,
3051 };
3052
3053 static const struct tegra_sor_regs tegra210_sor_regs = {
3054         .head_state0 = 0x05,
3055         .head_state1 = 0x07,
3056         .head_state2 = 0x09,
3057         .head_state3 = 0x0b,
3058         .head_state4 = 0x0d,
3059         .head_state5 = 0x0f,
3060         .pll0 = 0x17,
3061         .pll1 = 0x18,
3062         .pll2 = 0x19,
3063         .pll3 = 0x1a,
3064         .dp_padctl0 = 0x5c,
3065         .dp_padctl2 = 0x73,
3066 };
3067
3068 static const struct tegra_sor_soc tegra210_sor = {
3069         .supports_edp = true,
3070         .supports_lvds = false,
3071         .supports_hdmi = false,
3072         .supports_dp = false,
3073         .regs = &tegra210_sor_regs,
3074         .has_nvdisplay = false,
3075         .xbar_cfg = tegra124_sor_xbar_cfg,
3076 };
3077
3078 static const u8 tegra210_sor_xbar_cfg[5] = {
3079         2, 1, 0, 3, 4
3080 };
3081
3082 static const struct tegra_sor_soc tegra210_sor1 = {
3083         .supports_edp = false,
3084         .supports_lvds = false,
3085         .supports_hdmi = true,
3086         .supports_dp = true,
3087
3088         .regs = &tegra210_sor_regs,
3089         .has_nvdisplay = false,
3090
3091         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3092         .settings = tegra210_sor_hdmi_defaults,
3093
3094         .xbar_cfg = tegra210_sor_xbar_cfg,
3095 };
3096
3097 static const struct tegra_sor_regs tegra186_sor_regs = {
3098         .head_state0 = 0x151,
3099         .head_state1 = 0x154,
3100         .head_state2 = 0x157,
3101         .head_state3 = 0x15a,
3102         .head_state4 = 0x15d,
3103         .head_state5 = 0x160,
3104         .pll0 = 0x163,
3105         .pll1 = 0x164,
3106         .pll2 = 0x165,
3107         .pll3 = 0x166,
3108         .dp_padctl0 = 0x168,
3109         .dp_padctl2 = 0x16a,
3110 };
3111
3112 static const struct tegra_sor_soc tegra186_sor = {
3113         .supports_edp = false,
3114         .supports_lvds = false,
3115         .supports_hdmi = false,
3116         .supports_dp = true,
3117
3118         .regs = &tegra186_sor_regs,
3119         .has_nvdisplay = true,
3120
3121         .xbar_cfg = tegra124_sor_xbar_cfg,
3122 };
3123
3124 static const struct tegra_sor_soc tegra186_sor1 = {
3125         .supports_edp = false,
3126         .supports_lvds = false,
3127         .supports_hdmi = true,
3128         .supports_dp = true,
3129
3130         .regs = &tegra186_sor_regs,
3131         .has_nvdisplay = true,
3132
3133         .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3134         .settings = tegra186_sor_hdmi_defaults,
3135
3136         .xbar_cfg = tegra124_sor_xbar_cfg,
3137 };
3138
3139 static const struct tegra_sor_regs tegra194_sor_regs = {
3140         .head_state0 = 0x151,
3141         .head_state1 = 0x155,
3142         .head_state2 = 0x159,
3143         .head_state3 = 0x15d,
3144         .head_state4 = 0x161,
3145         .head_state5 = 0x165,
3146         .pll0 = 0x169,
3147         .pll1 = 0x16a,
3148         .pll2 = 0x16b,
3149         .pll3 = 0x16c,
3150         .dp_padctl0 = 0x16e,
3151         .dp_padctl2 = 0x16f,
3152 };
3153
3154 static const struct tegra_sor_soc tegra194_sor = {
3155         .supports_edp = true,
3156         .supports_lvds = false,
3157         .supports_hdmi = true,
3158         .supports_dp = true,
3159
3160         .regs = &tegra194_sor_regs,
3161         .has_nvdisplay = true,
3162
3163         .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3164         .settings = tegra194_sor_hdmi_defaults,
3165
3166         .xbar_cfg = tegra210_sor_xbar_cfg,
3167 };
3168
3169 static const struct of_device_id tegra_sor_of_match[] = {
3170         { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3171         { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
3172         { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3173         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3174         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3175         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3176         { },
3177 };
3178 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3179
3180 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3181 {
3182         struct device_node *np = sor->dev->of_node;
3183         u32 xbar_cfg[5];
3184         unsigned int i;
3185         u32 value;
3186         int err;
3187
3188         if (sor->soc->has_nvdisplay) {
3189                 err = of_property_read_u32(np, "nvidia,interface", &value);
3190                 if (err < 0)
3191                         return err;
3192
3193                 sor->index = value;
3194
3195                 /*
3196                  * override the default that we already set for Tegra210 and
3197                  * earlier
3198                  */
3199                 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3200         }
3201
3202         err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3203         if (err < 0) {
3204                 /* fall back to default per-SoC XBAR configuration */
3205                 for (i = 0; i < 5; i++)
3206                         sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3207         } else {
3208                 /* copy cells to SOR XBAR configuration */
3209                 for (i = 0; i < 5; i++)
3210                         sor->xbar_cfg[i] = xbar_cfg[i];
3211         }
3212
3213         return 0;
3214 }
3215
3216 static irqreturn_t tegra_sor_irq(int irq, void *data)
3217 {
3218         struct tegra_sor *sor = data;
3219         u32 value;
3220
3221         value = tegra_sor_readl(sor, SOR_INT_STATUS);
3222         tegra_sor_writel(sor, value, SOR_INT_STATUS);
3223
3224         if (value & SOR_INT_CODEC_SCRATCH0) {
3225                 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3226
3227                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3228                         unsigned int format;
3229
3230                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3231
3232                         tegra_hda_parse_format(format, &sor->format);
3233
3234                         tegra_sor_hdmi_audio_enable(sor);
3235                 } else {
3236                         tegra_sor_hdmi_audio_disable(sor);
3237                 }
3238         }
3239
3240         return IRQ_HANDLED;
3241 }
3242
3243 static int tegra_sor_probe(struct platform_device *pdev)
3244 {
3245         struct device_node *np;
3246         struct tegra_sor *sor;
3247         struct resource *regs;
3248         int err;
3249
3250         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3251         if (!sor)
3252                 return -ENOMEM;
3253
3254         sor->soc = of_device_get_match_data(&pdev->dev);
3255         sor->output.dev = sor->dev = &pdev->dev;
3256
3257         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3258                                      sor->soc->num_settings *
3259                                         sizeof(*sor->settings),
3260                                      GFP_KERNEL);
3261         if (!sor->settings)
3262                 return -ENOMEM;
3263
3264         sor->num_settings = sor->soc->num_settings;
3265
3266         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3267         if (np) {
3268                 sor->aux = drm_dp_aux_find_by_of_node(np);
3269                 of_node_put(np);
3270
3271                 if (!sor->aux)
3272                         return -EPROBE_DEFER;
3273         }
3274
3275         if (!sor->aux) {
3276                 if (sor->soc->supports_hdmi) {
3277                         sor->ops = &tegra_sor_hdmi_ops;
3278                         sor->pad = TEGRA_IO_PAD_HDMI;
3279                 } else if (sor->soc->supports_lvds) {
3280                         dev_err(&pdev->dev, "LVDS not supported yet\n");
3281                         return -ENODEV;
3282                 } else {
3283                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
3284                         return -ENODEV;
3285                 }
3286         } else {
3287                 if (sor->soc->supports_edp) {
3288                         sor->ops = &tegra_sor_edp_ops;
3289                         sor->pad = TEGRA_IO_PAD_LVDS;
3290                 } else if (sor->soc->supports_dp) {
3291                         dev_err(&pdev->dev, "DisplayPort not supported yet\n");
3292                         return -ENODEV;
3293                 } else {
3294                         dev_err(&pdev->dev, "unknown (DP) support\n");
3295                         return -ENODEV;
3296                 }
3297         }
3298
3299         err = tegra_sor_parse_dt(sor);
3300         if (err < 0)
3301                 return err;
3302
3303         err = tegra_output_probe(&sor->output);
3304         if (err < 0) {
3305                 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3306                 return err;
3307         }
3308
3309         if (sor->ops && sor->ops->probe) {
3310                 err = sor->ops->probe(sor);
3311                 if (err < 0) {
3312                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
3313                                 sor->ops->name, err);
3314                         goto output;
3315                 }
3316         }
3317
3318         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3319         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3320         if (IS_ERR(sor->regs)) {
3321                 err = PTR_ERR(sor->regs);
3322                 goto remove;
3323         }
3324
3325         err = platform_get_irq(pdev, 0);
3326         if (err < 0) {
3327                 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3328                 goto remove;
3329         }
3330
3331         sor->irq = err;
3332
3333         err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3334                                dev_name(sor->dev), sor);
3335         if (err < 0) {
3336                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3337                 goto remove;
3338         }
3339
3340         sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3341         if (IS_ERR(sor->rst)) {
3342                 err = PTR_ERR(sor->rst);
3343
3344                 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3345                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
3346                                 err);
3347                         goto remove;
3348                 }
3349
3350                 /*
3351                  * At this point, the reset control is most likely being used
3352                  * by the generic power domain implementation. With any luck
3353                  * the power domain will have taken care of resetting the SOR
3354                  * and we don't have to do anything.
3355                  */
3356                 sor->rst = NULL;
3357         }
3358
3359         sor->clk = devm_clk_get(&pdev->dev, NULL);
3360         if (IS_ERR(sor->clk)) {
3361                 err = PTR_ERR(sor->clk);
3362                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3363                 goto remove;
3364         }
3365
3366         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3367                 struct device_node *np = pdev->dev.of_node;
3368                 const char *name;
3369
3370                 /*
3371                  * For backwards compatibility with Tegra210 device trees,
3372                  * fall back to the old clock name "source" if the new "out"
3373                  * clock is not available.
3374                  */
3375                 if (of_property_match_string(np, "clock-names", "out") < 0)
3376                         name = "source";
3377                 else
3378                         name = "out";
3379
3380                 sor->clk_out = devm_clk_get(&pdev->dev, name);
3381                 if (IS_ERR(sor->clk_out)) {
3382                         err = PTR_ERR(sor->clk_out);
3383                         dev_err(sor->dev, "failed to get %s clock: %d\n",
3384                                 name, err);
3385                         goto remove;
3386                 }
3387         } else {
3388                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3389                 sor->clk_out = sor->clk;
3390         }
3391
3392         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3393         if (IS_ERR(sor->clk_parent)) {
3394                 err = PTR_ERR(sor->clk_parent);
3395                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3396                 goto remove;
3397         }
3398
3399         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3400         if (IS_ERR(sor->clk_safe)) {
3401                 err = PTR_ERR(sor->clk_safe);
3402                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3403                 goto remove;
3404         }
3405
3406         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3407         if (IS_ERR(sor->clk_dp)) {
3408                 err = PTR_ERR(sor->clk_dp);
3409                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3410                 goto remove;
3411         }
3412
3413         /*
3414          * Starting with Tegra186, the BPMP provides an implementation for
3415          * the pad output clock, so we have to look it up from device tree.
3416          */
3417         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3418         if (IS_ERR(sor->clk_pad)) {
3419                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3420                         err = PTR_ERR(sor->clk_pad);
3421                         goto remove;
3422                 }
3423
3424                 /*
3425                  * If the pad output clock is not available, then we assume
3426                  * we're on Tegra210 or earlier and have to provide our own
3427                  * implementation.
3428                  */
3429                 sor->clk_pad = NULL;
3430         }
3431
3432         /*
3433          * The bootloader may have set up the SOR such that it's module clock
3434          * is sourced by one of the display PLLs. However, that doesn't work
3435          * without properly having set up other bits of the SOR.
3436          */
3437         err = clk_set_parent(sor->clk_out, sor->clk_safe);
3438         if (err < 0) {
3439                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3440                 goto remove;
3441         }
3442
3443         platform_set_drvdata(pdev, sor);
3444         pm_runtime_enable(&pdev->dev);
3445
3446         /*
3447          * On Tegra210 and earlier, provide our own implementation for the
3448          * pad output clock.
3449          */
3450         if (!sor->clk_pad) {
3451                 err = pm_runtime_get_sync(&pdev->dev);
3452                 if (err < 0) {
3453                         dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
3454                                 err);
3455                         goto remove;
3456                 }
3457
3458                 sor->clk_pad = tegra_clk_sor_pad_register(sor,
3459                                                           "sor1_pad_clkout");
3460                 pm_runtime_put(&pdev->dev);
3461         }
3462
3463         if (IS_ERR(sor->clk_pad)) {
3464                 err = PTR_ERR(sor->clk_pad);
3465                 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
3466                         err);
3467                 goto remove;
3468         }
3469
3470         INIT_LIST_HEAD(&sor->client.list);
3471         sor->client.ops = &sor_client_ops;
3472         sor->client.dev = &pdev->dev;
3473
3474         err = host1x_client_register(&sor->client);
3475         if (err < 0) {
3476                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3477                         err);
3478                 goto remove;
3479         }
3480
3481         return 0;
3482
3483 remove:
3484         if (sor->ops && sor->ops->remove)
3485                 sor->ops->remove(sor);
3486 output:
3487         tegra_output_remove(&sor->output);
3488         return err;
3489 }
3490
3491 static int tegra_sor_remove(struct platform_device *pdev)
3492 {
3493         struct tegra_sor *sor = platform_get_drvdata(pdev);
3494         int err;
3495
3496         pm_runtime_disable(&pdev->dev);
3497
3498         err = host1x_client_unregister(&sor->client);
3499         if (err < 0) {
3500                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3501                         err);
3502                 return err;
3503         }
3504
3505         if (sor->ops && sor->ops->remove) {
3506                 err = sor->ops->remove(sor);
3507                 if (err < 0)
3508                         dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
3509         }
3510
3511         tegra_output_remove(&sor->output);
3512
3513         return 0;
3514 }
3515
3516 #ifdef CONFIG_PM
3517 static int tegra_sor_suspend(struct device *dev)
3518 {
3519         struct tegra_sor *sor = dev_get_drvdata(dev);
3520         int err;
3521
3522         if (sor->rst) {
3523                 err = reset_control_assert(sor->rst);
3524                 if (err < 0) {
3525                         dev_err(dev, "failed to assert reset: %d\n", err);
3526                         return err;
3527                 }
3528
3529                 reset_control_release(sor->rst);
3530         }
3531
3532         usleep_range(1000, 2000);
3533
3534         clk_disable_unprepare(sor->clk);
3535
3536         return 0;
3537 }
3538
3539 static int tegra_sor_resume(struct device *dev)
3540 {
3541         struct tegra_sor *sor = dev_get_drvdata(dev);
3542         int err;
3543
3544         err = clk_prepare_enable(sor->clk);
3545         if (err < 0) {
3546                 dev_err(dev, "failed to enable clock: %d\n", err);
3547                 return err;
3548         }
3549
3550         usleep_range(1000, 2000);
3551
3552         if (sor->rst) {
3553                 err = reset_control_acquire(sor->rst);
3554                 if (err < 0) {
3555                         dev_err(dev, "failed to acquire reset: %d\n", err);
3556                         clk_disable_unprepare(sor->clk);
3557                         return err;
3558                 }
3559
3560                 err = reset_control_deassert(sor->rst);
3561                 if (err < 0) {
3562                         dev_err(dev, "failed to deassert reset: %d\n", err);
3563                         reset_control_release(sor->rst);
3564                         clk_disable_unprepare(sor->clk);
3565                         return err;
3566                 }
3567         }
3568
3569         return 0;
3570 }
3571 #endif
3572
3573 static const struct dev_pm_ops tegra_sor_pm_ops = {
3574         SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
3575 };
3576
3577 struct platform_driver tegra_sor_driver = {
3578         .driver = {
3579                 .name = "tegra-sor",
3580                 .of_match_table = tegra_sor_of_match,
3581                 .pm = &tegra_sor_pm_ops,
3582         },
3583         .probe = tegra_sor_probe,
3584         .remove = tegra_sor_remove,
3585 };