2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/delay.h>
11 #include <linux/gpio.h>
12 #include <linux/interrupt.h>
14 #include <linux/of_gpio.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/pinctrl/pinctrl.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/platform_device.h>
19 #include <linux/reset.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/workqueue.h>
23 #include <drm/drm_dp_helper.h>
24 #include <drm/drm_panel.h>
30 static DEFINE_MUTEX(dpaux_lock);
31 static LIST_HEAD(dpaux_list);
34 struct drm_dp_aux aux;
40 struct tegra_output *output;
42 struct reset_control *rst;
43 struct clk *clk_parent;
46 struct regulator *vdd;
48 struct completion complete;
49 struct work_struct work;
50 struct list_head list;
52 #ifdef CONFIG_GENERIC_PINCONF
53 struct pinctrl_dev *pinctrl;
54 struct pinctrl_desc desc;
58 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
60 return container_of(aux, struct tegra_dpaux, aux);
63 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
65 return container_of(work, struct tegra_dpaux, work);
68 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
71 u32 value = readl(dpaux->regs + (offset << 2));
73 trace_dpaux_readl(dpaux->dev, offset, value);
78 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
79 u32 value, unsigned int offset)
81 trace_dpaux_writel(dpaux->dev, offset, value);
82 writel(value, dpaux->regs + (offset << 2));
85 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
90 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
91 size_t num = min_t(size_t, size - i * 4, 4);
94 for (j = 0; j < num; j++)
95 value |= buffer[i * 4 + j] << (j * 8);
97 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
101 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
106 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
107 size_t num = min_t(size_t, size - i * 4, 4);
110 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
112 for (j = 0; j < num; j++)
113 buffer[i * 4 + j] = value >> (j * 8);
117 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
118 struct drm_dp_aux_msg *msg)
120 unsigned long timeout = msecs_to_jiffies(250);
121 struct tegra_dpaux *dpaux = to_dpaux(aux);
122 unsigned long status;
126 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
131 * Allow zero-sized messages only for I2C, in which case they specify
132 * address-only transactions.
135 switch (msg->request & ~DP_AUX_I2C_MOT) {
136 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
137 case DP_AUX_I2C_WRITE:
138 case DP_AUX_I2C_READ:
139 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
146 /* For non-zero-sized messages, set the CMDLEN field. */
147 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
150 switch (msg->request & ~DP_AUX_I2C_MOT) {
151 case DP_AUX_I2C_WRITE:
152 if (msg->request & DP_AUX_I2C_MOT)
153 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
155 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
159 case DP_AUX_I2C_READ:
160 if (msg->request & DP_AUX_I2C_MOT)
161 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
163 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
167 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
168 if (msg->request & DP_AUX_I2C_MOT)
169 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
171 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
175 case DP_AUX_NATIVE_WRITE:
176 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
179 case DP_AUX_NATIVE_READ:
180 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
187 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
188 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
190 if ((msg->request & DP_AUX_I2C_READ) == 0) {
191 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
195 /* start transaction */
196 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
197 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
198 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
200 status = wait_for_completion_timeout(&dpaux->complete, timeout);
204 /* read status and clear errors */
205 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
206 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
208 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
211 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
212 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
213 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
216 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
218 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
222 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
226 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
230 msg->reply = DP_AUX_I2C_REPLY_NACK;
234 msg->reply = DP_AUX_I2C_REPLY_DEFER;
238 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
239 if (msg->request & DP_AUX_I2C_READ) {
240 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
242 if (WARN_ON(count != msg->size))
243 count = min_t(size_t, count, msg->size);
245 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
253 static void tegra_dpaux_hotplug(struct work_struct *work)
255 struct tegra_dpaux *dpaux = work_to_dpaux(work);
258 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
261 static irqreturn_t tegra_dpaux_irq(int irq, void *data)
263 struct tegra_dpaux *dpaux = data;
264 irqreturn_t ret = IRQ_HANDLED;
267 /* clear interrupts */
268 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
269 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
271 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
272 schedule_work(&dpaux->work);
274 if (value & DPAUX_INTR_IRQ_EVENT) {
275 /* TODO: handle this */
278 if (value & DPAUX_INTR_AUX_DONE)
279 complete(&dpaux->complete);
284 enum tegra_dpaux_functions {
285 DPAUX_PADCTL_FUNC_AUX,
286 DPAUX_PADCTL_FUNC_I2C,
287 DPAUX_PADCTL_FUNC_OFF,
290 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
292 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
294 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
296 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
299 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
301 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
303 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
305 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
308 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
313 case DPAUX_PADCTL_FUNC_AUX:
314 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
315 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
316 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
317 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
318 DPAUX_HYBRID_PADCTL_MODE_AUX;
321 case DPAUX_PADCTL_FUNC_I2C:
322 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
323 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
324 DPAUX_HYBRID_PADCTL_MODE_I2C;
327 case DPAUX_PADCTL_FUNC_OFF:
328 tegra_dpaux_pad_power_down(dpaux);
335 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
336 tegra_dpaux_pad_power_up(dpaux);
341 #ifdef CONFIG_GENERIC_PINCONF
342 static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
343 PINCTRL_PIN(0, "DP_AUX_CHx_P"),
344 PINCTRL_PIN(1, "DP_AUX_CHx_N"),
347 static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
349 static const char * const tegra_dpaux_groups[] = {
353 static const char * const tegra_dpaux_functions[] = {
359 static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
361 return ARRAY_SIZE(tegra_dpaux_groups);
364 static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
367 return tegra_dpaux_groups[group];
370 static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
371 unsigned group, const unsigned **pins,
374 *pins = tegra_dpaux_pin_numbers;
375 *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
380 static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
381 .get_groups_count = tegra_dpaux_get_groups_count,
382 .get_group_name = tegra_dpaux_get_group_name,
383 .get_group_pins = tegra_dpaux_get_group_pins,
384 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
385 .dt_free_map = pinconf_generic_dt_free_map,
388 static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
390 return ARRAY_SIZE(tegra_dpaux_functions);
393 static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
394 unsigned int function)
396 return tegra_dpaux_functions[function];
399 static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
400 unsigned int function,
401 const char * const **groups,
402 unsigned * const num_groups)
404 *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
405 *groups = tegra_dpaux_groups;
410 static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
411 unsigned int function, unsigned int group)
413 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
415 return tegra_dpaux_pad_config(dpaux, function);
418 static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
419 .get_functions_count = tegra_dpaux_get_functions_count,
420 .get_function_name = tegra_dpaux_get_function_name,
421 .get_function_groups = tegra_dpaux_get_function_groups,
422 .set_mux = tegra_dpaux_set_mux,
426 static int tegra_dpaux_probe(struct platform_device *pdev)
428 struct tegra_dpaux *dpaux;
429 struct resource *regs;
433 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
437 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
438 init_completion(&dpaux->complete);
439 INIT_LIST_HEAD(&dpaux->list);
440 dpaux->dev = &pdev->dev;
442 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
443 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
444 if (IS_ERR(dpaux->regs))
445 return PTR_ERR(dpaux->regs);
447 dpaux->irq = platform_get_irq(pdev, 0);
448 if (dpaux->irq < 0) {
449 dev_err(&pdev->dev, "failed to get IRQ\n");
453 if (!pdev->dev.pm_domain) {
454 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
455 if (IS_ERR(dpaux->rst)) {
457 "failed to get reset control: %ld\n",
458 PTR_ERR(dpaux->rst));
459 return PTR_ERR(dpaux->rst);
463 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
464 if (IS_ERR(dpaux->clk)) {
465 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
466 PTR_ERR(dpaux->clk));
467 return PTR_ERR(dpaux->clk);
470 err = clk_prepare_enable(dpaux->clk);
472 dev_err(&pdev->dev, "failed to enable module clock: %d\n",
478 reset_control_deassert(dpaux->rst);
480 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
481 if (IS_ERR(dpaux->clk_parent)) {
482 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
483 PTR_ERR(dpaux->clk_parent));
484 err = PTR_ERR(dpaux->clk_parent);
488 err = clk_prepare_enable(dpaux->clk_parent);
490 dev_err(&pdev->dev, "failed to enable parent clock: %d\n",
495 err = clk_set_rate(dpaux->clk_parent, 270000000);
497 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
499 goto disable_parent_clk;
502 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
503 if (IS_ERR(dpaux->vdd)) {
504 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
505 PTR_ERR(dpaux->vdd));
506 err = PTR_ERR(dpaux->vdd);
507 goto disable_parent_clk;
510 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
511 dev_name(dpaux->dev), dpaux);
513 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
515 goto disable_parent_clk;
518 disable_irq(dpaux->irq);
520 dpaux->aux.transfer = tegra_dpaux_transfer;
521 dpaux->aux.dev = &pdev->dev;
523 err = drm_dp_aux_register(&dpaux->aux);
525 goto disable_parent_clk;
528 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
529 * so power them up and configure them in I2C mode.
531 * The DPAUX code paths reconfigure the pads in AUX mode, but there
532 * is no possibility to perform the I2C mode configuration in the
535 err = tegra_dpaux_pad_config(dpaux, DPAUX_HYBRID_PADCTL_MODE_I2C);
539 #ifdef CONFIG_GENERIC_PINCONF
540 dpaux->desc.name = dev_name(&pdev->dev);
541 dpaux->desc.pins = tegra_dpaux_pins;
542 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
543 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
544 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
545 dpaux->desc.owner = THIS_MODULE;
547 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
548 if (IS_ERR(dpaux->pinctrl)) {
549 dev_err(&pdev->dev, "failed to register pincontrol\n");
550 return PTR_ERR(dpaux->pinctrl);
553 /* enable and clear all interrupts */
554 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
555 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
556 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
557 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
559 mutex_lock(&dpaux_lock);
560 list_add_tail(&dpaux->list, &dpaux_list);
561 mutex_unlock(&dpaux_lock);
563 platform_set_drvdata(pdev, dpaux);
568 clk_disable_unprepare(dpaux->clk_parent);
571 reset_control_assert(dpaux->rst);
573 clk_disable_unprepare(dpaux->clk);
578 static int tegra_dpaux_remove(struct platform_device *pdev)
580 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
582 /* make sure pads are powered down when not in use */
583 tegra_dpaux_pad_power_down(dpaux);
585 drm_dp_aux_unregister(&dpaux->aux);
587 mutex_lock(&dpaux_lock);
588 list_del(&dpaux->list);
589 mutex_unlock(&dpaux_lock);
591 cancel_work_sync(&dpaux->work);
593 clk_disable_unprepare(dpaux->clk_parent);
596 reset_control_assert(dpaux->rst);
598 clk_disable_unprepare(dpaux->clk);
603 static const struct of_device_id tegra_dpaux_of_match[] = {
604 { .compatible = "nvidia,tegra210-dpaux", },
605 { .compatible = "nvidia,tegra124-dpaux", },
608 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
610 struct platform_driver tegra_dpaux_driver = {
612 .name = "tegra-dpaux",
613 .of_match_table = tegra_dpaux_of_match,
615 .probe = tegra_dpaux_probe,
616 .remove = tegra_dpaux_remove,
619 struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
621 struct tegra_dpaux *dpaux;
623 mutex_lock(&dpaux_lock);
625 list_for_each_entry(dpaux, &dpaux_list, list)
626 if (np == dpaux->dev->of_node) {
627 mutex_unlock(&dpaux_lock);
631 mutex_unlock(&dpaux_lock);
636 int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
638 struct tegra_dpaux *dpaux = to_dpaux(aux);
639 unsigned long timeout;
642 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
643 dpaux->output = output;
645 err = regulator_enable(dpaux->vdd);
649 timeout = jiffies + msecs_to_jiffies(250);
651 while (time_before(jiffies, timeout)) {
652 enum drm_connector_status status;
654 status = drm_dp_aux_detect(aux);
655 if (status == connector_status_connected) {
656 enable_irq(dpaux->irq);
660 usleep_range(1000, 2000);
666 int drm_dp_aux_detach(struct drm_dp_aux *aux)
668 struct tegra_dpaux *dpaux = to_dpaux(aux);
669 unsigned long timeout;
672 disable_irq(dpaux->irq);
674 err = regulator_disable(dpaux->vdd);
678 timeout = jiffies + msecs_to_jiffies(250);
680 while (time_before(jiffies, timeout)) {
681 enum drm_connector_status status;
683 status = drm_dp_aux_detect(aux);
684 if (status == connector_status_disconnected) {
685 dpaux->output = NULL;
689 usleep_range(1000, 2000);
695 enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
697 struct tegra_dpaux *dpaux = to_dpaux(aux);
700 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
702 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
703 return connector_status_connected;
705 return connector_status_disconnected;
708 int drm_dp_aux_enable(struct drm_dp_aux *aux)
710 struct tegra_dpaux *dpaux = to_dpaux(aux);
712 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
715 int drm_dp_aux_disable(struct drm_dp_aux *aux)
717 struct tegra_dpaux *dpaux = to_dpaux(aux);
719 tegra_dpaux_pad_power_down(dpaux);
724 int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
728 err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
736 int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
739 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
740 u8 status[DP_LINK_STATUS_SIZE], values[4];
744 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
748 if (tp == DP_TRAINING_PATTERN_DISABLE)
751 for (i = 0; i < link->num_lanes; i++)
752 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
753 DP_TRAIN_PRE_EMPH_LEVEL_0 |
754 DP_TRAIN_MAX_SWING_REACHED |
755 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
757 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
762 usleep_range(500, 1000);
764 err = drm_dp_dpcd_read_link_status(aux, status);
769 case DP_TRAINING_PATTERN_1:
770 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
775 case DP_TRAINING_PATTERN_2:
776 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
782 dev_err(aux->dev, "unsupported training pattern %u\n", tp);
786 err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);