1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
5 * Based on sun4i_backend.c, which is:
6 * Copyright (C) 2015 Free Electrons
7 * Copyright (C) 2015 NextThing Co
10 #include <linux/component.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/reset.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_fb_cma_helper.h>
20 #include <drm/drm_gem_cma_helper.h>
21 #include <drm/drm_plane_helper.h>
22 #include <drm/drm_probe_helper.h>
24 #include "sun4i_drv.h"
25 #include "sun8i_mixer.h"
26 #include "sun8i_ui_layer.h"
27 #include "sun8i_vi_layer.h"
28 #include "sunxi_engine.h"
30 static const struct de2_fmt_info de2_formats[] = {
32 .drm_fmt = DRM_FORMAT_ARGB8888,
33 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB8888,
35 .csc = SUN8I_CSC_MODE_OFF,
38 .drm_fmt = DRM_FORMAT_ABGR8888,
39 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR8888,
41 .csc = SUN8I_CSC_MODE_OFF,
44 .drm_fmt = DRM_FORMAT_RGBA8888,
45 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA8888,
47 .csc = SUN8I_CSC_MODE_OFF,
50 .drm_fmt = DRM_FORMAT_BGRA8888,
51 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA8888,
53 .csc = SUN8I_CSC_MODE_OFF,
56 .drm_fmt = DRM_FORMAT_XRGB8888,
57 .de2_fmt = SUN8I_MIXER_FBFMT_XRGB8888,
59 .csc = SUN8I_CSC_MODE_OFF,
62 .drm_fmt = DRM_FORMAT_XBGR8888,
63 .de2_fmt = SUN8I_MIXER_FBFMT_XBGR8888,
65 .csc = SUN8I_CSC_MODE_OFF,
68 .drm_fmt = DRM_FORMAT_RGBX8888,
69 .de2_fmt = SUN8I_MIXER_FBFMT_RGBX8888,
71 .csc = SUN8I_CSC_MODE_OFF,
74 .drm_fmt = DRM_FORMAT_BGRX8888,
75 .de2_fmt = SUN8I_MIXER_FBFMT_BGRX8888,
77 .csc = SUN8I_CSC_MODE_OFF,
80 .drm_fmt = DRM_FORMAT_RGB888,
81 .de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
83 .csc = SUN8I_CSC_MODE_OFF,
86 .drm_fmt = DRM_FORMAT_BGR888,
87 .de2_fmt = SUN8I_MIXER_FBFMT_BGR888,
89 .csc = SUN8I_CSC_MODE_OFF,
92 .drm_fmt = DRM_FORMAT_RGB565,
93 .de2_fmt = SUN8I_MIXER_FBFMT_RGB565,
95 .csc = SUN8I_CSC_MODE_OFF,
98 .drm_fmt = DRM_FORMAT_BGR565,
99 .de2_fmt = SUN8I_MIXER_FBFMT_BGR565,
101 .csc = SUN8I_CSC_MODE_OFF,
104 .drm_fmt = DRM_FORMAT_ARGB4444,
105 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
107 .csc = SUN8I_CSC_MODE_OFF,
110 /* for DE2 VI layer which ignores alpha */
111 .drm_fmt = DRM_FORMAT_XRGB4444,
112 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
114 .csc = SUN8I_CSC_MODE_OFF,
117 .drm_fmt = DRM_FORMAT_ABGR4444,
118 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
120 .csc = SUN8I_CSC_MODE_OFF,
123 /* for DE2 VI layer which ignores alpha */
124 .drm_fmt = DRM_FORMAT_XBGR4444,
125 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
127 .csc = SUN8I_CSC_MODE_OFF,
130 .drm_fmt = DRM_FORMAT_RGBA4444,
131 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
133 .csc = SUN8I_CSC_MODE_OFF,
136 /* for DE2 VI layer which ignores alpha */
137 .drm_fmt = DRM_FORMAT_RGBX4444,
138 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
140 .csc = SUN8I_CSC_MODE_OFF,
143 .drm_fmt = DRM_FORMAT_BGRA4444,
144 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
146 .csc = SUN8I_CSC_MODE_OFF,
149 /* for DE2 VI layer which ignores alpha */
150 .drm_fmt = DRM_FORMAT_BGRX4444,
151 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
153 .csc = SUN8I_CSC_MODE_OFF,
156 .drm_fmt = DRM_FORMAT_ARGB1555,
157 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
159 .csc = SUN8I_CSC_MODE_OFF,
162 /* for DE2 VI layer which ignores alpha */
163 .drm_fmt = DRM_FORMAT_XRGB1555,
164 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
166 .csc = SUN8I_CSC_MODE_OFF,
169 .drm_fmt = DRM_FORMAT_ABGR1555,
170 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
172 .csc = SUN8I_CSC_MODE_OFF,
175 /* for DE2 VI layer which ignores alpha */
176 .drm_fmt = DRM_FORMAT_XBGR1555,
177 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
179 .csc = SUN8I_CSC_MODE_OFF,
182 .drm_fmt = DRM_FORMAT_RGBA5551,
183 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
185 .csc = SUN8I_CSC_MODE_OFF,
188 /* for DE2 VI layer which ignores alpha */
189 .drm_fmt = DRM_FORMAT_RGBX5551,
190 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
192 .csc = SUN8I_CSC_MODE_OFF,
195 .drm_fmt = DRM_FORMAT_BGRA5551,
196 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
198 .csc = SUN8I_CSC_MODE_OFF,
201 /* for DE2 VI layer which ignores alpha */
202 .drm_fmt = DRM_FORMAT_BGRX5551,
203 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
205 .csc = SUN8I_CSC_MODE_OFF,
208 .drm_fmt = DRM_FORMAT_ARGB2101010,
209 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB2101010,
211 .csc = SUN8I_CSC_MODE_OFF,
214 .drm_fmt = DRM_FORMAT_ABGR2101010,
215 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR2101010,
217 .csc = SUN8I_CSC_MODE_OFF,
220 .drm_fmt = DRM_FORMAT_RGBA1010102,
221 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA1010102,
223 .csc = SUN8I_CSC_MODE_OFF,
226 .drm_fmt = DRM_FORMAT_BGRA1010102,
227 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA1010102,
229 .csc = SUN8I_CSC_MODE_OFF,
232 .drm_fmt = DRM_FORMAT_UYVY,
233 .de2_fmt = SUN8I_MIXER_FBFMT_UYVY,
235 .csc = SUN8I_CSC_MODE_YUV2RGB,
238 .drm_fmt = DRM_FORMAT_VYUY,
239 .de2_fmt = SUN8I_MIXER_FBFMT_VYUY,
241 .csc = SUN8I_CSC_MODE_YUV2RGB,
244 .drm_fmt = DRM_FORMAT_YUYV,
245 .de2_fmt = SUN8I_MIXER_FBFMT_YUYV,
247 .csc = SUN8I_CSC_MODE_YUV2RGB,
250 .drm_fmt = DRM_FORMAT_YVYU,
251 .de2_fmt = SUN8I_MIXER_FBFMT_YVYU,
253 .csc = SUN8I_CSC_MODE_YUV2RGB,
256 .drm_fmt = DRM_FORMAT_NV16,
257 .de2_fmt = SUN8I_MIXER_FBFMT_NV16,
259 .csc = SUN8I_CSC_MODE_YUV2RGB,
262 .drm_fmt = DRM_FORMAT_NV61,
263 .de2_fmt = SUN8I_MIXER_FBFMT_NV61,
265 .csc = SUN8I_CSC_MODE_YUV2RGB,
268 .drm_fmt = DRM_FORMAT_NV12,
269 .de2_fmt = SUN8I_MIXER_FBFMT_NV12,
271 .csc = SUN8I_CSC_MODE_YUV2RGB,
274 .drm_fmt = DRM_FORMAT_NV21,
275 .de2_fmt = SUN8I_MIXER_FBFMT_NV21,
277 .csc = SUN8I_CSC_MODE_YUV2RGB,
280 .drm_fmt = DRM_FORMAT_YUV422,
281 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
283 .csc = SUN8I_CSC_MODE_YUV2RGB,
286 .drm_fmt = DRM_FORMAT_YUV420,
287 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
289 .csc = SUN8I_CSC_MODE_YUV2RGB,
292 .drm_fmt = DRM_FORMAT_YUV411,
293 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
295 .csc = SUN8I_CSC_MODE_YUV2RGB,
298 .drm_fmt = DRM_FORMAT_YVU422,
299 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
301 .csc = SUN8I_CSC_MODE_YVU2RGB,
304 .drm_fmt = DRM_FORMAT_YVU420,
305 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
307 .csc = SUN8I_CSC_MODE_YVU2RGB,
310 .drm_fmt = DRM_FORMAT_YVU411,
311 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
313 .csc = SUN8I_CSC_MODE_YVU2RGB,
316 .drm_fmt = DRM_FORMAT_P010,
317 .de2_fmt = SUN8I_MIXER_FBFMT_P010_YUV,
319 .csc = SUN8I_CSC_MODE_YUV2RGB,
322 .drm_fmt = DRM_FORMAT_P210,
323 .de2_fmt = SUN8I_MIXER_FBFMT_P210_YUV,
325 .csc = SUN8I_CSC_MODE_YUV2RGB,
329 const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)
333 for (i = 0; i < ARRAY_SIZE(de2_formats); ++i)
334 if (de2_formats[i].drm_fmt == format)
335 return &de2_formats[i];
340 static void sun8i_mixer_commit(struct sunxi_engine *engine)
342 DRM_DEBUG_DRIVER("Committing changes\n");
344 regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
345 SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
348 static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
349 struct sunxi_engine *engine)
351 struct drm_plane **planes;
352 struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
355 planes = devm_kcalloc(drm->dev,
356 mixer->cfg->vi_num + mixer->cfg->ui_num + 1,
357 sizeof(*planes), GFP_KERNEL);
359 return ERR_PTR(-ENOMEM);
361 for (i = 0; i < mixer->cfg->vi_num; i++) {
362 struct sun8i_vi_layer *layer;
364 layer = sun8i_vi_layer_init_one(drm, mixer, i);
367 "Couldn't initialize overlay plane\n");
368 return ERR_CAST(layer);
371 planes[i] = &layer->plane;
374 for (i = 0; i < mixer->cfg->ui_num; i++) {
375 struct sun8i_ui_layer *layer;
377 layer = sun8i_ui_layer_init_one(drm, mixer, i);
379 dev_err(drm->dev, "Couldn't initialize %s plane\n",
380 i ? "overlay" : "primary");
381 return ERR_CAST(layer);
384 planes[mixer->cfg->vi_num + i] = &layer->plane;
390 static const struct sunxi_engine_ops sun8i_engine_ops = {
391 .commit = sun8i_mixer_commit,
392 .layers_init = sun8i_layers_init,
395 static struct regmap_config sun8i_mixer_regmap_config = {
399 .max_register = 0xbfffc, /* guessed */
402 static int sun8i_mixer_of_get_id(struct device_node *node)
404 struct device_node *ep, *remote;
405 struct of_endpoint of_ep;
407 /* Output port is 1, and we want the first endpoint. */
408 ep = of_graph_get_endpoint_by_regs(node, 1, -1);
412 remote = of_graph_get_remote_endpoint(ep);
417 of_graph_parse_endpoint(remote, &of_ep);
422 static int sun8i_mixer_bind(struct device *dev, struct device *master,
425 struct platform_device *pdev = to_platform_device(dev);
426 struct drm_device *drm = data;
427 struct sun4i_drv *drv = drm->dev_private;
428 struct sun8i_mixer *mixer;
429 struct resource *res;
436 * The mixer uses single 32-bit register to store memory
437 * addresses, so that it cannot deal with 64-bit memory
439 * Restrict the DMA mask so that the mixer won't be
440 * allocated some memory that is too high.
442 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
444 dev_err(dev, "Cannot do 32-bit DMA.\n");
448 mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
451 dev_set_drvdata(dev, mixer);
452 mixer->engine.ops = &sun8i_engine_ops;
453 mixer->engine.node = dev->of_node;
456 * While this function can fail, we shouldn't do anything
457 * if this happens. Some early DE2 DT entries don't provide
458 * mixer id but work nevertheless because matching between
459 * TCON and mixer is done by comparing node pointers (old
460 * way) instead comparing ids. If this function fails and
461 * id is needed, it will fail during id matching anyway.
463 mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node);
465 mixer->cfg = of_device_get_match_data(dev);
469 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
470 regs = devm_ioremap_resource(dev, res);
472 return PTR_ERR(regs);
474 mixer->engine.regs = devm_regmap_init_mmio(dev, regs,
475 &sun8i_mixer_regmap_config);
476 if (IS_ERR(mixer->engine.regs)) {
477 dev_err(dev, "Couldn't create the mixer regmap\n");
478 return PTR_ERR(mixer->engine.regs);
481 mixer->reset = devm_reset_control_get(dev, NULL);
482 if (IS_ERR(mixer->reset)) {
483 dev_err(dev, "Couldn't get our reset line\n");
484 return PTR_ERR(mixer->reset);
487 ret = reset_control_deassert(mixer->reset);
489 dev_err(dev, "Couldn't deassert our reset line\n");
493 mixer->bus_clk = devm_clk_get(dev, "bus");
494 if (IS_ERR(mixer->bus_clk)) {
495 dev_err(dev, "Couldn't get the mixer bus clock\n");
496 ret = PTR_ERR(mixer->bus_clk);
497 goto err_assert_reset;
499 clk_prepare_enable(mixer->bus_clk);
501 mixer->mod_clk = devm_clk_get(dev, "mod");
502 if (IS_ERR(mixer->mod_clk)) {
503 dev_err(dev, "Couldn't get the mixer module clock\n");
504 ret = PTR_ERR(mixer->mod_clk);
505 goto err_disable_bus_clk;
509 * It seems that we need to enforce that rate for whatever
510 * reason for the mixer to be functional. Make sure it's the
513 if (mixer->cfg->mod_rate)
514 clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate);
516 clk_prepare_enable(mixer->mod_clk);
518 list_add_tail(&mixer->engine.list, &drv->engine_list);
520 base = sun8i_blender_base(mixer);
522 /* Reset registers and disable unused sub-engines */
523 if (mixer->cfg->is_de3) {
524 for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
525 regmap_write(mixer->engine.regs, i, 0);
527 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCE_EN, 0);
528 regmap_write(mixer->engine.regs, SUN50I_MIXER_PEAK_EN, 0);
529 regmap_write(mixer->engine.regs, SUN50I_MIXER_LCTI_EN, 0);
530 regmap_write(mixer->engine.regs, SUN50I_MIXER_BLS_EN, 0);
531 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCC_EN, 0);
532 regmap_write(mixer->engine.regs, SUN50I_MIXER_DNS_EN, 0);
533 regmap_write(mixer->engine.regs, SUN50I_MIXER_DRC_EN, 0);
534 regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0);
535 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0);
536 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0);
538 for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
539 regmap_write(mixer->engine.regs, i, 0);
541 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0);
542 regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0);
543 regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0);
544 regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0);
545 regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0);
546 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0);
547 regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0);
550 /* Enable the mixer */
551 regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
552 SUN8I_MIXER_GLOBAL_CTL_RT_EN);
554 /* Set background color to black */
555 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
556 SUN8I_MIXER_BLEND_COLOR_BLACK);
559 * Set fill color of bottom plane to black. Generally not needed
560 * except when VI plane is at bottom (zpos = 0) and enabled.
562 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
563 SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
564 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
565 SUN8I_MIXER_BLEND_COLOR_BLACK);
567 plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
568 for (i = 0; i < plane_cnt; i++)
569 regmap_write(mixer->engine.regs,
570 SUN8I_MIXER_BLEND_MODE(base, i),
571 SUN8I_MIXER_BLEND_MODE_DEF);
573 regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
574 SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
579 clk_disable_unprepare(mixer->bus_clk);
581 reset_control_assert(mixer->reset);
585 static void sun8i_mixer_unbind(struct device *dev, struct device *master,
588 struct sun8i_mixer *mixer = dev_get_drvdata(dev);
590 list_del(&mixer->engine.list);
592 clk_disable_unprepare(mixer->mod_clk);
593 clk_disable_unprepare(mixer->bus_clk);
594 reset_control_assert(mixer->reset);
597 static const struct component_ops sun8i_mixer_ops = {
598 .bind = sun8i_mixer_bind,
599 .unbind = sun8i_mixer_unbind,
602 static int sun8i_mixer_probe(struct platform_device *pdev)
604 return component_add(&pdev->dev, &sun8i_mixer_ops);
607 static int sun8i_mixer_remove(struct platform_device *pdev)
609 component_del(&pdev->dev, &sun8i_mixer_ops);
614 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
617 .scanline_yuv = 2048,
622 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
625 .scanline_yuv = 2048,
630 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
632 .mod_rate = 432000000,
634 .scanline_yuv = 2048,
639 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
641 .mod_rate = 297000000,
643 .scanline_yuv = 2048,
648 static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
650 .mod_rate = 297000000,
652 .scanline_yuv = 2048,
657 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
661 .scanline_yuv = 2048,
663 .mod_rate = 150000000,
666 static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
668 .mod_rate = 297000000,
670 .scanline_yuv = 4096,
675 static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
677 .mod_rate = 297000000,
679 .scanline_yuv = 2048,
684 static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
687 .mod_rate = 600000000,
689 .scanline_yuv = 4096,
694 static const struct of_device_id sun8i_mixer_of_table[] = {
696 .compatible = "allwinner,sun8i-a83t-de2-mixer-0",
697 .data = &sun8i_a83t_mixer0_cfg,
700 .compatible = "allwinner,sun8i-a83t-de2-mixer-1",
701 .data = &sun8i_a83t_mixer1_cfg,
704 .compatible = "allwinner,sun8i-h3-de2-mixer-0",
705 .data = &sun8i_h3_mixer0_cfg,
708 .compatible = "allwinner,sun8i-r40-de2-mixer-0",
709 .data = &sun8i_r40_mixer0_cfg,
712 .compatible = "allwinner,sun8i-r40-de2-mixer-1",
713 .data = &sun8i_r40_mixer1_cfg,
716 .compatible = "allwinner,sun8i-v3s-de2-mixer",
717 .data = &sun8i_v3s_mixer_cfg,
720 .compatible = "allwinner,sun50i-a64-de2-mixer-0",
721 .data = &sun50i_a64_mixer0_cfg,
724 .compatible = "allwinner,sun50i-a64-de2-mixer-1",
725 .data = &sun50i_a64_mixer1_cfg,
728 .compatible = "allwinner,sun50i-h6-de3-mixer-0",
729 .data = &sun50i_h6_mixer0_cfg,
733 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
735 static struct platform_driver sun8i_mixer_platform_driver = {
736 .probe = sun8i_mixer_probe,
737 .remove = sun8i_mixer_remove,
739 .name = "sun8i-mixer",
740 .of_match_table = sun8i_mixer_of_table,
743 module_platform_driver(sun8i_mixer_platform_driver);
745 MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
746 MODULE_DESCRIPTION("Allwinner DE2 Mixer driver");
747 MODULE_LICENSE("GPL");