drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2016 Maxime Ripard
   4  *
   5  * Maxime Ripard <maxime.ripard@free-electrons.com>
   6  */
   7
   8 #include <drm/drmP.h>
   9 #include <drm/drm_atomic_helper.h>
  10 #include <drm/drm_probe_helper.h>
  11 #include <drm/drm_edid.h>
  12 #include <drm/drm_encoder.h>
  13 #include <drm/drm_of.h>
  14 #include <drm/drm_panel.h>
  15
  16 #include <linux/clk.h>
  17 #include <linux/component.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset.h>
  24
  25 #include "sun4i_backend.h"
  26 #include "sun4i_crtc.h"
  27 #include "sun4i_drv.h"
  28 #include "sun4i_hdmi.h"
  29
  30 static inline struct sun4i_hdmi *
  31 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
  32 {
  33         return container_of(encoder, struct sun4i_hdmi,
  34                             encoder);
  35 }
  36
  37 static inline struct sun4i_hdmi *
  38 drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
  39 {
  40         return container_of(connector, struct sun4i_hdmi,
  41                             connector);
  42 }
  43
  44 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
  45                                            struct drm_display_mode *mode)
  46 {
  47         struct hdmi_avi_infoframe frame;
  48         u8 buffer[17];
  49         int i, ret;
  50
  51         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
  52                                                        &hdmi->connector, mode);
  53         if (ret < 0) {
  54                 DRM_ERROR("Failed to get infoframes from mode\n");
  55                 return ret;
  56         }
  57
  58         ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  59         if (ret < 0) {
  60                 DRM_ERROR("Failed to pack infoframes\n");
  61                 return ret;
  62         }
  63
  64         for (i = 0; i < sizeof(buffer); i++)
  65                 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
  66
  67         return 0;
  68 }
  69
  70 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
  71                                    struct drm_crtc_state *crtc_state,
  72                                    struct drm_connector_state *conn_state)
  73 {
  74         struct drm_display_mode *mode = &crtc_state->mode;
  75
  76         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  77                 return -EINVAL;
  78
  79         return 0;
  80 }
  81
  82 static void sun4i_hdmi_disable(struct drm_encoder *encoder)
  83 {
  84         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
  85         u32 val;
  86
  87         DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
  88
  89         val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
  90         val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
  91         writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
  92
  93         clk_disable_unprepare(hdmi->tmds_clk);
  94 }
  95
  96 static void sun4i_hdmi_enable(struct drm_encoder *encoder)
  97 {
  98         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
  99         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
 100         u32 val = 0;
 101
 102         DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
 103
 104         clk_prepare_enable(hdmi->tmds_clk);
 105
 106         sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
 107         val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
 108         val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
 109         writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
 110
 111         val = SUN4I_HDMI_VID_CTRL_ENABLE;
 112         if (hdmi->hdmi_monitor)
 113                 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
 114
 115         writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
 116 }
 117
 118 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
 119                                 struct drm_display_mode *mode,
 120                                 struct drm_display_mode *adjusted_mode)
 121 {
 122         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
 123         unsigned int x, y;
 124         u32 val;
 125
 126         clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
 127         clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
 128
 129         /* Set input sync enable */
 130         writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
 131                hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
 132
 133         /*
 134          * Setup output pad (?) controls
 135          *
 136          * This is done here instead of at probe/bind time because
 137          * the controller seems to toggle some of the bits on its own.
 138          *
 139          * We can't just initialize the register there, we need to
 140          * protect the clock bits that have already been read out and
 141          * cached by the clock framework.
 142          */
 143         val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
 144         val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
 145         val |= hdmi->variant->pad_ctrl1_init_val;
 146         writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
 147         val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
 148
 149         /* Setup timing registers */
 150         writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
 151                SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
 152                hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
 153
 154         x = mode->htotal - mode->hsync_start;
 155         y = mode->vtotal - mode->vsync_start;
 156         writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
 157                hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
 158
 159         x = mode->hsync_start - mode->hdisplay;
 160         y = mode->vsync_start - mode->vdisplay;
 161         writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
 162                hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
 163
 164         x = mode->hsync_end - mode->hsync_start;
 165         y = mode->vsync_end - mode->vsync_start;
 166         writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
 167                hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
 168
 169         val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
 170         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 171                 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
 172
 173         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 174                 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
 175
 176         writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
 177 }
 178
 179 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder,
 180                                         const struct drm_display_mode *mode)
 181 {
 182         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
 183         unsigned long rate = mode->clock * 1000;
 184         unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */
 185         long rounded_rate;
 186
 187         /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */
 188         if (rate > 165000000)
 189                 return MODE_CLOCK_HIGH;
 190         rounded_rate = clk_round_rate(hdmi->tmds_clk, rate);
 191         if (rounded_rate > 0 &&
 192             max_t(unsigned long, rounded_rate, rate) -
 193             min_t(unsigned long, rounded_rate, rate) < diff)
 194                 return MODE_OK;
 195         return MODE_NOCLOCK;
 196 }
 197
 198 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
 199         .atomic_check   = sun4i_hdmi_atomic_check,
 200         .disable        = sun4i_hdmi_disable,
 201         .enable         = sun4i_hdmi_enable,
 202         .mode_set       = sun4i_hdmi_mode_set,
 203         .mode_valid     = sun4i_hdmi_mode_valid,
 204 };
 205
 206 static const struct drm_encoder_funcs sun4i_hdmi_funcs = {
 207         .destroy        = drm_encoder_cleanup,
 208 };
 209
 210 static int sun4i_hdmi_get_modes(struct drm_connector *connector)
 211 {
 212         struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
 213         struct edid *edid;
 214         int ret;
 215
 216         edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c);
 217         if (!edid)
 218                 return 0;
 219
 220         hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 221         DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
 222                          hdmi->hdmi_monitor ? "an HDMI" : "a DVI");
 223
 224         drm_connector_update_edid_property(connector, edid);
 225         cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
 226         ret = drm_add_edid_modes(connector, edid);
 227         kfree(edid);
 228
 229         return ret;
 230 }
 231
 232 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev)
 233 {
 234         struct device_node *phandle, *remote;
 235         struct i2c_adapter *ddc;
 236
 237         remote = of_graph_get_remote_node(dev->of_node, 1, -1);
 238         if (!remote)
 239                 return ERR_PTR(-EINVAL);
 240
 241         phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0);
 242         of_node_put(remote);
 243         if (!phandle)
 244                 return ERR_PTR(-ENODEV);
 245
 246         ddc = of_get_i2c_adapter_by_node(phandle);
 247         of_node_put(phandle);
 248         if (!ddc)
 249                 return ERR_PTR(-EPROBE_DEFER);
 250
 251         return ddc;
 252 }
 253
 254 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
 255         .get_modes      = sun4i_hdmi_get_modes,
 256 };
 257
 258 static enum drm_connector_status
 259 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
 260 {
 261         struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
 262         unsigned long reg;
 263
 264         if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg,
 265                                reg & SUN4I_HDMI_HPD_HIGH,
 266                                0, 500000)) {
 267                 cec_phys_addr_invalidate(hdmi->cec_adap);
 268                 return connector_status_disconnected;
 269         }
 270
 271         return connector_status_connected;
 272 }
 273
 274 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
 275         .detect                 = sun4i_hdmi_connector_detect,
 276         .fill_modes             = drm_helper_probe_single_connector_modes,
 277         .destroy                = drm_connector_cleanup,
 278         .reset                  = drm_atomic_helper_connector_reset,
 279         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 280         .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
 281 };
 282
 283 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
 284 static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
 285 {
 286         struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
 287
 288         return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
 289 }
 290
 291 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
 292 {
 293         struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
 294
 295         /* Start driving the CEC pin low */
 296         writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
 297 }
 298
 299 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
 300 {
 301         struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
 302
 303         /*
 304          * Stop driving the CEC pin, the pull up will take over
 305          * unless another CEC device is driving the pin low.
 306          */
 307         writel(0, hdmi->base + SUN4I_HDMI_CEC);
 308 }
 309
 310 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
 311         .read = sun4i_hdmi_cec_pin_read,
 312         .low = sun4i_hdmi_cec_pin_low,
 313         .high = sun4i_hdmi_cec_pin_high,
 314 };
 315 #endif
 316
 317 #define SUN4I_HDMI_PAD_CTRL1_MASK       (GENMASK(24, 7) | GENMASK(5, 0))
 318 #define SUN4I_HDMI_PLL_CTRL_MASK        (GENMASK(31, 8) | GENMASK(3, 0))
 319
 320 /* Only difference from sun5i is AMP is 4 instead of 6 */
 321 static const struct sun4i_hdmi_variant sun4i_variant = {
 322         .pad_ctrl0_init_val     = SUN4I_HDMI_PAD_CTRL0_TXEN |
 323                                   SUN4I_HDMI_PAD_CTRL0_CKEN |
 324                                   SUN4I_HDMI_PAD_CTRL0_PWENG |
 325                                   SUN4I_HDMI_PAD_CTRL0_PWEND |
 326                                   SUN4I_HDMI_PAD_CTRL0_PWENC |
 327                                   SUN4I_HDMI_PAD_CTRL0_LDODEN |
 328                                   SUN4I_HDMI_PAD_CTRL0_LDOCEN |
 329                                   SUN4I_HDMI_PAD_CTRL0_BIASEN,
 330         .pad_ctrl1_init_val     = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) |
 331                                   SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
 332                                   SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
 333                                   SUN4I_HDMI_PAD_CTRL1_REG_DEN |
 334                                   SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
 335                                   SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
 336                                   SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
 337                                   SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
 338         .pll_ctrl_init_val      = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
 339                                   SUN4I_HDMI_PLL_CTRL_CS(7) |
 340                                   SUN4I_HDMI_PLL_CTRL_CP_S(15) |
 341                                   SUN4I_HDMI_PLL_CTRL_S(7) |
 342                                   SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
 343                                   SUN4I_HDMI_PLL_CTRL_SDIV2 |
 344                                   SUN4I_HDMI_PLL_CTRL_LDO2_EN |
 345                                   SUN4I_HDMI_PLL_CTRL_LDO1_EN |
 346                                   SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
 347                                   SUN4I_HDMI_PLL_CTRL_BWS |
 348                                   SUN4I_HDMI_PLL_CTRL_PLL_EN,
 349
 350         .ddc_clk_reg            = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
 351         .ddc_clk_pre_divider    = 2,
 352         .ddc_clk_m_offset       = 1,
 353
 354         .field_ddc_en           = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
 355         .field_ddc_start        = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
 356         .field_ddc_reset        = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
 357         .field_ddc_addr_reg     = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
 358         .field_ddc_slave_addr   = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
 359         .field_ddc_int_status   = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
 360         .field_ddc_fifo_clear   = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
 361         .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
 362         .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
 363         .field_ddc_byte_count   = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
 364         .field_ddc_cmd          = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
 365         .field_ddc_sda_en       = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
 366         .field_ddc_sck_en       = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
 367
 368         .ddc_fifo_reg           = SUN4I_HDMI_DDC_FIFO_DATA_REG,
 369         .ddc_fifo_has_dir       = true,
 370 };
 371
 372 static const struct sun4i_hdmi_variant sun5i_variant = {
 373         .pad_ctrl0_init_val     = SUN4I_HDMI_PAD_CTRL0_TXEN |
 374                                   SUN4I_HDMI_PAD_CTRL0_CKEN |
 375                                   SUN4I_HDMI_PAD_CTRL0_PWENG |
 376                                   SUN4I_HDMI_PAD_CTRL0_PWEND |
 377                                   SUN4I_HDMI_PAD_CTRL0_PWENC |
 378                                   SUN4I_HDMI_PAD_CTRL0_LDODEN |
 379                                   SUN4I_HDMI_PAD_CTRL0_LDOCEN |
 380                                   SUN4I_HDMI_PAD_CTRL0_BIASEN,
 381         .pad_ctrl1_init_val     = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
 382                                   SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
 383                                   SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
 384                                   SUN4I_HDMI_PAD_CTRL1_REG_DEN |
 385                                   SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
 386                                   SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
 387                                   SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
 388                                   SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
 389         .pll_ctrl_init_val      = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
 390                                   SUN4I_HDMI_PLL_CTRL_CS(7) |
 391                                   SUN4I_HDMI_PLL_CTRL_CP_S(15) |
 392                                   SUN4I_HDMI_PLL_CTRL_S(7) |
 393                                   SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
 394                                   SUN4I_HDMI_PLL_CTRL_SDIV2 |
 395                                   SUN4I_HDMI_PLL_CTRL_LDO2_EN |
 396                                   SUN4I_HDMI_PLL_CTRL_LDO1_EN |
 397                                   SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
 398                                   SUN4I_HDMI_PLL_CTRL_BWS |
 399                                   SUN4I_HDMI_PLL_CTRL_PLL_EN,
 400
 401         .ddc_clk_reg            = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
 402         .ddc_clk_pre_divider    = 2,
 403         .ddc_clk_m_offset       = 1,
 404
 405         .field_ddc_en           = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
 406         .field_ddc_start        = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
 407         .field_ddc_reset        = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
 408         .field_ddc_addr_reg     = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
 409         .field_ddc_slave_addr   = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
 410         .field_ddc_int_status   = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
 411         .field_ddc_fifo_clear   = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
 412         .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
 413         .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
 414         .field_ddc_byte_count   = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
 415         .field_ddc_cmd          = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
 416         .field_ddc_sda_en       = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
 417         .field_ddc_sck_en       = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
 418
 419         .ddc_fifo_reg           = SUN4I_HDMI_DDC_FIFO_DATA_REG,
 420         .ddc_fifo_has_dir       = true,
 421 };
 422
 423 static const struct sun4i_hdmi_variant sun6i_variant = {
 424         .has_ddc_parent_clk     = true,
 425         .has_reset_control      = true,
 426         .pad_ctrl0_init_val     = 0xff |
 427                                   SUN4I_HDMI_PAD_CTRL0_TXEN |
 428                                   SUN4I_HDMI_PAD_CTRL0_CKEN |
 429                                   SUN4I_HDMI_PAD_CTRL0_PWENG |
 430                                   SUN4I_HDMI_PAD_CTRL0_PWEND |
 431                                   SUN4I_HDMI_PAD_CTRL0_PWENC |
 432                                   SUN4I_HDMI_PAD_CTRL0_LDODEN |
 433                                   SUN4I_HDMI_PAD_CTRL0_LDOCEN,
 434         .pad_ctrl1_init_val     = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
 435                                   SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
 436                                   SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
 437                                   SUN4I_HDMI_PAD_CTRL1_REG_DEN |
 438                                   SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
 439                                   SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
 440                                   SUN4I_HDMI_PAD_CTRL1_PWSDT |
 441                                   SUN4I_HDMI_PAD_CTRL1_PWSCK |
 442                                   SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
 443                                   SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
 444                                   SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
 445         .pll_ctrl_init_val      = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
 446                                   SUN4I_HDMI_PLL_CTRL_CS(3) |
 447                                   SUN4I_HDMI_PLL_CTRL_CP_S(10) |
 448                                   SUN4I_HDMI_PLL_CTRL_S(4) |
 449                                   SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
 450                                   SUN4I_HDMI_PLL_CTRL_SDIV2 |
 451                                   SUN4I_HDMI_PLL_CTRL_LDO2_EN |
 452                                   SUN4I_HDMI_PLL_CTRL_LDO1_EN |
 453                                   SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
 454                                   SUN4I_HDMI_PLL_CTRL_PLL_EN,
 455
 456         .ddc_clk_reg            = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
 457         .ddc_clk_pre_divider    = 1,
 458         .ddc_clk_m_offset       = 2,
 459
 460         .tmds_clk_div_offset    = 1,
 461
 462         .field_ddc_en           = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
 463         .field_ddc_start        = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
 464         .field_ddc_reset        = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
 465         .field_ddc_addr_reg     = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
 466         .field_ddc_slave_addr   = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
 467         .field_ddc_int_status   = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
 468         .field_ddc_fifo_clear   = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
 469         .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
 470         .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
 471         .field_ddc_byte_count   = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
 472         .field_ddc_cmd          = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
 473         .field_ddc_sda_en       = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
 474         .field_ddc_sck_en       = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
 475
 476         .ddc_fifo_reg           = SUN6I_HDMI_DDC_FIFO_DATA_REG,
 477         .ddc_fifo_thres_incl    = true,
 478 };
 479
 480 static const struct regmap_config sun4i_hdmi_regmap_config = {
 481         .reg_bits       = 32,
 482         .val_bits       = 32,
 483         .reg_stride     = 4,
 484         .max_register   = 0x580,
 485 };
 486
 487 static int sun4i_hdmi_bind(struct device *dev, struct device *master,
 488                            void *data)
 489 {
 490         struct platform_device *pdev = to_platform_device(dev);
 491         struct drm_device *drm = data;
 492         struct sun4i_drv *drv = drm->dev_private;
 493         struct sun4i_hdmi *hdmi;
 494         struct resource *res;
 495         u32 reg;
 496         int ret;
 497
 498         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 499         if (!hdmi)
 500                 return -ENOMEM;
 501         dev_set_drvdata(dev, hdmi);
 502         hdmi->dev = dev;
 503         hdmi->drv = drv;
 504
 505         hdmi->variant = of_device_get_match_data(dev);
 506         if (!hdmi->variant)
 507                 return -EINVAL;
 508
 509         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 510         hdmi->base = devm_ioremap_resource(dev, res);
 511         if (IS_ERR(hdmi->base)) {
 512                 dev_err(dev, "Couldn't map the HDMI encoder registers\n");
 513                 return PTR_ERR(hdmi->base);
 514         }
 515
 516         if (hdmi->variant->has_reset_control) {
 517                 hdmi->reset = devm_reset_control_get(dev, NULL);
 518                 if (IS_ERR(hdmi->reset)) {
 519                         dev_err(dev, "Couldn't get the HDMI reset control\n");
 520                         return PTR_ERR(hdmi->reset);
 521                 }
 522
 523                 ret = reset_control_deassert(hdmi->reset);
 524                 if (ret) {
 525                         dev_err(dev, "Couldn't deassert HDMI reset\n");
 526                         return ret;
 527                 }
 528         }
 529
 530         hdmi->bus_clk = devm_clk_get(dev, "ahb");
 531         if (IS_ERR(hdmi->bus_clk)) {
 532                 dev_err(dev, "Couldn't get the HDMI bus clock\n");
 533                 ret = PTR_ERR(hdmi->bus_clk);
 534                 goto err_assert_reset;
 535         }
 536         clk_prepare_enable(hdmi->bus_clk);
 537
 538         hdmi->mod_clk = devm_clk_get(dev, "mod");
 539         if (IS_ERR(hdmi->mod_clk)) {
 540                 dev_err(dev, "Couldn't get the HDMI mod clock\n");
 541                 ret = PTR_ERR(hdmi->mod_clk);
 542                 goto err_disable_bus_clk;
 543         }
 544         clk_prepare_enable(hdmi->mod_clk);
 545
 546         hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
 547         if (IS_ERR(hdmi->pll0_clk)) {
 548                 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
 549                 ret = PTR_ERR(hdmi->pll0_clk);
 550                 goto err_disable_mod_clk;
 551         }
 552
 553         hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
 554         if (IS_ERR(hdmi->pll1_clk)) {
 555                 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
 556                 ret = PTR_ERR(hdmi->pll1_clk);
 557                 goto err_disable_mod_clk;
 558         }
 559
 560         hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
 561                                              &sun4i_hdmi_regmap_config);
 562         if (IS_ERR(hdmi->regmap)) {
 563                 dev_err(dev, "Couldn't create HDMI encoder regmap\n");
 564                 ret = PTR_ERR(hdmi->regmap);
 565                 goto err_disable_mod_clk;
 566         }
 567
 568         ret = sun4i_tmds_create(hdmi);
 569         if (ret) {
 570                 dev_err(dev, "Couldn't create the TMDS clock\n");
 571                 goto err_disable_mod_clk;
 572         }
 573
 574         if (hdmi->variant->has_ddc_parent_clk) {
 575                 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
 576                 if (IS_ERR(hdmi->ddc_parent_clk)) {
 577                         dev_err(dev, "Couldn't get the HDMI DDC clock\n");
 578                         ret = PTR_ERR(hdmi->ddc_parent_clk);
 579                         goto err_disable_mod_clk;
 580                 }
 581         } else {
 582                 hdmi->ddc_parent_clk = hdmi->tmds_clk;
 583         }
 584
 585         writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
 586
 587         writel(hdmi->variant->pad_ctrl0_init_val,
 588                hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
 589
 590         reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 591         reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
 592         reg |= hdmi->variant->pll_ctrl_init_val;
 593         writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 594
 595         ret = sun4i_hdmi_i2c_create(dev, hdmi);
 596         if (ret) {
 597                 dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
 598                 goto err_disable_mod_clk;
 599         }
 600
 601         hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev);
 602         if (IS_ERR(hdmi->ddc_i2c)) {
 603                 ret = PTR_ERR(hdmi->ddc_i2c);
 604                 if (ret == -ENODEV)
 605                         hdmi->ddc_i2c = NULL;
 606                 else
 607                         goto err_del_i2c_adapter;
 608         }
 609
 610         drm_encoder_helper_add(&hdmi->encoder,
 611                                &sun4i_hdmi_helper_funcs);
 612         ret = drm_encoder_init(drm,
 613                                &hdmi->encoder,
 614                                &sun4i_hdmi_funcs,
 615                                DRM_MODE_ENCODER_TMDS,
 616                                NULL);
 617         if (ret) {
 618                 dev_err(dev, "Couldn't initialise the HDMI encoder\n");
 619                 goto err_put_ddc_i2c;
 620         }
 621
 622         hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
 623                                                                   dev->of_node);
 624         if (!hdmi->encoder.possible_crtcs) {
 625                 ret = -EPROBE_DEFER;
 626                 goto err_put_ddc_i2c;
 627         }
 628
 629 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
 630         hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
 631                 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
 632                 CEC_CAP_PASSTHROUGH | CEC_CAP_RC);
 633         ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
 634         if (ret < 0)
 635                 goto err_cleanup_connector;
 636         writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
 637                hdmi->base + SUN4I_HDMI_CEC);
 638 #endif
 639
 640         drm_connector_helper_add(&hdmi->connector,
 641                                  &sun4i_hdmi_connector_helper_funcs);
 642         ret = drm_connector_init(drm, &hdmi->connector,
 643                                  &sun4i_hdmi_connector_funcs,
 644                                  DRM_MODE_CONNECTOR_HDMIA);
 645         if (ret) {
 646                 dev_err(dev,
 647                         "Couldn't initialise the HDMI connector\n");
 648                 goto err_cleanup_connector;
 649         }
 650
 651         /* There is no HPD interrupt, so we need to poll the controller */
 652         hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
 653                 DRM_CONNECTOR_POLL_DISCONNECT;
 654
 655         ret = cec_register_adapter(hdmi->cec_adap, dev);
 656         if (ret < 0)
 657                 goto err_cleanup_connector;
 658         drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
 659
 660         return 0;
 661
 662 err_cleanup_connector:
 663         cec_delete_adapter(hdmi->cec_adap);
 664         drm_encoder_cleanup(&hdmi->encoder);
 665 err_put_ddc_i2c:
 666         i2c_put_adapter(hdmi->ddc_i2c);
 667 err_del_i2c_adapter:
 668         i2c_del_adapter(hdmi->i2c);
 669 err_disable_mod_clk:
 670         clk_disable_unprepare(hdmi->mod_clk);
 671 err_disable_bus_clk:
 672         clk_disable_unprepare(hdmi->bus_clk);
 673 err_assert_reset:
 674         reset_control_assert(hdmi->reset);
 675         return ret;
 676 }
 677
 678 static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
 679                             void *data)
 680 {
 681         struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
 682
 683         cec_unregister_adapter(hdmi->cec_adap);
 684         drm_connector_cleanup(&hdmi->connector);
 685         drm_encoder_cleanup(&hdmi->encoder);
 686         i2c_del_adapter(hdmi->i2c);
 687         i2c_put_adapter(hdmi->ddc_i2c);
 688         clk_disable_unprepare(hdmi->mod_clk);
 689         clk_disable_unprepare(hdmi->bus_clk);
 690 }
 691
 692 static const struct component_ops sun4i_hdmi_ops = {
 693         .bind   = sun4i_hdmi_bind,
 694         .unbind = sun4i_hdmi_unbind,
 695 };
 696
 697 static int sun4i_hdmi_probe(struct platform_device *pdev)
 698 {
 699         return component_add(&pdev->dev, &sun4i_hdmi_ops);
 700 }
 701
 702 static int sun4i_hdmi_remove(struct platform_device *pdev)
 703 {
 704         component_del(&pdev->dev, &sun4i_hdmi_ops);
 705
 706         return 0;
 707 }
 708
 709 static const struct of_device_id sun4i_hdmi_of_table[] = {
 710         { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, },
 711         { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
 712         { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
 713         { }
 714 };
 715 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
 716
 717 static struct platform_driver sun4i_hdmi_driver = {
 718         .probe          = sun4i_hdmi_probe,
 719         .remove         = sun4i_hdmi_remove,
 720         .driver         = {
 721                 .name           = "sun4i-hdmi",
 722                 .of_match_table = sun4i_hdmi_of_table,
 723         },
 724 };
 725 module_platform_driver(sun4i_hdmi_driver);
 726
 727 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 728 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
 729 MODULE_LICENSE("GPL");