drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  * Author:
   5  *      Chris Zhong <zyw@rock-chips.com>
   6  *      Nickey Yang <nickey.yang@rock-chips.com>
   7  */
   8
   9 #include <drm/drmP.h>
  10 #include <drm/drm_mipi_dsi.h>
  11 #include <drm/bridge/dw_mipi_dsi.h>
  12 #include <drm/drm_of.h>
  13 #include <linux/clk.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/math64.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <video/mipi_display.h>
  22
  23 #include "rockchip_drm_drv.h"
  24 #include "rockchip_drm_vop.h"
  25
  26 #define DSI_PHY_RSTZ                    0xa0
  27 #define PHY_DISFORCEPLL                 0
  28 #define PHY_ENFORCEPLL                  BIT(3)
  29 #define PHY_DISABLECLK                  0
  30 #define PHY_ENABLECLK                   BIT(2)
  31 #define PHY_RSTZ                        0
  32 #define PHY_UNRSTZ                      BIT(1)
  33 #define PHY_SHUTDOWNZ                   0
  34 #define PHY_UNSHUTDOWNZ                 BIT(0)
  35
  36 #define DSI_PHY_IF_CFG                  0xa4
  37 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
  38 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
  39
  40 #define DSI_PHY_STATUS                  0xb0
  41 #define LOCK                            BIT(0)
  42 #define STOP_STATE_CLK_LANE             BIT(2)
  43
  44 #define DSI_PHY_TST_CTRL0               0xb4
  45 #define PHY_TESTCLK                     BIT(1)
  46 #define PHY_UNTESTCLK                   0
  47 #define PHY_TESTCLR                     BIT(0)
  48 #define PHY_UNTESTCLR                   0
  49
  50 #define DSI_PHY_TST_CTRL1               0xb8
  51 #define PHY_TESTEN                      BIT(16)
  52 #define PHY_UNTESTEN                    0
  53 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
  54 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
  55
  56 #define DSI_INT_ST0                     0xbc
  57 #define DSI_INT_ST1                     0xc0
  58 #define DSI_INT_MSK0                    0xc4
  59 #define DSI_INT_MSK1                    0xc8
  60
  61 #define PHY_STATUS_TIMEOUT_US           10000
  62 #define CMD_PKT_STATUS_TIMEOUT_US       20000
  63
  64 #define BYPASS_VCO_RANGE        BIT(7)
  65 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
  66 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
  67 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
  68 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
  69 #define REF_BIAS_CUR_SEL        BIT(0)
  70
  71 #define CP_CURRENT_3UA  0x1
  72 #define CP_CURRENT_4_5UA        0x2
  73 #define CP_CURRENT_7_5UA        0x6
  74 #define CP_CURRENT_6UA  0x9
  75 #define CP_CURRENT_12UA 0xb
  76 #define CP_CURRENT_SEL(val)     ((val) & 0xf)
  77 #define CP_PROGRAM_EN           BIT(7)
  78
  79 #define LPF_RESISTORS_15_5KOHM  0x1
  80 #define LPF_RESISTORS_13KOHM    0x2
  81 #define LPF_RESISTORS_11_5KOHM  0x4
  82 #define LPF_RESISTORS_10_5KOHM  0x8
  83 #define LPF_RESISTORS_8KOHM     0x10
  84 #define LPF_PROGRAM_EN          BIT(6)
  85 #define LPF_RESISTORS_SEL(val)  ((val) & 0x3f)
  86
  87 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
  88
  89 #define INPUT_DIVIDER(val)      (((val) - 1) & 0x7f)
  90 #define LOW_PROGRAM_EN          0
  91 #define HIGH_PROGRAM_EN         BIT(7)
  92 #define LOOP_DIV_LOW_SEL(val)   (((val) - 1) & 0x1f)
  93 #define LOOP_DIV_HIGH_SEL(val)  ((((val) - 1) >> 5) & 0xf)
  94 #define PLL_LOOP_DIV_EN         BIT(5)
  95 #define PLL_INPUT_DIV_EN        BIT(4)
  96
  97 #define POWER_CONTROL           BIT(6)
  98 #define INTERNAL_REG_CURRENT    BIT(3)
  99 #define BIAS_BLOCK_ON           BIT(2)
 100 #define BANDGAP_ON              BIT(0)
 101
 102 #define TER_RESISTOR_HIGH       BIT(7)
 103 #define TER_RESISTOR_LOW        0
 104 #define LEVEL_SHIFTERS_ON       BIT(6)
 105 #define TER_CAL_DONE            BIT(5)
 106 #define SETRD_MAX               (0x7 << 2)
 107 #define POWER_MANAGE            BIT(1)
 108 #define TER_RESISTORS_ON        BIT(0)
 109
 110 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 111 #define BANDGAP_SEL(val)        ((val) & 0x7)
 112 #define TLP_PROGRAM_EN          BIT(7)
 113 #define THS_PRE_PROGRAM_EN      BIT(7)
 114 #define THS_ZERO_PROGRAM_EN     BIT(6)
 115
 116 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL                0x10
 117 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS                  0x11
 118 #define PLL_LPF_AND_CP_CONTROL                          0x12
 119 #define PLL_INPUT_DIVIDER_RATIO                         0x17
 120 #define PLL_LOOP_DIVIDER_RATIO                          0x18
 121 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL       0x19
 122 #define BANDGAP_AND_BIAS_CONTROL                        0x20
 123 #define TERMINATION_RESISTER_CONTROL                    0x21
 124 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY         0x22
 125 #define HS_RX_CONTROL_OF_LANE_0                         0x44
 126 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL     0x60
 127 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL     0x61
 128 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL     0x62
 129 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL       0x63
 130 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL        0x64
 131 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL              0x65
 132 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL      0x70
 133 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL      0x71
 134 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL      0x72
 135 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL        0x73
 136 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL         0x74
 137
 138 #define DW_MIPI_NEEDS_PHY_CFG_CLK       BIT(0)
 139 #define DW_MIPI_NEEDS_GRF_CLK           BIT(1)
 140
 141 #define RK3288_GRF_SOC_CON6             0x025c
 142 #define RK3288_DSI0_LCDC_SEL            BIT(6)
 143 #define RK3288_DSI1_LCDC_SEL            BIT(9)
 144
 145 #define RK3399_GRF_SOC_CON20            0x6250
 146 #define RK3399_DSI0_LCDC_SEL            BIT(0)
 147 #define RK3399_DSI1_LCDC_SEL            BIT(4)
 148
 149 #define RK3399_GRF_SOC_CON22            0x6258
 150 #define RK3399_DSI0_TURNREQUEST         (0xf << 12)
 151 #define RK3399_DSI0_TURNDISABLE         (0xf << 8)
 152 #define RK3399_DSI0_FORCETXSTOPMODE     (0xf << 4)
 153 #define RK3399_DSI0_FORCERXMODE         (0xf << 0)
 154
 155 #define RK3399_GRF_SOC_CON23            0x625c
 156 #define RK3399_DSI1_TURNDISABLE         (0xf << 12)
 157 #define RK3399_DSI1_FORCETXSTOPMODE     (0xf << 8)
 158 #define RK3399_DSI1_FORCERXMODE         (0xf << 4)
 159 #define RK3399_DSI1_ENABLE              (0xf << 0)
 160
 161 #define RK3399_GRF_SOC_CON24            0x6260
 162 #define RK3399_TXRX_MASTERSLAVEZ        BIT(7)
 163 #define RK3399_TXRX_ENABLECLK           BIT(6)
 164 #define RK3399_TXRX_BASEDIR             BIT(5)
 165
 166 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
 167
 168 #define to_dsi(nm)      container_of(nm, struct dw_mipi_dsi_rockchip, nm)
 169
 170 enum {
 171         BANDGAP_97_07,
 172         BANDGAP_98_05,
 173         BANDGAP_99_02,
 174         BANDGAP_100_00,
 175         BANDGAP_93_17,
 176         BANDGAP_94_15,
 177         BANDGAP_95_12,
 178         BANDGAP_96_10,
 179 };
 180
 181 enum {
 182         BIASEXTR_87_1,
 183         BIASEXTR_91_5,
 184         BIASEXTR_95_9,
 185         BIASEXTR_100,
 186         BIASEXTR_105_94,
 187         BIASEXTR_111_88,
 188         BIASEXTR_118_8,
 189         BIASEXTR_127_7,
 190 };
 191
 192 struct rockchip_dw_dsi_chip_data {
 193         u32 reg;
 194
 195         u32 lcdsel_grf_reg;
 196         u32 lcdsel_big;
 197         u32 lcdsel_lit;
 198
 199         u32 enable_grf_reg;
 200         u32 enable;
 201
 202         u32 lanecfg1_grf_reg;
 203         u32 lanecfg1;
 204         u32 lanecfg2_grf_reg;
 205         u32 lanecfg2;
 206
 207         unsigned int flags;
 208         unsigned int max_data_lanes;
 209 };
 210
 211 struct dw_mipi_dsi_rockchip {
 212         struct device *dev;
 213         struct drm_encoder encoder;
 214         void __iomem *base;
 215
 216         struct regmap *grf_regmap;
 217         struct clk *pllref_clk;
 218         struct clk *grf_clk;
 219         struct clk *phy_cfg_clk;
 220
 221         /* dual-channel */
 222         bool is_slave;
 223         struct dw_mipi_dsi_rockchip *slave;
 224
 225         unsigned int lane_mbps; /* per lane */
 226         u16 input_div;
 227         u16 feedback_div;
 228         u32 format;
 229
 230         struct dw_mipi_dsi *dmd;
 231         const struct rockchip_dw_dsi_chip_data *cdata;
 232         struct dw_mipi_dsi_plat_data pdata;
 233         int devcnt;
 234 };
 235
 236 struct dphy_pll_parameter_map {
 237         unsigned int max_mbps;
 238         u8 hsfreqrange;
 239         u8 icpctrl;
 240         u8 lpfctrl;
 241 };
 242
 243 /* The table is based on 27MHz DPHY pll reference clock. */
 244 static const struct dphy_pll_parameter_map dppa_map[] = {
 245         {  89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 246         {  99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 247         { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
 248         { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 249         { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 250         { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 251         { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 252         { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 253         { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
 254         { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 255         { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 256         { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
 257         { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
 258         { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
 259         { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 260         { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 261         { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
 262         { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 263         { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 264         { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
 265         { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
 266         { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 267         { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 268         { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 269         { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 270         { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 271         { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
 272         { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 273         { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 274         {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 275         {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
 276         {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 277         {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 278         {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 279         {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 280         {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 281         {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 282         {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
 283         {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
 284 };
 285
 286 static int max_mbps_to_parameter(unsigned int max_mbps)
 287 {
 288         int i;
 289
 290         for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
 291                 if (dppa_map[i].max_mbps >= max_mbps)
 292                         return i;
 293
 294         return -EINVAL;
 295 }
 296
 297 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
 298 {
 299         writel(val, dsi->base + reg);
 300 }
 301
 302 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
 303 {
 304         return readl(dsi->base + reg);
 305 }
 306
 307 static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask)
 308 {
 309         dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
 310 }
 311
 312 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
 313                                    u32 mask, u32 val)
 314 {
 315         dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
 316 }
 317
 318 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
 319                                   u8 test_code,
 320                                   u8 test_data)
 321 {
 322         /*
 323          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 324          * is latched internally as the current test code. Test data is
 325          * programmed internally by rising edge on TESTCLK.
 326          */
 327         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 328
 329         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 330                                           PHY_TESTDIN(test_code));
 331
 332         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 333
 334         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 335                                           PHY_TESTDIN(test_data));
 336
 337         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 338 }
 339
 340 /**
 341  * ns2bc - Nanoseconds to byte clock cycles
 342  */
 343 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
 344 {
 345         return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
 346 }
 347
 348 /**
 349  * ns2ui - Nanoseconds to UI time periods
 350  */
 351 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
 352 {
 353         return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
 354 }
 355
 356 static int dw_mipi_dsi_phy_init(void *priv_data)
 357 {
 358         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 359         int ret, i, vco;
 360
 361         /*
 362          * Get vco from frequency(lane_mbps)
 363          * vco  frequency table
 364          * 000 - between   80 and  200 MHz
 365          * 001 - between  200 and  300 MHz
 366          * 010 - between  300 and  500 MHz
 367          * 011 - between  500 and  700 MHz
 368          * 100 - between  700 and  900 MHz
 369          * 101 - between  900 and 1100 MHz
 370          * 110 - between 1100 and 1300 MHz
 371          * 111 - between 1300 and 1500 MHz
 372          */
 373         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 374
 375         i = max_mbps_to_parameter(dsi->lane_mbps);
 376         if (i < 0) {
 377                 DRM_DEV_ERROR(dsi->dev,
 378                               "failed to get parameter for %dmbps clock\n",
 379                               dsi->lane_mbps);
 380                 return i;
 381         }
 382
 383         ret = clk_prepare_enable(dsi->phy_cfg_clk);
 384         if (ret) {
 385                 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
 386                 return ret;
 387         }
 388
 389         dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
 390                               BYPASS_VCO_RANGE |
 391                               VCO_RANGE_CON_SEL(vco) |
 392                               VCO_IN_CAP_CON_LOW |
 393                               REF_BIAS_CUR_SEL);
 394
 395         dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
 396                               CP_CURRENT_SEL(dppa_map[i].icpctrl));
 397         dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
 398                               CP_PROGRAM_EN | LPF_PROGRAM_EN |
 399                               LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
 400
 401         dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
 402                               HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
 403
 404         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
 405                               INPUT_DIVIDER(dsi->input_div));
 406         dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
 407                               LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 408                               LOW_PROGRAM_EN);
 409         /*
 410          * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
 411          * to make the configured LSB effective according to IP simulation
 412          * and lab test results.
 413          * Only in this way can we get correct mipi phy pll frequency.
 414          */
 415         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
 416                               PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 417         dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
 418                               LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 419                               HIGH_PROGRAM_EN);
 420         dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
 421                               PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 422
 423         dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
 424                               LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
 425         dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
 426                               HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
 427
 428         dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
 429                               POWER_CONTROL | INTERNAL_REG_CURRENT |
 430                               BIAS_BLOCK_ON | BANDGAP_ON);
 431
 432         dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
 433                               TER_RESISTOR_LOW | TER_CAL_DONE |
 434                               SETRD_MAX | TER_RESISTORS_ON);
 435         dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
 436                               TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 437                               SETRD_MAX | POWER_MANAGE |
 438                               TER_RESISTORS_ON);
 439
 440         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
 441                               TLP_PROGRAM_EN | ns2bc(dsi, 500));
 442         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
 443                               THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
 444         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
 445                               THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
 446         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
 447                               THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
 448         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
 449                               BIT(5) | ns2bc(dsi, 100));
 450         dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
 451                               BIT(5) | (ns2bc(dsi, 60) + 7));
 452
 453         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
 454                               TLP_PROGRAM_EN | ns2bc(dsi, 500));
 455         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
 456                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
 457         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
 458                               THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
 459         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
 460                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
 461         dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
 462                               BIT(5) | ns2bc(dsi, 100));
 463
 464         clk_disable_unprepare(dsi->phy_cfg_clk);
 465
 466         return ret;
 467 }
 468
 469 static int
 470 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 471                           unsigned long mode_flags, u32 lanes, u32 format,
 472                           unsigned int *lane_mbps)
 473 {
 474         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 475         int bpp;
 476         unsigned long mpclk, tmp;
 477         unsigned int target_mbps = 1000;
 478         unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
 479         unsigned long best_freq = 0;
 480         unsigned long fvco_min, fvco_max, fin, fout;
 481         unsigned int min_prediv, max_prediv;
 482         unsigned int _prediv, uninitialized_var(best_prediv);
 483         unsigned long _fbdiv, uninitialized_var(best_fbdiv);
 484         unsigned long min_delta = ULONG_MAX;
 485
 486         dsi->format = format;
 487         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 488         if (bpp < 0) {
 489                 DRM_DEV_ERROR(dsi->dev,
 490                               "failed to get bpp for pixel format %d\n",
 491                               dsi->format);
 492                 return bpp;
 493         }
 494
 495         mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
 496         if (mpclk) {
 497                 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
 498                 tmp = mpclk * (bpp / lanes) * 10 / 8;
 499                 if (tmp < max_mbps)
 500                         target_mbps = tmp;
 501                 else
 502                         DRM_DEV_ERROR(dsi->dev,
 503                                       "DPHY clock frequency is out of range\n");
 504         }
 505
 506         fin = clk_get_rate(dsi->pllref_clk);
 507         fout = target_mbps * USEC_PER_SEC;
 508
 509         /* constraint: 5Mhz <= Fref / N <= 40MHz */
 510         min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
 511         max_prediv = fin / (5 * USEC_PER_SEC);
 512
 513         /* constraint: 80MHz <= Fvco <= 1500Mhz */
 514         fvco_min = 80 * USEC_PER_SEC;
 515         fvco_max = 1500 * USEC_PER_SEC;
 516
 517         for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
 518                 u64 tmp;
 519                 u32 delta;
 520                 /* Fvco = Fref * M / N */
 521                 tmp = (u64)fout * _prediv;
 522                 do_div(tmp, fin);
 523                 _fbdiv = tmp;
 524                 /*
 525                  * Due to the use of a "by 2 pre-scaler," the range of the
 526                  * feedback multiplication value M is limited to even division
 527                  * numbers, and m must be greater than 6, not bigger than 512.
 528                  */
 529                 if (_fbdiv < 6 || _fbdiv > 512)
 530                         continue;
 531
 532                 _fbdiv += _fbdiv % 2;
 533
 534                 tmp = (u64)_fbdiv * fin;
 535                 do_div(tmp, _prediv);
 536                 if (tmp < fvco_min || tmp > fvco_max)
 537                         continue;
 538
 539                 delta = abs(fout - tmp);
 540                 if (delta < min_delta) {
 541                         best_prediv = _prediv;
 542                         best_fbdiv = _fbdiv;
 543                         min_delta = delta;
 544                         best_freq = tmp;
 545                 }
 546         }
 547
 548         if (best_freq) {
 549                 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
 550                 *lane_mbps = dsi->lane_mbps;
 551                 dsi->input_div = best_prediv;
 552                 dsi->feedback_div = best_fbdiv;
 553         } else {
 554                 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
 555                 return -EINVAL;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
 562         .init = dw_mipi_dsi_phy_init,
 563         .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
 564 };
 565
 566 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi,
 567                                         int mux)
 568 {
 569         if (dsi->cdata->lcdsel_grf_reg)
 570                 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
 571                         mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
 572
 573         if (dsi->cdata->lanecfg1_grf_reg)
 574                 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
 575                                               dsi->cdata->lanecfg1);
 576
 577         if (dsi->cdata->lanecfg2_grf_reg)
 578                 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
 579                                               dsi->cdata->lanecfg2);
 580
 581         if (dsi->cdata->enable_grf_reg)
 582                 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
 583                                               dsi->cdata->enable);
 584 }
 585
 586 static int
 587 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 588                                  struct drm_crtc_state *crtc_state,
 589                                  struct drm_connector_state *conn_state)
 590 {
 591         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 592         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 593
 594         switch (dsi->format) {
 595         case MIPI_DSI_FMT_RGB888:
 596                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 597                 break;
 598         case MIPI_DSI_FMT_RGB666:
 599                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
 600                 break;
 601         case MIPI_DSI_FMT_RGB565:
 602                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
 603                 break;
 604         default:
 605                 WARN_ON(1);
 606                 return -EINVAL;
 607         }
 608
 609         s->output_type = DRM_MODE_CONNECTOR_DSI;
 610         if (dsi->slave)
 611                 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
 612
 613         return 0;
 614 }
 615
 616 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 617 {
 618         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 619         int ret, mux;
 620
 621         mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
 622                                                 &dsi->encoder);
 623         if (mux < 0)
 624                 return;
 625
 626         pm_runtime_get_sync(dsi->dev);
 627         if (dsi->slave)
 628                 pm_runtime_get_sync(dsi->slave->dev);
 629
 630         /*
 631          * For the RK3399, the clk of grf must be enabled before writing grf
 632          * register. And for RK3288 or other soc, this grf_clk must be NULL,
 633          * the clk_prepare_enable return true directly.
 634          */
 635         ret = clk_prepare_enable(dsi->grf_clk);
 636         if (ret) {
 637                 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
 638                 return;
 639         }
 640
 641         dw_mipi_dsi_rockchip_config(dsi, mux);
 642         if (dsi->slave)
 643                 dw_mipi_dsi_rockchip_config(dsi->slave, mux);
 644
 645         clk_disable_unprepare(dsi->grf_clk);
 646 }
 647
 648 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 649 {
 650         struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
 651
 652         if (dsi->slave)
 653                 pm_runtime_put(dsi->slave->dev);
 654         pm_runtime_put(dsi->dev);
 655 }
 656
 657 static const struct drm_encoder_helper_funcs
 658 dw_mipi_dsi_encoder_helper_funcs = {
 659         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
 660         .enable = dw_mipi_dsi_encoder_enable,
 661         .disable = dw_mipi_dsi_encoder_disable,
 662 };
 663
 664 static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
 665         .destroy = drm_encoder_cleanup,
 666 };
 667
 668 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
 669                                            struct drm_device *drm_dev)
 670 {
 671         struct drm_encoder *encoder = &dsi->encoder;
 672         int ret;
 673
 674         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
 675                                                              dsi->dev->of_node);
 676
 677         ret = drm_encoder_init(drm_dev, encoder, &dw_mipi_dsi_encoder_funcs,
 678                                DRM_MODE_ENCODER_DSI, NULL);
 679         if (ret) {
 680                 DRM_ERROR("Failed to initialize encoder with drm\n");
 681                 return ret;
 682         }
 683
 684         drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
 685
 686         return 0;
 687 }
 688
 689 static struct device
 690 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
 691 {
 692         const struct of_device_id *match;
 693         struct device_node *node = NULL, *local;
 694
 695         match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
 696
 697         local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
 698         if (!local)
 699                 return NULL;
 700
 701         while ((node = of_find_compatible_node(node, NULL,
 702                                                match->compatible))) {
 703                 struct device_node *remote;
 704
 705                 /* found ourself */
 706                 if (node == dsi->dev->of_node)
 707                         continue;
 708
 709                 remote = of_graph_get_remote_node(node, 1, 0);
 710                 if (!remote)
 711                         continue;
 712
 713                 /* same display device in port1-ep0 for both */
 714                 if (remote == local) {
 715                         struct dw_mipi_dsi_rockchip *dsi2;
 716                         struct platform_device *pdev;
 717
 718                         pdev = of_find_device_by_node(node);
 719
 720                         /*
 721                          * we have found the second, so will either return it
 722                          * or return with an error. In any case won't need the
 723                          * nodes anymore nor continue the loop.
 724                          */
 725                         of_node_put(remote);
 726                         of_node_put(node);
 727                         of_node_put(local);
 728
 729                         if (!pdev)
 730                                 return ERR_PTR(-EPROBE_DEFER);
 731
 732                         dsi2 = platform_get_drvdata(pdev);
 733                         if (!dsi2) {
 734                                 platform_device_put(pdev);
 735                                 return ERR_PTR(-EPROBE_DEFER);
 736                         }
 737
 738                         return &pdev->dev;
 739                 }
 740
 741                 of_node_put(remote);
 742         }
 743
 744         of_node_put(local);
 745
 746         return NULL;
 747 }
 748
 749 static int dw_mipi_dsi_rockchip_bind(struct device *dev,
 750                                      struct device *master,
 751                                      void *data)
 752 {
 753         struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
 754         struct drm_device *drm_dev = data;
 755         struct device *second;
 756         bool master1, master2;
 757         int ret;
 758
 759         second = dw_mipi_dsi_rockchip_find_second(dsi);
 760         if (IS_ERR(second))
 761                 return PTR_ERR(second);
 762
 763         if (second) {
 764                 master1 = of_property_read_bool(dsi->dev->of_node,
 765                                                 "clock-master");
 766                 master2 = of_property_read_bool(second->of_node,
 767                                                 "clock-master");
 768
 769                 if (master1 && master2) {
 770                         DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
 771                         return -EINVAL;
 772                 }
 773
 774                 if (!master1 && !master2) {
 775                         DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
 776                         return -EINVAL;
 777                 }
 778
 779                 /* we are the slave in dual-DSI */
 780                 if (!master1) {
 781                         dsi->is_slave = true;
 782                         return 0;
 783                 }
 784
 785                 dsi->slave = dev_get_drvdata(second);
 786                 if (!dsi->slave) {
 787                         DRM_DEV_ERROR(dev, "could not get slaves data\n");
 788                         return -ENODEV;
 789                 }
 790
 791                 dsi->slave->is_slave = true;
 792                 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
 793                 put_device(second);
 794         }
 795
 796         ret = clk_prepare_enable(dsi->pllref_clk);
 797         if (ret) {
 798                 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
 799                 return ret;
 800         }
 801
 802         ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
 803         if (ret) {
 804                 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
 805                 return ret;
 806         }
 807
 808         ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
 809         if (ret) {
 810                 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
 811                 return ret;
 812         }
 813
 814         return 0;
 815 }
 816
 817 static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
 818                                         struct device *master,
 819                                         void *data)
 820 {
 821         struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
 822
 823         if (dsi->is_slave)
 824                 return;
 825
 826         dw_mipi_dsi_unbind(dsi->dmd);
 827
 828         clk_disable_unprepare(dsi->pllref_clk);
 829 }
 830
 831 static const struct component_ops dw_mipi_dsi_rockchip_ops = {
 832         .bind   = dw_mipi_dsi_rockchip_bind,
 833         .unbind = dw_mipi_dsi_rockchip_unbind,
 834 };
 835
 836 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
 837                                             struct mipi_dsi_device *device)
 838 {
 839         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 840         struct device *second;
 841         int ret;
 842
 843         ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
 844         if (ret) {
 845                 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
 846                                         ret);
 847                 return ret;
 848         }
 849
 850         second = dw_mipi_dsi_rockchip_find_second(dsi);
 851         if (IS_ERR(second))
 852                 return PTR_ERR(second);
 853         if (second) {
 854                 ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
 855                 if (ret) {
 856                         DRM_DEV_ERROR(second,
 857                                       "Failed to register component: %d\n",
 858                                       ret);
 859                         return ret;
 860                 }
 861         }
 862
 863         return 0;
 864 }
 865
 866 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
 867                                             struct mipi_dsi_device *device)
 868 {
 869         struct dw_mipi_dsi_rockchip *dsi = priv_data;
 870         struct device *second;
 871
 872         second = dw_mipi_dsi_rockchip_find_second(dsi);
 873         if (second && !IS_ERR(second))
 874                 component_del(second, &dw_mipi_dsi_rockchip_ops);
 875
 876         component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
 877
 878         return 0;
 879 }
 880
 881 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
 882         .attach = dw_mipi_dsi_rockchip_host_attach,
 883         .detach = dw_mipi_dsi_rockchip_host_detach,
 884 };
 885
 886 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
 887 {
 888         struct device *dev = &pdev->dev;
 889         struct device_node *np = dev->of_node;
 890         struct dw_mipi_dsi_rockchip *dsi;
 891         struct resource *res;
 892         const struct rockchip_dw_dsi_chip_data *cdata =
 893                                 of_device_get_match_data(dev);
 894         int ret, i;
 895
 896         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
 897         if (!dsi)
 898                 return -ENOMEM;
 899
 900         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 901         dsi->base = devm_ioremap_resource(dev, res);
 902         if (IS_ERR(dsi->base)) {
 903                 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
 904                 return PTR_ERR(dsi->base);
 905         }
 906
 907         i = 0;
 908         while (cdata[i].reg) {
 909                 if (cdata[i].reg == res->start) {
 910                         dsi->cdata = &cdata[i];
 911                         break;
 912                 }
 913
 914                 i++;
 915         }
 916
 917         if (!dsi->cdata) {
 918                 dev_err(dev, "no dsi-config for %s node\n", np->name);
 919                 return -EINVAL;
 920         }
 921
 922         dsi->pllref_clk = devm_clk_get(dev, "ref");
 923         if (IS_ERR(dsi->pllref_clk)) {
 924                 ret = PTR_ERR(dsi->pllref_clk);
 925                 DRM_DEV_ERROR(dev,
 926                               "Unable to get pll reference clock: %d\n", ret);
 927                 return ret;
 928         }
 929
 930         if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
 931                 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
 932                 if (IS_ERR(dsi->phy_cfg_clk)) {
 933                         ret = PTR_ERR(dsi->phy_cfg_clk);
 934                         DRM_DEV_ERROR(dev,
 935                                       "Unable to get phy_cfg_clk: %d\n", ret);
 936                         return ret;
 937                 }
 938         }
 939
 940         if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
 941                 dsi->grf_clk = devm_clk_get(dev, "grf");
 942                 if (IS_ERR(dsi->grf_clk)) {
 943                         ret = PTR_ERR(dsi->grf_clk);
 944                         DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
 945                         return ret;
 946                 }
 947         }
 948
 949         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 950         if (IS_ERR(dsi->grf_regmap)) {
 951                 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
 952                 return PTR_ERR(dsi->grf_regmap);
 953         }
 954
 955         dsi->dev = dev;
 956         dsi->pdata.base = dsi->base;
 957         dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
 958         dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
 959         dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
 960         dsi->pdata.priv_data = dsi;
 961         platform_set_drvdata(pdev, dsi);
 962
 963         dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
 964         if (IS_ERR(dsi->dmd)) {
 965                 ret = PTR_ERR(dsi->dmd);
 966                 if (ret != -EPROBE_DEFER)
 967                         DRM_DEV_ERROR(dev,
 968                                       "Failed to probe dw_mipi_dsi: %d\n", ret);
 969                 goto err_clkdisable;
 970         }
 971
 972         return 0;
 973
 974 err_clkdisable:
 975         clk_disable_unprepare(dsi->pllref_clk);
 976         return ret;
 977 }
 978
 979 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
 980 {
 981         struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
 982
 983         if (dsi->devcnt == 0)
 984                 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
 985
 986         dw_mipi_dsi_remove(dsi->dmd);
 987
 988         return 0;
 989 }
 990
 991 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
 992         {
 993                 .reg = 0xff960000,
 994                 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
 995                 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
 996                 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
 997
 998                 .max_data_lanes = 4,
 999         },
1000         {
1001                 .reg = 0xff964000,
1002                 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1003                 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1004                 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1005
1006                 .max_data_lanes = 4,
1007         },
1008         { /* sentinel */ }
1009 };
1010
1011 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1012         {
1013                 .reg = 0xff960000,
1014                 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1015                 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1016                 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1017                                             RK3399_DSI0_LCDC_SEL),
1018
1019                 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1020                 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1021                                              RK3399_DSI0_TURNDISABLE |
1022                                              RK3399_DSI0_FORCETXSTOPMODE |
1023                                              RK3399_DSI0_FORCERXMODE),
1024
1025                 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1026                 .max_data_lanes = 4,
1027         },
1028         {
1029                 .reg = 0xff968000,
1030                 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1031                 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1032                 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1033                                             RK3399_DSI1_LCDC_SEL),
1034
1035                 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1036                 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1037                                              RK3399_DSI1_FORCETXSTOPMODE |
1038                                              RK3399_DSI1_FORCERXMODE |
1039                                              RK3399_DSI1_ENABLE),
1040
1041                 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1042                 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1043                                           RK3399_TXRX_ENABLECLK,
1044                                           RK3399_TXRX_MASTERSLAVEZ |
1045                                           RK3399_TXRX_ENABLECLK |
1046                                           RK3399_TXRX_BASEDIR),
1047
1048                 .enable_grf_reg = RK3399_GRF_SOC_CON23,
1049                 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1050
1051                 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1052                 .max_data_lanes = 4,
1053         },
1054         { /* sentinel */ }
1055 };
1056
1057 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1058         {
1059          .compatible = "rockchip,rk3288-mipi-dsi",
1060          .data = &rk3288_chip_data,
1061         }, {
1062          .compatible = "rockchip,rk3399-mipi-dsi",
1063          .data = &rk3399_chip_data,
1064         },
1065         { /* sentinel */ }
1066 };
1067 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1068
1069 struct platform_driver dw_mipi_dsi_rockchip_driver = {
1070         .probe          = dw_mipi_dsi_rockchip_probe,
1071         .remove         = dw_mipi_dsi_rockchip_remove,
1072         .driver         = {
1073                 .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1074                 .name   = "dw-mipi-dsi-rockchip",
1075         },
1076 };