2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * DEALINGS IN THE SOFTWARE.
27 #include <core/gpuobj.h>
28 #include <subdev/fb.h>
29 #include <engine/falcon.h>
30 #include <subdev/mc.h>
33 * gm200_secboot_run_blob() - run the given high-secure blob
37 gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob,
38 struct nvkm_falcon *falcon)
40 struct gm200_secboot *gsb = gm200_secboot(sb);
41 struct nvkm_subdev *subdev = &gsb->base.subdev;
42 struct nvkm_vma *vma = NULL;
46 ret = nvkm_falcon_get(falcon, subdev);
50 /* Map the HS firmware so the HS bootloader can see it */
51 ret = nvkm_vmm_get(gsb->vmm, 12, blob->size, &vma);
53 nvkm_falcon_put(falcon, subdev);
57 ret = nvkm_memory_map(blob, 0, gsb->vmm, vma, NULL, 0);
61 /* Reset and set the falcon up */
62 ret = nvkm_falcon_reset(falcon);
65 nvkm_falcon_bind_context(falcon, gsb->inst);
67 /* Load the HS bootloader into the falcon's IMEM/DMEM */
68 ret = sb->acr->func->load(sb->acr, falcon, blob, vma->addr);
74 /* Disable interrupts as we will poll for the HALT bit */
75 nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, false);
77 /* Set default error value in mailbox register */
78 nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5);
80 /* Start the HS bootloader */
81 nvkm_falcon_set_start_addr(falcon, start_address);
82 nvkm_falcon_start(falcon);
83 ret = nvkm_falcon_wait_for_halt(falcon, 100);
88 * The mailbox register contains the (positive) error code - return this
91 ret = nvkm_falcon_rd32(falcon, 0x040);
94 /* Reenable interrupts */
95 nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, true);
97 /* We don't need the ACR firmware anymore */
98 nvkm_vmm_put(gsb->vmm, &vma);
99 nvkm_falcon_put(falcon, subdev);
105 gm200_secboot_oneinit(struct nvkm_secboot *sb)
107 struct gm200_secboot *gsb = gm200_secboot(sb);
108 struct nvkm_device *device = sb->subdev.device;
111 /* Allocate instance block and VM */
112 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0, true,
117 ret = nvkm_vmm_new(device, 0, 600 * 1024, NULL, 0, NULL, "acr",
122 atomic_inc(&gsb->vmm->engref[NVKM_SUBDEV_PMU]);
123 gsb->vmm->debug = gsb->base.subdev.debug;
125 ret = nvkm_vmm_join(gsb->vmm, gsb->inst);
129 if (sb->acr->func->oneinit) {
130 ret = sb->acr->func->oneinit(sb->acr, sb);
139 gm200_secboot_fini(struct nvkm_secboot *sb, bool suspend)
143 if (sb->acr->func->fini)
144 ret = sb->acr->func->fini(sb->acr, sb, suspend);
150 gm200_secboot_dtor(struct nvkm_secboot *sb)
152 struct gm200_secboot *gsb = gm200_secboot(sb);
154 sb->acr->func->dtor(sb->acr);
156 nvkm_vmm_part(gsb->vmm, gsb->inst);
157 nvkm_vmm_unref(&gsb->vmm);
158 nvkm_memory_unref(&gsb->inst);
164 static const struct nvkm_secboot_func
166 .dtor = gm200_secboot_dtor,
167 .oneinit = gm200_secboot_oneinit,
168 .fini = gm200_secboot_fini,
169 .run_blob = gm200_secboot_run_blob,
173 gm200_secboot_new(struct nvkm_device *device, int index,
174 struct nvkm_secboot **psb)
177 struct gm200_secboot *gsb;
178 struct nvkm_acr *acr;
180 acr = acr_r361_new(BIT(NVKM_SECBOOT_FALCON_FECS) |
181 BIT(NVKM_SECBOOT_FALCON_GPCCS));
185 gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
192 ret = nvkm_secboot_ctor(&gm200_secboot, acr, device, index, &gsb->base);