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24 #include "changk104.h"
27 #include <core/gpuobj.h>
29 #include <nvif/class.h>
32 tu102_fifo_runlist_commit(struct gk104_fifo *fifo, int runl,
33 struct nvkm_memory *mem, int nr)
35 struct nvkm_device *device = fifo->base.engine.subdev.device;
36 u64 addr = nvkm_memory_addr(mem);
39 nvkm_wr32(device, 0x002b00 + (runl * 0x10), lower_32_bits(addr));
40 nvkm_wr32(device, 0x002b04 + (runl * 0x10), upper_32_bits(addr));
41 nvkm_wr32(device, 0x002b08 + (runl * 0x10), nr);
43 /*XXX: how to wait? can you even wait? */
46 const struct gk104_fifo_runlist_func
47 tu102_fifo_runlist = {
49 .cgrp = gv100_fifo_runlist_cgrp,
50 .chan = gv100_fifo_runlist_chan,
51 .commit = tu102_fifo_runlist_commit,
54 static const struct nvkm_enum
55 tu102_fifo_fault_engine[] = {
59 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
77 { 0x80, "BAR1", NULL, NVKM_SUBDEV_BAR },
78 { 0xc0, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
83 tu102_fifo_pbdma_init(struct gk104_fifo *fifo)
85 struct nvkm_device *device = fifo->base.engine.subdev.device;
86 const u32 mask = (1 << fifo->pbdma_nr) - 1;
87 /*XXX: this is a bit of a guess at this point in time. */
88 nvkm_mask(device, 0xb65000, 0x80000fff, 0x80000000 | mask);
91 static const struct gk104_fifo_pbdma_func
93 .nr = gm200_fifo_pbdma_nr,
94 .init = tu102_fifo_pbdma_init,
95 .init_timeout = gk208_fifo_pbdma_init_timeout,
98 static const struct gk104_fifo_func
100 .pbdma = &tu102_fifo_pbdma,
101 .fault.access = gv100_fifo_fault_access,
102 .fault.engine = tu102_fifo_fault_engine,
103 .fault.reason = gv100_fifo_fault_reason,
104 .fault.hubclient = gv100_fifo_fault_hubclient,
105 .fault.gpcclient = gv100_fifo_fault_gpcclient,
106 .runlist = &tu102_fifo_runlist,
107 .user = {{-1,-1,VOLTA_USERMODE_A }, tu102_fifo_user_new },
108 .chan = {{ 0, 0,TURING_CHANNEL_GPFIFO_A}, tu102_fifo_gpfifo_new },
113 tu102_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
115 return gk104_fifo_new_(&tu102_fifo, device, index, 4096, pfifo);