2 * Copyright 2018 Red Hat Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #include <subdev/timer.h>
26 const struct nv50_disp_mthd_list
27 gv100_disp_core_mthd_base = {
42 const struct nv50_disp_mthd_list
43 gv100_disp_core_mthd_sor = {
55 static const struct nv50_disp_mthd_list
56 gv100_disp_core_mthd_wndw = {
69 static const struct nv50_disp_mthd_list
70 gv100_disp_core_mthd_head = {
100 { 0x207c, 0x68207c },
101 { 0x2080, 0x682080 },
102 { 0x2088, 0x682088 },
103 { 0x2090, 0x682090 },
104 { 0x209c, 0x68209c },
105 { 0x20a0, 0x6820a0 },
106 { 0x20a4, 0x6820a4 },
107 { 0x20a8, 0x6820a8 },
108 { 0x20ac, 0x6820ac },
109 { 0x218c, 0x68218c },
110 { 0x2194, 0x682194 },
111 { 0x2198, 0x682198 },
112 { 0x219c, 0x68219c },
113 { 0x21a0, 0x6821a0 },
114 { 0x21a4, 0x6821a4 },
115 { 0x2214, 0x682214 },
116 { 0x2218, 0x682218 },
121 static const struct nv50_disp_chan_mthd
122 gv100_disp_core_mthd = {
127 { "Global", 1, &gv100_disp_core_mthd_base },
128 { "SOR", 4, &gv100_disp_core_mthd_sor },
129 { "WINDOW", 8, &gv100_disp_core_mthd_wndw },
130 { "HEAD", 4, &gv100_disp_core_mthd_head },
136 gv100_disp_core_idle(struct nv50_disp_chan *chan)
138 struct nvkm_device *device = chan->disp->base.engine.subdev.device;
139 nvkm_msec(device, 2000,
140 u32 stat = nvkm_rd32(device, 0x610630);
141 if ((stat & 0x001f0000) == 0x000b0000)
148 gv100_disp_core_user(struct nv50_disp_chan *chan, u64 *psize)
155 gv100_disp_core_intr(struct nv50_disp_chan *chan, bool en)
157 struct nvkm_device *device = chan->disp->base.engine.subdev.device;
158 const u32 mask = 0x00000001;
159 const u32 data = en ? mask : 0;
160 nvkm_mask(device, 0x611dac, mask, data);
164 gv100_disp_core_fini(struct nv50_disp_chan *chan)
166 struct nvkm_device *device = chan->disp->base.engine.subdev.device;
167 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000);
168 gv100_disp_core_idle(chan);
169 nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000);
173 gv100_disp_core_init(struct nv50_disp_chan *chan)
175 struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
176 struct nvkm_device *device = subdev->device;
178 nvkm_wr32(device, 0x610b24, lower_32_bits(chan->push));
179 nvkm_wr32(device, 0x610b20, upper_32_bits(chan->push));
180 nvkm_wr32(device, 0x610b28, 0x00000001);
181 nvkm_wr32(device, 0x610b2c, 0x00000040);
183 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000010);
184 nvkm_wr32(device, 0x680000, 0x00000000);
185 nvkm_wr32(device, 0x6104e0, 0x00000013);
186 return gv100_disp_core_idle(chan);
189 static const struct nv50_disp_chan_func
191 .init = gv100_disp_core_init,
192 .fini = gv100_disp_core_fini,
193 .intr = gv100_disp_core_intr,
194 .user = gv100_disp_core_user,
195 .bind = gv100_disp_dmac_bind,
199 gv100_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
200 struct nv50_disp *disp, struct nvkm_object **pobject)
202 return nv50_disp_core_new_(&gv100_disp_core, &gv100_disp_core_mthd,
203 disp, 0, oclass, argv, argc, pobject);