2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_encoder.h"
31 #include <linux/io-mapping.h>
33 /* these defines are made up */
34 #define NV_CIO_CRE_44_HEADA 0x0
35 #define NV_CIO_CRE_44_HEADB 0x3
36 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
37 #define LEGACY_I2C_CRT 0x80
38 #define LEGACY_I2C_PANEL 0x81
39 #define LEGACY_I2C_TV 0x82
43 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
44 #define LOG_OLD_VALUE(x)
51 static bool nv_cksum(const uint8_t *data, unsigned int length)
54 * There's a few checksums in the BIOS, so here's a generic checking
60 for (i = 0; i < length; i++)
70 score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
72 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
73 NV_TRACEWARN(dev, "... BIOS signature not found\n");
77 if (nv_cksum(data, data[2] * 512)) {
78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable ? 2 : 1;
82 NV_TRACE(dev, "... appears to be valid\n");
87 static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 uint32_t pci_nv_20, save_pci_nv_20;
94 if (dev_priv->card_type >= NV_50)
97 pci_nv_20 = NV_PBUS_PCI_NV_20;
99 /* enable ROM access */
100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
101 nvWriteMC(dev, pci_nv_20,
102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
104 /* bail if no rom signature */
105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
122 for (i = 0; i < NV_PROM_SIZE; i++)
123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
126 /* disable ROM access */
127 nvWriteMC(dev, pci_nv_20,
128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
131 static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 uint32_t old_bar0_pramin = 0;
137 if (dev_priv->card_type >= NV_50) {
138 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
140 addr = (u64)nv_rd32(dev, 0x1700) << 16;
144 old_bar0_pramin = nv_rd32(dev, 0x1700);
145 nv_wr32(dev, 0x1700, addr >> 16);
148 /* bail if no rom signature */
149 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
150 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
153 for (i = 0; i < NV_PROM_SIZE; i++)
154 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
157 if (dev_priv->card_type >= NV_50)
158 nv_wr32(dev, 0x1700, old_bar0_pramin);
161 static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
163 void __iomem *rom = NULL;
167 ret = pci_enable_rom(dev->pdev);
171 rom = pci_map_rom(dev->pdev, &rom_len);
174 memcpy_fromio(data, rom, rom_len);
175 pci_unmap_rom(dev->pdev, rom);
178 pci_disable_rom(dev->pdev);
181 static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
185 int size = 64 * 1024;
187 if (!nouveau_acpi_rom_supported(dev->pdev))
190 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
191 ret = nouveau_acpi_get_bios_chunk(data,
202 void (*loadbios)(struct drm_device *, uint8_t *);
206 static struct methods shadow_methods[] = {
207 { "PRAMIN", load_vbios_pramin, true },
208 { "PROM", load_vbios_prom, false },
209 { "PCIROM", load_vbios_pci, true },
210 { "ACPI", load_vbios_acpi, true },
212 #define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
214 static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
216 struct methods *methods = shadow_methods;
218 int scores[NUM_SHADOW_METHODS], i;
221 for (i = 0; i < NUM_SHADOW_METHODS; i++)
222 if (!strcasecmp(nouveau_vbios, methods[i].desc))
225 if (i < NUM_SHADOW_METHODS) {
226 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
229 methods[i].loadbios(dev, data);
230 if (score_vbios(dev, data, methods[i].rw))
234 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
237 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
238 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
240 data[0] = data[1] = 0; /* avoid reuse of previous image */
241 methods[i].loadbios(dev, data);
242 scores[i] = score_vbios(dev, data, methods[i].rw);
243 if (scores[i] == testscore)
247 while (--testscore > 0) {
248 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
249 if (scores[i] == testscore) {
250 NV_TRACE(dev, "Using BIOS image from %s\n",
252 methods[i].loadbios(dev, data);
258 NV_ERROR(dev, "No valid BIOS image found\n");
262 struct init_tbl_entry {
266 * > 0: success, length of opcode
267 * 0: success, but abort further parsing of table (INIT_DONE etc)
268 * < 0: failure, table parsing will be aborted
270 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
273 static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
275 #define MACRO_INDEX_SIZE 2
277 #define CONDITION_SIZE 12
278 #define IO_FLAG_CONDITION_SIZE 9
279 #define IO_CONDITION_SIZE 5
280 #define MEM_INIT_SIZE 66
282 static void still_alive(void)
291 munge_reg(struct nvbios *bios, uint32_t reg)
293 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
294 struct dcb_entry *dcbent = bios->display.output;
296 if (dev_priv->card_type < NV_50)
299 if (reg & 0x80000000) {
300 BUG_ON(bios->display.crtc < 0);
301 reg += bios->display.crtc * 0x800;
304 if (reg & 0x40000000) {
307 reg += (ffs(dcbent->or) - 1) * 0x800;
308 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
317 valid_reg(struct nvbios *bios, uint32_t reg)
319 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
320 struct drm_device *dev = bios->dev;
322 /* C51 has misaligned regs on purpose. Marvellous */
324 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
325 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
327 /* warn on C51 regs that haven't been verified accessible in tracing */
328 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
329 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
330 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
333 if (reg >= (8*1024*1024)) {
334 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
342 valid_idx_port(struct nvbios *bios, uint16_t port)
344 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
345 struct drm_device *dev = bios->dev;
348 * If adding more ports here, the read/write functions below will need
349 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
350 * used for the port in question
352 if (dev_priv->card_type < NV_50) {
353 if (port == NV_CIO_CRX__COLOR)
355 if (port == NV_VIO_SRX)
358 if (port == NV_CIO_CRX__COLOR)
362 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
369 valid_port(struct nvbios *bios, uint16_t port)
371 struct drm_device *dev = bios->dev;
374 * If adding more ports here, the read/write functions below will need
375 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
376 * used for the port in question
378 if (port == NV_VIO_VSE2)
381 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
387 bios_rd32(struct nvbios *bios, uint32_t reg)
391 reg = munge_reg(bios, reg);
392 if (!valid_reg(bios, reg))
396 * C51 sometimes uses regs with bit0 set in the address. For these
397 * cases there should exist a translation in a BIOS table to an IO
398 * port address which the BIOS uses for accessing the reg
400 * These only seem to appear for the power control regs to a flat panel,
401 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
402 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
403 * suspend-resume mmio trace from a C51 will be required to see if this
404 * is true for the power microcode in 0x14.., or whether the direct IO
405 * port access method is needed
410 data = nv_rd32(bios->dev, reg);
412 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
418 bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
420 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
422 reg = munge_reg(bios, reg);
423 if (!valid_reg(bios, reg))
426 /* see note in bios_rd32 */
430 LOG_OLD_VALUE(bios_rd32(bios, reg));
431 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
433 if (dev_priv->vbios.execute) {
435 nv_wr32(bios->dev, reg, data);
440 bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
442 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
443 struct drm_device *dev = bios->dev;
446 if (!valid_idx_port(bios, port))
449 if (dev_priv->card_type < NV_50) {
450 if (port == NV_VIO_SRX)
451 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
452 else /* assume NV_CIO_CRX__COLOR */
453 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
457 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
458 data = (data32 >> ((index & 3) << 3)) & 0xff;
461 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
462 "Head: 0x%02X, Data: 0x%02X\n",
463 port, index, bios->state.crtchead, data);
468 bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
470 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
471 struct drm_device *dev = bios->dev;
473 if (!valid_idx_port(bios, port))
477 * The current head is maintained in the nvbios member state.crtchead.
478 * We trap changes to CR44 and update the head variable and hence the
479 * register set written.
480 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
481 * of the write, and to head1 after the write
483 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
484 data != NV_CIO_CRE_44_HEADB)
485 bios->state.crtchead = 0;
487 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
488 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
489 "Head: 0x%02X, Data: 0x%02X\n",
490 port, index, bios->state.crtchead, data);
492 if (bios->execute && dev_priv->card_type < NV_50) {
494 if (port == NV_VIO_SRX)
495 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
496 else /* assume NV_CIO_CRX__COLOR */
497 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
500 uint32_t data32, shift = (index & 3) << 3;
504 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
505 data32 &= ~(0xff << shift);
506 data32 |= (data << shift);
507 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
510 if (port == NV_CIO_CRX__COLOR &&
511 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
512 bios->state.crtchead = 1;
516 bios_port_rd(struct nvbios *bios, uint16_t port)
518 uint8_t data, head = bios->state.crtchead;
520 if (!valid_port(bios, port))
523 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
525 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
532 bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
534 int head = bios->state.crtchead;
536 if (!valid_port(bios, port))
539 LOG_OLD_VALUE(bios_port_rd(bios, port));
540 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
547 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
551 io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
554 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
555 * for the CRTC index; 1 byte for the mask to apply to the value
556 * retrieved from the CRTC; 1 byte for the shift right to apply to the
557 * masked CRTC value; 2 bytes for the offset to the flag array, to
558 * which the shifted value is added; 1 byte for the mask applied to the
559 * value read from the flag array; and 1 byte for the value to compare
560 * against the masked byte from the flag table.
563 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
564 uint16_t crtcport = ROM16(bios->data[condptr]);
565 uint8_t crtcindex = bios->data[condptr + 2];
566 uint8_t mask = bios->data[condptr + 3];
567 uint8_t shift = bios->data[condptr + 4];
568 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
569 uint8_t flagarraymask = bios->data[condptr + 7];
570 uint8_t cmpval = bios->data[condptr + 8];
573 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
574 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
576 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
578 data = bios_idxprt_rd(bios, crtcport, crtcindex);
580 data = bios->data[flagarray + ((data & mask) >> shift)];
581 data &= flagarraymask;
583 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
584 offset, data, cmpval);
586 return (data == cmpval);
590 bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
593 * The condition table entry has 4 bytes for the address of the
594 * register to check, 4 bytes for a mask to apply to the register and
595 * 4 for a test comparison value
598 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
599 uint32_t reg = ROM32(bios->data[condptr]);
600 uint32_t mask = ROM32(bios->data[condptr + 4]);
601 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
604 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
605 offset, cond, reg, mask);
607 data = bios_rd32(bios, reg) & mask;
609 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
610 offset, data, cmpval);
612 return (data == cmpval);
616 io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
619 * The IO condition entry has 2 bytes for the IO port address; 1 byte
620 * for the index to write to io_port; 1 byte for the mask to apply to
621 * the byte read from io_port+1; and 1 byte for the value to compare
622 * against the masked byte.
625 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
626 uint16_t io_port = ROM16(bios->data[condptr]);
627 uint8_t port_index = bios->data[condptr + 2];
628 uint8_t mask = bios->data[condptr + 3];
629 uint8_t cmpval = bios->data[condptr + 4];
631 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
633 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
634 offset, data, cmpval);
636 return (data == cmpval);
640 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
642 struct drm_nouveau_private *dev_priv = dev->dev_private;
643 struct nouveau_pll_vals pll;
644 struct pll_lims pll_limits;
645 u32 ctrl, mask, coef;
648 ret = get_pll_limits(dev, reg, &pll_limits);
652 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
656 coef = pll.N1 << 8 | pll.M1;
657 ctrl = pll.log2P << 16;
659 if (reg == 0x004008) {
661 ctrl |= (pll_limits.log2p_bias << 19);
662 ctrl |= (pll.log2P << 22);
665 if (!dev_priv->vbios.execute)
668 nv_mask(dev, reg + 0, mask, ctrl);
669 nv_wr32(dev, reg + 4, coef);
674 setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
676 struct drm_device *dev = bios->dev;
677 struct drm_nouveau_private *dev_priv = dev->dev_private;
679 struct pll_lims pll_lim;
680 struct nouveau_pll_vals pllvals;
683 if (dev_priv->card_type >= NV_50)
684 return nv50_pll_set(dev, reg, clk);
686 /* high regs (such as in the mac g5 table) are not -= 4 */
687 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
691 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
697 nouveau_hw_setpll(dev, reg, &pllvals);
703 static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
705 struct drm_nouveau_private *dev_priv = dev->dev_private;
706 struct nvbios *bios = &dev_priv->vbios;
709 * For the results of this function to be correct, CR44 must have been
710 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
711 * and the DCB table parsed, before the script calling the function is
712 * run. run_digital_op_script is example of how to do such setup
715 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
717 if (dcb_entry > bios->dcb.entries) {
718 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
719 "(%02X)\n", dcb_entry);
720 dcb_entry = 0x7f; /* unused / invalid marker */
727 read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
729 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
730 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
731 int recordoffset = 0, rdofs = 1, wrofs = 0;
732 uint8_t port_type = 0;
737 if (dcb_version >= 0x30) {
738 if (i2ctable[0] != dcb_version) /* necessary? */
740 "DCB I2C table version mismatch (%02X vs %02X)\n",
741 i2ctable[0], dcb_version);
742 dcb_i2c_ver = i2ctable[0];
743 headerlen = i2ctable[1];
744 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
745 i2c_entries = i2ctable[2];
748 "DCB I2C table has more entries than indexable "
749 "(%d entries, max %d)\n", i2ctable[2],
750 DCB_MAX_NUM_I2C_ENTRIES);
751 entry_len = i2ctable[3];
752 /* [4] is i2c_default_indices, read in parse_dcb_table() */
755 * It's your own fault if you call this function on a DCB 1.1 BIOS --
756 * the test below is for DCB 1.2
758 if (dcb_version < 0x14) {
766 if (index >= i2c_entries) {
767 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
771 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
772 NV_ERROR(dev, "DCB I2C entry invalid\n");
776 if (dcb_i2c_ver >= 0x30) {
777 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
780 * Fixup for chips using same address offset for read and
783 if (port_type == 4) /* seen on C51 */
785 if (port_type >= 5) /* G80+ */
789 if (dcb_i2c_ver >= 0x40) {
790 if (port_type != 5 && port_type != 6)
791 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
793 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
796 i2c->port_type = port_type;
797 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
798 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
803 static struct nouveau_i2c_chan *
804 init_i2c_device_find(struct drm_device *dev, int i2c_index)
806 struct drm_nouveau_private *dev_priv = dev->dev_private;
807 struct dcb_table *dcb = &dev_priv->vbios.dcb;
809 if (i2c_index == 0xff) {
810 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
811 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
812 int default_indices = dcb->i2c_default_indices;
814 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
817 i2c_index = (default_indices >> shift) & 0xf;
819 if (i2c_index == 0x80) /* g80+ */
820 i2c_index = dcb->i2c_default_indices & 0xf;
822 if (i2c_index == 0x81)
823 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
825 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
826 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
830 /* Make sure i2c table entry has been parsed, it may not
831 * have been if this is a bus not referenced by a DCB encoder
833 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
834 i2c_index, &dcb->i2c[i2c_index]);
836 return nouveau_i2c_find(dev, i2c_index);
840 get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
843 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
844 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
845 * CR58 for CR57 = 0 to index a table of offsets to the basic
847 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
848 * CR58 for CR57 = 0 to index a table of offsets to the basic
849 * 0x6808b0 address, and then flip the offset by 8.
852 struct drm_nouveau_private *dev_priv = dev->dev_private;
853 struct nvbios *bios = &dev_priv->vbios;
854 const int pramdac_offset[13] = {
855 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
856 const uint32_t pramdac_table[4] = {
857 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
860 int dcb_entry, dacoffset;
862 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
863 dcb_entry = dcb_entry_idx_from_crtchead(dev);
864 if (dcb_entry == 0x7f)
866 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
869 return 0x6808b0 + dacoffset;
871 if (mlv >= ARRAY_SIZE(pramdac_table)) {
872 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
876 return pramdac_table[mlv];
881 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
882 struct init_exec *iexec)
885 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
887 * offset (8 bit): opcode
888 * offset + 1 (16 bit): CRTC port
889 * offset + 3 (8 bit): CRTC index
890 * offset + 4 (8 bit): mask
891 * offset + 5 (8 bit): shift
892 * offset + 6 (8 bit): count
893 * offset + 7 (32 bit): register
894 * offset + 11 (32 bit): configuration 1
897 * Starting at offset + 11 there are "count" 32 bit values.
898 * To find out which value to use read index "CRTC index" on "CRTC
899 * port", AND this value with "mask" and then bit shift right "shift"
900 * bits. Read the appropriate value using this index and write to
904 uint16_t crtcport = ROM16(bios->data[offset + 1]);
905 uint8_t crtcindex = bios->data[offset + 3];
906 uint8_t mask = bios->data[offset + 4];
907 uint8_t shift = bios->data[offset + 5];
908 uint8_t count = bios->data[offset + 6];
909 uint32_t reg = ROM32(bios->data[offset + 7]);
912 int len = 11 + count * 4;
917 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
918 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
919 offset, crtcport, crtcindex, mask, shift, count, reg);
921 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
922 if (config > count) {
924 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
925 offset, config, count);
929 configval = ROM32(bios->data[offset + 11 + config * 4]);
931 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
933 bios_wr32(bios, reg, configval);
939 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
942 * INIT_REPEAT opcode: 0x33 ('3')
944 * offset (8 bit): opcode
945 * offset + 1 (8 bit): count
947 * Execute script following this opcode up to INIT_REPEAT_END
951 uint8_t count = bios->data[offset + 1];
954 /* no iexec->execute check by design */
956 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
959 iexec->repeat = true;
962 * count - 1, as the script block will execute once when we leave this
963 * opcode -- this is compatible with bios behaviour as:
964 * a) the block is always executed at least once, even if count == 0
965 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
968 for (i = 0; i < count - 1; i++)
969 parse_init_table(bios, offset + 2, iexec);
971 iexec->repeat = false;
977 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
978 struct init_exec *iexec)
981 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
983 * offset (8 bit): opcode
984 * offset + 1 (16 bit): CRTC port
985 * offset + 3 (8 bit): CRTC index
986 * offset + 4 (8 bit): mask
987 * offset + 5 (8 bit): shift
988 * offset + 6 (8 bit): IO flag condition index
989 * offset + 7 (8 bit): count
990 * offset + 8 (32 bit): register
991 * offset + 12 (16 bit): frequency 1
994 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
995 * Set PLL register "register" to coefficients for frequency n,
996 * selected by reading index "CRTC index" of "CRTC port" ANDed with
997 * "mask" and shifted right by "shift".
999 * If "IO flag condition index" > 0, and condition met, double
1000 * frequency before setting it.
1003 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1004 uint8_t crtcindex = bios->data[offset + 3];
1005 uint8_t mask = bios->data[offset + 4];
1006 uint8_t shift = bios->data[offset + 5];
1007 int8_t io_flag_condition_idx = bios->data[offset + 6];
1008 uint8_t count = bios->data[offset + 7];
1009 uint32_t reg = ROM32(bios->data[offset + 8]);
1012 int len = 12 + count * 2;
1014 if (!iexec->execute)
1017 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1018 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1019 "Count: 0x%02X, Reg: 0x%08X\n",
1020 offset, crtcport, crtcindex, mask, shift,
1021 io_flag_condition_idx, count, reg);
1023 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1024 if (config > count) {
1026 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1027 offset, config, count);
1031 freq = ROM16(bios->data[offset + 12 + config * 2]);
1033 if (io_flag_condition_idx > 0) {
1034 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1035 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1036 "frequency doubled\n", offset);
1039 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1040 "frequency unchanged\n", offset);
1043 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1044 offset, reg, config, freq);
1046 setPLL(bios, reg, freq * 10);
1052 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1055 * INIT_END_REPEAT opcode: 0x36 ('6')
1057 * offset (8 bit): opcode
1059 * Marks the end of the block for INIT_REPEAT to repeat
1062 /* no iexec->execute check by design */
1065 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1066 * we're not in repeat mode
1075 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1078 * INIT_COPY opcode: 0x37 ('7')
1080 * offset (8 bit): opcode
1081 * offset + 1 (32 bit): register
1082 * offset + 5 (8 bit): shift
1083 * offset + 6 (8 bit): srcmask
1084 * offset + 7 (16 bit): CRTC port
1085 * offset + 9 (8 bit): CRTC index
1086 * offset + 10 (8 bit): mask
1088 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1089 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1093 uint32_t reg = ROM32(bios->data[offset + 1]);
1094 uint8_t shift = bios->data[offset + 5];
1095 uint8_t srcmask = bios->data[offset + 6];
1096 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1097 uint8_t crtcindex = bios->data[offset + 9];
1098 uint8_t mask = bios->data[offset + 10];
1102 if (!iexec->execute)
1105 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1106 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1107 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1109 data = bios_rd32(bios, reg);
1114 data <<= (0x100 - shift);
1118 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1119 crtcdata |= (uint8_t)data;
1120 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1126 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1129 * INIT_NOT opcode: 0x38 ('8')
1131 * offset (8 bit): opcode
1133 * Invert the current execute / no-execute condition (i.e. "else")
1136 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1138 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1140 iexec->execute = !iexec->execute;
1145 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1146 struct init_exec *iexec)
1149 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1151 * offset (8 bit): opcode
1152 * offset + 1 (8 bit): condition number
1154 * Check condition "condition number" in the IO flag condition table.
1155 * If condition not met skip subsequent opcodes until condition is
1156 * inverted (INIT_NOT), or we hit INIT_RESUME
1159 uint8_t cond = bios->data[offset + 1];
1161 if (!iexec->execute)
1164 if (io_flag_condition_met(bios, offset, cond))
1165 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1167 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1168 iexec->execute = false;
1175 init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1178 * INIT_DP_CONDITION opcode: 0x3A ('')
1180 * offset (8 bit): opcode
1181 * offset + 1 (8 bit): "sub" opcode
1182 * offset + 2 (8 bit): unknown
1186 struct dcb_entry *dcb = bios->display.output;
1187 struct drm_device *dev = bios->dev;
1188 uint8_t cond = bios->data[offset + 1];
1189 uint8_t *table, *entry;
1191 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1193 if (!iexec->execute)
1196 table = nouveau_dp_bios_data(dev, dcb, &entry);
1203 struct dcb_connector_table_entry *ent =
1204 &bios->dcb.connector.entry[dcb->connector];
1206 if (ent->type != DCB_CONNECTOR_eDP)
1207 iexec->execute = false;
1212 if (!(entry[5] & cond))
1213 iexec->execute = false;
1217 struct nouveau_i2c_chan *auxch;
1220 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1222 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1226 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1228 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1233 iexec->execute = false;
1237 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1242 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1244 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1250 init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1253 * INIT_3B opcode: 0x3B ('')
1255 * offset (8 bit): opcode
1256 * offset + 1 (8 bit): crtc index
1260 uint8_t or = ffs(bios->display.output->or) - 1;
1261 uint8_t index = bios->data[offset + 1];
1264 if (!iexec->execute)
1267 data = bios_idxprt_rd(bios, 0x3d4, index);
1268 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1273 init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1276 * INIT_3C opcode: 0x3C ('')
1278 * offset (8 bit): opcode
1279 * offset + 1 (8 bit): crtc index
1283 uint8_t or = ffs(bios->display.output->or) - 1;
1284 uint8_t index = bios->data[offset + 1];
1287 if (!iexec->execute)
1290 data = bios_idxprt_rd(bios, 0x3d4, index);
1291 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1296 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1297 struct init_exec *iexec)
1300 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1302 * offset (8 bit): opcode
1303 * offset + 1 (32 bit): control register
1304 * offset + 5 (32 bit): data register
1305 * offset + 9 (32 bit): mask
1306 * offset + 13 (32 bit): data
1307 * offset + 17 (8 bit): count
1308 * offset + 18 (8 bit): address 1
1309 * offset + 19 (8 bit): data 1
1312 * For each of "count" address and data pairs, write "data n" to
1313 * "data register", read the current value of "control register",
1314 * and write it back once ANDed with "mask", ORed with "data",
1315 * and ORed with "address n"
1318 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1319 uint32_t datareg = ROM32(bios->data[offset + 5]);
1320 uint32_t mask = ROM32(bios->data[offset + 9]);
1321 uint32_t data = ROM32(bios->data[offset + 13]);
1322 uint8_t count = bios->data[offset + 17];
1323 int len = 18 + count * 2;
1327 if (!iexec->execute)
1330 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1331 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1332 offset, controlreg, datareg, mask, data, count);
1334 for (i = 0; i < count; i++) {
1335 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1336 uint8_t instdata = bios->data[offset + 19 + i * 2];
1338 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1339 offset, instaddress, instdata);
1341 bios_wr32(bios, datareg, instdata);
1342 value = bios_rd32(bios, controlreg) & mask;
1344 value |= instaddress;
1345 bios_wr32(bios, controlreg, value);
1352 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1353 struct init_exec *iexec)
1356 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1358 * offset (8 bit): opcode
1359 * offset + 1 (16 bit): CRTC port
1360 * offset + 3 (8 bit): CRTC index
1361 * offset + 4 (8 bit): mask
1362 * offset + 5 (8 bit): shift
1363 * offset + 6 (8 bit): count
1364 * offset + 7 (32 bit): register
1365 * offset + 11 (32 bit): frequency 1
1368 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1369 * Set PLL register "register" to coefficients for frequency n,
1370 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1371 * "mask" and shifted right by "shift".
1374 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1375 uint8_t crtcindex = bios->data[offset + 3];
1376 uint8_t mask = bios->data[offset + 4];
1377 uint8_t shift = bios->data[offset + 5];
1378 uint8_t count = bios->data[offset + 6];
1379 uint32_t reg = ROM32(bios->data[offset + 7]);
1380 int len = 11 + count * 4;
1384 if (!iexec->execute)
1387 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1388 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1389 offset, crtcport, crtcindex, mask, shift, count, reg);
1394 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1395 if (config > count) {
1397 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1398 offset, config, count);
1402 freq = ROM32(bios->data[offset + 11 + config * 4]);
1404 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1405 offset, reg, config, freq);
1407 setPLL(bios, reg, freq);
1413 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1416 * INIT_PLL2 opcode: 0x4B ('K')
1418 * offset (8 bit): opcode
1419 * offset + 1 (32 bit): register
1420 * offset + 5 (32 bit): freq
1422 * Set PLL register "register" to coefficients for frequency "freq"
1425 uint32_t reg = ROM32(bios->data[offset + 1]);
1426 uint32_t freq = ROM32(bios->data[offset + 5]);
1428 if (!iexec->execute)
1431 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1434 setPLL(bios, reg, freq);
1439 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1442 * INIT_I2C_BYTE opcode: 0x4C ('L')
1444 * offset (8 bit): opcode
1445 * offset + 1 (8 bit): DCB I2C table entry index
1446 * offset + 2 (8 bit): I2C slave address
1447 * offset + 3 (8 bit): count
1448 * offset + 4 (8 bit): I2C register 1
1449 * offset + 5 (8 bit): mask 1
1450 * offset + 6 (8 bit): data 1
1453 * For each of "count" registers given by "I2C register n" on the device
1454 * addressed by "I2C slave address" on the I2C bus given by
1455 * "DCB I2C table entry index", read the register, AND the result with
1456 * "mask n" and OR it with "data n" before writing it back to the device
1459 struct drm_device *dev = bios->dev;
1460 uint8_t i2c_index = bios->data[offset + 1];
1461 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1462 uint8_t count = bios->data[offset + 3];
1463 struct nouveau_i2c_chan *chan;
1464 int len = 4 + count * 3;
1467 if (!iexec->execute)
1470 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1472 offset, i2c_index, i2c_address, count);
1474 chan = init_i2c_device_find(dev, i2c_index);
1476 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1480 for (i = 0; i < count; i++) {
1481 uint8_t reg = bios->data[offset + 4 + i * 3];
1482 uint8_t mask = bios->data[offset + 5 + i * 3];
1483 uint8_t data = bios->data[offset + 6 + i * 3];
1484 union i2c_smbus_data val;
1486 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1487 I2C_SMBUS_READ, reg,
1488 I2C_SMBUS_BYTE_DATA, &val);
1490 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1494 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1495 "Mask: 0x%02X, Data: 0x%02X\n",
1496 offset, reg, val.byte, mask, data);
1503 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1504 I2C_SMBUS_WRITE, reg,
1505 I2C_SMBUS_BYTE_DATA, &val);
1507 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1516 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1519 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1521 * offset (8 bit): opcode
1522 * offset + 1 (8 bit): DCB I2C table entry index
1523 * offset + 2 (8 bit): I2C slave address
1524 * offset + 3 (8 bit): count
1525 * offset + 4 (8 bit): I2C register 1
1526 * offset + 5 (8 bit): data 1
1529 * For each of "count" registers given by "I2C register n" on the device
1530 * addressed by "I2C slave address" on the I2C bus given by
1531 * "DCB I2C table entry index", set the register to "data n"
1534 struct drm_device *dev = bios->dev;
1535 uint8_t i2c_index = bios->data[offset + 1];
1536 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1537 uint8_t count = bios->data[offset + 3];
1538 struct nouveau_i2c_chan *chan;
1539 int len = 4 + count * 2;
1542 if (!iexec->execute)
1545 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1547 offset, i2c_index, i2c_address, count);
1549 chan = init_i2c_device_find(dev, i2c_index);
1551 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1555 for (i = 0; i < count; i++) {
1556 uint8_t reg = bios->data[offset + 4 + i * 2];
1557 union i2c_smbus_data val;
1559 val.byte = bios->data[offset + 5 + i * 2];
1561 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1562 offset, reg, val.byte);
1567 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1568 I2C_SMBUS_WRITE, reg,
1569 I2C_SMBUS_BYTE_DATA, &val);
1571 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1580 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1583 * INIT_ZM_I2C opcode: 0x4E ('N')
1585 * offset (8 bit): opcode
1586 * offset + 1 (8 bit): DCB I2C table entry index
1587 * offset + 2 (8 bit): I2C slave address
1588 * offset + 3 (8 bit): count
1589 * offset + 4 (8 bit): data 1
1592 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1593 * address" on the I2C bus given by "DCB I2C table entry index"
1596 struct drm_device *dev = bios->dev;
1597 uint8_t i2c_index = bios->data[offset + 1];
1598 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1599 uint8_t count = bios->data[offset + 3];
1600 int len = 4 + count;
1601 struct nouveau_i2c_chan *chan;
1606 if (!iexec->execute)
1609 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1611 offset, i2c_index, i2c_address, count);
1613 chan = init_i2c_device_find(dev, i2c_index);
1615 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1619 for (i = 0; i < count; i++) {
1620 data[i] = bios->data[offset + 4 + i];
1622 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1625 if (bios->execute) {
1626 msg.addr = i2c_address;
1630 ret = i2c_transfer(&chan->adapter, &msg, 1);
1632 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1641 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1644 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1646 * offset (8 bit): opcode
1647 * offset + 1 (8 bit): magic lookup value
1648 * offset + 2 (8 bit): TMDS address
1649 * offset + 3 (8 bit): mask
1650 * offset + 4 (8 bit): data
1652 * Read the data reg for TMDS address "TMDS address", AND it with mask
1653 * and OR it with data, then write it back
1654 * "magic lookup value" determines which TMDS base address register is
1655 * used -- see get_tmds_index_reg()
1658 struct drm_device *dev = bios->dev;
1659 uint8_t mlv = bios->data[offset + 1];
1660 uint32_t tmdsaddr = bios->data[offset + 2];
1661 uint8_t mask = bios->data[offset + 3];
1662 uint8_t data = bios->data[offset + 4];
1663 uint32_t reg, value;
1665 if (!iexec->execute)
1668 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1669 "Mask: 0x%02X, Data: 0x%02X\n",
1670 offset, mlv, tmdsaddr, mask, data);
1672 reg = get_tmds_index_reg(bios->dev, mlv);
1674 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1678 bios_wr32(bios, reg,
1679 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1680 value = (bios_rd32(bios, reg + 4) & mask) | data;
1681 bios_wr32(bios, reg + 4, value);
1682 bios_wr32(bios, reg, tmdsaddr);
1688 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1689 struct init_exec *iexec)
1692 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1694 * offset (8 bit): opcode
1695 * offset + 1 (8 bit): magic lookup value
1696 * offset + 2 (8 bit): count
1697 * offset + 3 (8 bit): addr 1
1698 * offset + 4 (8 bit): data 1
1701 * For each of "count" TMDS address and data pairs write "data n" to
1702 * "addr n". "magic lookup value" determines which TMDS base address
1703 * register is used -- see get_tmds_index_reg()
1706 struct drm_device *dev = bios->dev;
1707 uint8_t mlv = bios->data[offset + 1];
1708 uint8_t count = bios->data[offset + 2];
1709 int len = 3 + count * 2;
1713 if (!iexec->execute)
1716 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1717 offset, mlv, count);
1719 reg = get_tmds_index_reg(bios->dev, mlv);
1721 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1725 for (i = 0; i < count; i++) {
1726 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1727 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1729 bios_wr32(bios, reg + 4, tmdsdata);
1730 bios_wr32(bios, reg, tmdsaddr);
1737 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1738 struct init_exec *iexec)
1741 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1743 * offset (8 bit): opcode
1744 * offset + 1 (8 bit): CRTC index1
1745 * offset + 2 (8 bit): CRTC index2
1746 * offset + 3 (8 bit): baseaddr
1747 * offset + 4 (8 bit): count
1748 * offset + 5 (8 bit): data 1
1751 * For each of "count" address and data pairs, write "baseaddr + n" to
1752 * "CRTC index1" and "data n" to "CRTC index2"
1753 * Once complete, restore initial value read from "CRTC index1"
1755 uint8_t crtcindex1 = bios->data[offset + 1];
1756 uint8_t crtcindex2 = bios->data[offset + 2];
1757 uint8_t baseaddr = bios->data[offset + 3];
1758 uint8_t count = bios->data[offset + 4];
1759 int len = 5 + count;
1760 uint8_t oldaddr, data;
1763 if (!iexec->execute)
1766 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1767 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1768 offset, crtcindex1, crtcindex2, baseaddr, count);
1770 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1772 for (i = 0; i < count; i++) {
1773 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1775 data = bios->data[offset + 5 + i];
1776 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1779 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1785 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1788 * INIT_CR opcode: 0x52 ('R')
1790 * offset (8 bit): opcode
1791 * offset + 1 (8 bit): CRTC index
1792 * offset + 2 (8 bit): mask
1793 * offset + 3 (8 bit): data
1795 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1796 * data back to "CRTC index"
1799 uint8_t crtcindex = bios->data[offset + 1];
1800 uint8_t mask = bios->data[offset + 2];
1801 uint8_t data = bios->data[offset + 3];
1804 if (!iexec->execute)
1807 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1808 offset, crtcindex, mask, data);
1810 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1812 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1818 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1821 * INIT_ZM_CR opcode: 0x53 ('S')
1823 * offset (8 bit): opcode
1824 * offset + 1 (8 bit): CRTC index
1825 * offset + 2 (8 bit): value
1827 * Assign "value" to CRTC register with index "CRTC index".
1830 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1831 uint8_t data = bios->data[offset + 2];
1833 if (!iexec->execute)
1836 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1842 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1845 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1847 * offset (8 bit): opcode
1848 * offset + 1 (8 bit): count
1849 * offset + 2 (8 bit): CRTC index 1
1850 * offset + 3 (8 bit): value 1
1853 * For "count", assign "value n" to CRTC register with index
1857 uint8_t count = bios->data[offset + 1];
1858 int len = 2 + count * 2;
1861 if (!iexec->execute)
1864 for (i = 0; i < count; i++)
1865 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1871 init_condition_time(struct nvbios *bios, uint16_t offset,
1872 struct init_exec *iexec)
1875 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1877 * offset (8 bit): opcode
1878 * offset + 1 (8 bit): condition number
1879 * offset + 2 (8 bit): retries / 50
1881 * Check condition "condition number" in the condition table.
1882 * Bios code then sleeps for 2ms if the condition is not met, and
1883 * repeats up to "retries" times, but on one C51 this has proved
1884 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1885 * this, and bail after "retries" times, or 2s, whichever is less.
1886 * If still not met after retries, clear execution flag for this table.
1889 uint8_t cond = bios->data[offset + 1];
1890 uint16_t retries = bios->data[offset + 2] * 50;
1893 if (!iexec->execute)
1899 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1900 offset, cond, retries);
1902 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1905 for (cnt = 0; cnt < retries; cnt++) {
1906 if (bios_condition_met(bios, offset, cond)) {
1907 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1911 BIOSLOG(bios, "0x%04X: "
1912 "Condition not met, sleeping for 20ms\n",
1918 if (!bios_condition_met(bios, offset, cond)) {
1920 "0x%04X: Condition still not met after %dms, "
1921 "skipping following opcodes\n", offset, 20 * retries);
1922 iexec->execute = false;
1929 init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1932 * INIT_LTIME opcode: 0x57 ('V')
1934 * offset (8 bit): opcode
1935 * offset + 1 (16 bit): time
1937 * Sleep for "time" milliseconds.
1940 unsigned time = ROM16(bios->data[offset + 1]);
1942 if (!iexec->execute)
1945 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
1954 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1955 struct init_exec *iexec)
1958 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1960 * offset (8 bit): opcode
1961 * offset + 1 (32 bit): base register
1962 * offset + 5 (8 bit): count
1963 * offset + 6 (32 bit): value 1
1966 * Starting at offset + 6 there are "count" 32 bit values.
1967 * For "count" iterations set "base register" + 4 * current_iteration
1968 * to "value current_iteration"
1971 uint32_t basereg = ROM32(bios->data[offset + 1]);
1972 uint32_t count = bios->data[offset + 5];
1973 int len = 6 + count * 4;
1976 if (!iexec->execute)
1979 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1980 offset, basereg, count);
1982 for (i = 0; i < count; i++) {
1983 uint32_t reg = basereg + i * 4;
1984 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1986 bios_wr32(bios, reg, data);
1993 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1996 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1998 * offset (8 bit): opcode
1999 * offset + 1 (16 bit): subroutine offset (in bios)
2001 * Calls a subroutine that will execute commands until INIT_DONE
2005 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
2007 if (!iexec->execute)
2010 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
2011 offset, sub_offset);
2013 parse_init_table(bios, sub_offset, iexec);
2015 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
2021 init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2024 * INIT_JUMP opcode: 0x5C ('\')
2026 * offset (8 bit): opcode
2027 * offset + 1 (16 bit): offset (in bios)
2029 * Continue execution of init table from 'offset'
2032 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
2034 if (!iexec->execute)
2037 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
2038 return jmp_offset - offset;
2042 init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2045 * INIT_I2C_IF opcode: 0x5E ('^')
2047 * offset (8 bit): opcode
2048 * offset + 1 (8 bit): DCB I2C table entry index
2049 * offset + 2 (8 bit): I2C slave address
2050 * offset + 3 (8 bit): I2C register
2051 * offset + 4 (8 bit): mask
2052 * offset + 5 (8 bit): data
2054 * Read the register given by "I2C register" on the device addressed
2055 * by "I2C slave address" on the I2C bus given by "DCB I2C table
2056 * entry index". Compare the result AND "mask" to "data".
2057 * If they're not equal, skip subsequent opcodes until condition is
2058 * inverted (INIT_NOT), or we hit INIT_RESUME
2061 uint8_t i2c_index = bios->data[offset + 1];
2062 uint8_t i2c_address = bios->data[offset + 2] >> 1;
2063 uint8_t reg = bios->data[offset + 3];
2064 uint8_t mask = bios->data[offset + 4];
2065 uint8_t data = bios->data[offset + 5];
2066 struct nouveau_i2c_chan *chan;
2067 union i2c_smbus_data val;
2070 /* no execute check by design */
2072 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2073 offset, i2c_index, i2c_address);
2075 chan = init_i2c_device_find(bios->dev, i2c_index);
2079 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
2080 I2C_SMBUS_READ, reg,
2081 I2C_SMBUS_BYTE_DATA, &val);
2083 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2084 "Mask: 0x%02X, Data: 0x%02X\n",
2085 offset, reg, mask, data);
2090 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2091 "Mask: 0x%02X, Data: 0x%02X\n",
2092 offset, reg, val.byte, mask, data);
2094 iexec->execute = ((val.byte & mask) == data);
2100 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2103 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2105 * offset (8 bit): opcode
2106 * offset + 1 (32 bit): src reg
2107 * offset + 5 (8 bit): shift
2108 * offset + 6 (32 bit): src mask
2109 * offset + 10 (32 bit): xor
2110 * offset + 14 (32 bit): dst reg
2111 * offset + 18 (32 bit): dst mask
2113 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2114 * "src mask", then XOR with "xor". Write this OR'd with
2115 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2118 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2119 uint8_t shift = bios->data[offset + 5];
2120 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2121 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2122 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2123 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2124 uint32_t srcvalue, dstvalue;
2126 if (!iexec->execute)
2129 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2130 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2131 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2133 srcvalue = bios_rd32(bios, srcreg);
2138 srcvalue <<= (0x100 - shift);
2140 srcvalue = (srcvalue & srcmask) ^ xor;
2142 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2144 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2150 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2153 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2155 * offset (8 bit): opcode
2156 * offset + 1 (16 bit): CRTC port
2157 * offset + 3 (8 bit): CRTC index
2158 * offset + 4 (8 bit): data
2160 * Write "data" to index "CRTC index" of "CRTC port"
2162 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2163 uint8_t crtcindex = bios->data[offset + 3];
2164 uint8_t data = bios->data[offset + 4];
2166 if (!iexec->execute)
2169 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2175 bios_md32(struct nvbios *bios, uint32_t reg,
2176 uint32_t mask, uint32_t val)
2178 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2182 peek_fb(struct drm_device *dev, struct io_mapping *fb,
2187 if (off < pci_resource_len(dev->pdev, 1)) {
2188 uint8_t __iomem *p =
2189 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2191 val = ioread32(p + (off & ~PAGE_MASK));
2193 io_mapping_unmap_atomic(p);
2200 poke_fb(struct drm_device *dev, struct io_mapping *fb,
2201 uint32_t off, uint32_t val)
2203 if (off < pci_resource_len(dev->pdev, 1)) {
2204 uint8_t __iomem *p =
2205 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2207 iowrite32(val, p + (off & ~PAGE_MASK));
2210 io_mapping_unmap_atomic(p);
2215 read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2216 uint32_t off, uint32_t val)
2218 poke_fb(dev, fb, off, val);
2219 return val == peek_fb(dev, fb, off);
2223 nv04_init_compute_mem(struct nvbios *bios)
2225 struct drm_device *dev = bios->dev;
2226 uint32_t patt = 0xdeadbeef;
2227 struct io_mapping *fb;
2230 /* Map the framebuffer aperture */
2231 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2232 pci_resource_len(dev->pdev, 1));
2236 /* Sequencer and refresh off */
2237 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2238 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2240 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2241 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2242 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2243 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2245 for (i = 0; i < 4; i++)
2246 poke_fb(dev, fb, 4 * i, patt);
2248 poke_fb(dev, fb, 0x400000, patt + 1);
2250 if (peek_fb(dev, fb, 0) == patt + 1) {
2251 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2252 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2253 bios_md32(bios, NV04_PFB_DEBUG_0,
2254 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2256 for (i = 0; i < 4; i++)
2257 poke_fb(dev, fb, 4 * i, patt);
2259 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2260 bios_md32(bios, NV04_PFB_BOOT_0,
2261 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2262 NV04_PFB_BOOT_0_RAM_AMOUNT,
2263 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2265 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2266 (patt & 0xffff0000)) {
2267 bios_md32(bios, NV04_PFB_BOOT_0,
2268 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2269 NV04_PFB_BOOT_0_RAM_AMOUNT,
2270 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2272 } else if (peek_fb(dev, fb, 0) != patt) {
2273 if (read_back_fb(dev, fb, 0x800000, patt))
2274 bios_md32(bios, NV04_PFB_BOOT_0,
2275 NV04_PFB_BOOT_0_RAM_AMOUNT,
2276 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2278 bios_md32(bios, NV04_PFB_BOOT_0,
2279 NV04_PFB_BOOT_0_RAM_AMOUNT,
2280 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2282 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2283 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2285 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2286 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2287 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2291 /* Refresh on, sequencer on */
2292 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2293 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2295 io_mapping_free(fb);
2299 static const uint8_t *
2300 nv05_memory_config(struct nvbios *bios)
2302 /* Defaults for BIOSes lacking a memory config table */
2303 static const uint8_t default_config_tab[][2] = {
2313 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2314 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2316 if (bios->legacy.mem_init_tbl_ptr)
2317 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2319 return default_config_tab[i];
2323 nv05_init_compute_mem(struct nvbios *bios)
2325 struct drm_device *dev = bios->dev;
2326 const uint8_t *ramcfg = nv05_memory_config(bios);
2327 uint32_t patt = 0xdeadbeef;
2328 struct io_mapping *fb;
2331 /* Map the framebuffer aperture */
2332 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2333 pci_resource_len(dev->pdev, 1));
2338 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2340 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2343 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2345 /* If present load the hardcoded scrambling table */
2346 if (bios->legacy.mem_init_tbl_ptr) {
2347 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2348 bios->legacy.mem_init_tbl_ptr + 0x10];
2350 for (i = 0; i < 8; i++)
2351 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2352 ROM32(scramble_tab[i]));
2355 /* Set memory type/width/length defaults depending on the straps */
2356 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2358 if (ramcfg[1] & 0x80)
2359 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2361 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2362 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2364 /* Probe memory bus width */
2365 for (i = 0; i < 4; i++)
2366 poke_fb(dev, fb, 4 * i, patt);
2368 if (peek_fb(dev, fb, 0xc) != patt)
2369 bios_md32(bios, NV04_PFB_BOOT_0,
2370 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2372 /* Probe memory length */
2373 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2375 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2376 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2377 !read_back_fb(dev, fb, 0, ++patt)))
2378 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2379 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2381 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2382 !read_back_fb(dev, fb, 0x800000, ++patt))
2383 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2384 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2386 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2387 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2388 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2392 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2394 io_mapping_free(fb);
2399 nv10_init_compute_mem(struct nvbios *bios)
2401 struct drm_device *dev = bios->dev;
2402 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2403 const int mem_width[] = { 0x10, 0x00, 0x20 };
2404 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2405 uint32_t patt = 0xdeadbeef;
2406 struct io_mapping *fb;
2409 /* Map the framebuffer aperture */
2410 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2411 pci_resource_len(dev->pdev, 1));
2415 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2417 /* Probe memory bus width */
2418 for (i = 0; i < mem_width_count; i++) {
2419 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2421 for (j = 0; j < 4; j++) {
2422 for (k = 0; k < 4; k++)
2423 poke_fb(dev, fb, 0x1c, 0);
2425 poke_fb(dev, fb, 0x1c, patt);
2426 poke_fb(dev, fb, 0x3c, 0);
2428 if (peek_fb(dev, fb, 0x1c) == patt)
2429 goto mem_width_found;
2436 /* Probe amount of installed memory */
2437 for (i = 0; i < 4; i++) {
2438 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2440 poke_fb(dev, fb, off, patt);
2441 poke_fb(dev, fb, 0, 0);
2443 peek_fb(dev, fb, 0);
2444 peek_fb(dev, fb, 0);
2445 peek_fb(dev, fb, 0);
2446 peek_fb(dev, fb, 0);
2448 if (peek_fb(dev, fb, off) == patt)
2452 /* IC missing - disable the upper half memory space. */
2453 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2456 io_mapping_free(fb);
2461 nv20_init_compute_mem(struct nvbios *bios)
2463 struct drm_device *dev = bios->dev;
2464 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2465 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2466 uint32_t amount, off;
2467 struct io_mapping *fb;
2469 /* Map the framebuffer aperture */
2470 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2471 pci_resource_len(dev->pdev, 1));
2475 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2477 /* Allow full addressing */
2478 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2480 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2481 for (off = amount; off > 0x2000000; off -= 0x2000000)
2482 poke_fb(dev, fb, off - 4, off);
2484 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2485 if (amount != peek_fb(dev, fb, amount - 4))
2486 /* IC missing - disable the upper half memory space. */
2487 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2489 io_mapping_free(fb);
2494 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2497 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2499 * offset (8 bit): opcode
2501 * This opcode is meant to set the PFB memory config registers
2502 * appropriately so that we can correctly calculate how much VRAM it
2503 * has (on nv10 and better chipsets the amount of installed VRAM is
2504 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2506 * The implementation of this opcode in general consists of several
2509 * 1) Determination of memory type and density. Only necessary for
2510 * really old chipsets, the memory type reported by the strap bits
2511 * (0x101000) is assumed to be accurate on nv05 and newer.
2513 * 2) Determination of the memory bus width. Usually done by a cunning
2514 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2515 * seeing whether the written values are read back correctly.
2517 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2520 * 3) Determination of how many of the card's RAM pads have ICs
2521 * attached, usually done by a cunning combination of writes to an
2522 * offset slightly less than the maximum memory reported by
2523 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2525 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2526 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2527 * card show nothing being done for this opcode. Why is it still listed
2531 /* no iexec->execute check by design */
2533 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2536 if (dev_priv->chipset >= 0x40 ||
2537 dev_priv->chipset == 0x1a ||
2538 dev_priv->chipset == 0x1f)
2540 else if (dev_priv->chipset >= 0x20 &&
2541 dev_priv->chipset != 0x34)
2542 ret = nv20_init_compute_mem(bios);
2543 else if (dev_priv->chipset >= 0x10)
2544 ret = nv10_init_compute_mem(bios);
2545 else if (dev_priv->chipset >= 0x5)
2546 ret = nv05_init_compute_mem(bios);
2548 ret = nv04_init_compute_mem(bios);
2557 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2560 * INIT_RESET opcode: 0x65 ('e')
2562 * offset (8 bit): opcode
2563 * offset + 1 (32 bit): register
2564 * offset + 5 (32 bit): value1
2565 * offset + 9 (32 bit): value2
2567 * Assign "value1" to "register", then assign "value2" to "register"
2570 uint32_t reg = ROM32(bios->data[offset + 1]);
2571 uint32_t value1 = ROM32(bios->data[offset + 5]);
2572 uint32_t value2 = ROM32(bios->data[offset + 9]);
2573 uint32_t pci_nv_19, pci_nv_20;
2575 /* no iexec->execute check by design */
2577 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2578 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2580 bios_wr32(bios, reg, value1);
2584 bios_wr32(bios, reg, value2);
2585 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2587 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2588 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2589 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2595 init_configure_mem(struct nvbios *bios, uint16_t offset,
2596 struct init_exec *iexec)
2599 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2601 * offset (8 bit): opcode
2603 * Equivalent to INIT_DONE on bios version 3 or greater.
2604 * For early bios versions, sets up the memory registers, using values
2605 * taken from the memory init table
2608 /* no iexec->execute check by design */
2610 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2611 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2614 if (bios->major_version > 2)
2617 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2618 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2620 if (bios->data[meminitoffs] & 1)
2621 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2623 for (reg = ROM32(bios->data[seqtbloffs]);
2625 reg = ROM32(bios->data[seqtbloffs += 4])) {
2629 data = NV04_PFB_PRE_CMD_PRECHARGE;
2632 data = NV04_PFB_PAD_CKE_NORMAL;
2635 data = NV04_PFB_REF_CMD_REFRESH;
2638 data = ROM32(bios->data[meminitdata]);
2640 if (data == 0xffffffff)
2644 bios_wr32(bios, reg, data);
2651 init_configure_clk(struct nvbios *bios, uint16_t offset,
2652 struct init_exec *iexec)
2655 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2657 * offset (8 bit): opcode
2659 * Equivalent to INIT_DONE on bios version 3 or greater.
2660 * For early bios versions, sets up the NVClk and MClk PLLs, using
2661 * values taken from the memory init table
2664 /* no iexec->execute check by design */
2666 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2669 if (bios->major_version > 2)
2672 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2673 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2675 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2676 if (bios->data[meminitoffs] & 1) /* DDR */
2678 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2684 init_configure_preinit(struct nvbios *bios, uint16_t offset,
2685 struct init_exec *iexec)
2688 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2690 * offset (8 bit): opcode
2692 * Equivalent to INIT_DONE on bios version 3 or greater.
2693 * For early bios versions, does early init, loading ram and crystal
2694 * configuration from straps into CR3C
2697 /* no iexec->execute check by design */
2699 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2700 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
2702 if (bios->major_version > 2)
2705 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2706 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2712 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2715 * INIT_IO opcode: 0x69 ('i')
2717 * offset (8 bit): opcode
2718 * offset + 1 (16 bit): CRTC port
2719 * offset + 3 (8 bit): mask
2720 * offset + 4 (8 bit): data
2722 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2725 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2726 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2727 uint8_t mask = bios->data[offset + 3];
2728 uint8_t data = bios->data[offset + 4];
2730 if (!iexec->execute)
2733 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2734 offset, crtcport, mask, data);
2737 * I have no idea what this does, but NVIDIA do this magic sequence
2738 * in the places where this INIT_IO happens..
2740 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2743 bios_wr32(bios, 0x614100, (bios_rd32(
2744 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2746 bios_wr32(bios, 0x00e18c, bios_rd32(
2747 bios, 0x00e18c) | 0x00020000);
2749 bios_wr32(bios, 0x614900, (bios_rd32(
2750 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2752 bios_wr32(bios, 0x000200, bios_rd32(
2753 bios, 0x000200) & ~0x40000000);
2757 bios_wr32(bios, 0x00e18c, bios_rd32(
2758 bios, 0x00e18c) & ~0x00020000);
2760 bios_wr32(bios, 0x000200, bios_rd32(
2761 bios, 0x000200) | 0x40000000);
2763 bios_wr32(bios, 0x614100, 0x00800018);
2764 bios_wr32(bios, 0x614900, 0x00800018);
2768 bios_wr32(bios, 0x614100, 0x10000018);
2769 bios_wr32(bios, 0x614900, 0x10000018);
2771 for (i = 0; i < 3; i++)
2772 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2773 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2775 for (i = 0; i < 2; i++)
2776 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2777 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2779 for (i = 0; i < 3; i++)
2780 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2781 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2783 for (i = 0; i < 2; i++)
2784 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2785 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2787 for (i = 0; i < 2; i++)
2788 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2789 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2793 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2799 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2802 * INIT_SUB opcode: 0x6B ('k')
2804 * offset (8 bit): opcode
2805 * offset + 1 (8 bit): script number
2807 * Execute script number "script number", as a subroutine
2810 uint8_t sub = bios->data[offset + 1];
2812 if (!iexec->execute)
2815 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2817 parse_init_table(bios,
2818 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2821 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2827 init_ram_condition(struct nvbios *bios, uint16_t offset,
2828 struct init_exec *iexec)
2831 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2833 * offset (8 bit): opcode
2834 * offset + 1 (8 bit): mask
2835 * offset + 2 (8 bit): cmpval
2837 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2838 * If condition not met skip subsequent opcodes until condition is
2839 * inverted (INIT_NOT), or we hit INIT_RESUME
2842 uint8_t mask = bios->data[offset + 1];
2843 uint8_t cmpval = bios->data[offset + 2];
2846 if (!iexec->execute)
2849 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
2851 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2852 offset, data, cmpval);
2855 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2857 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2858 iexec->execute = false;
2865 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2868 * INIT_NV_REG opcode: 0x6E ('n')
2870 * offset (8 bit): opcode
2871 * offset + 1 (32 bit): register
2872 * offset + 5 (32 bit): mask
2873 * offset + 9 (32 bit): data
2875 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2878 uint32_t reg = ROM32(bios->data[offset + 1]);
2879 uint32_t mask = ROM32(bios->data[offset + 5]);
2880 uint32_t data = ROM32(bios->data[offset + 9]);
2882 if (!iexec->execute)
2885 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2886 offset, reg, mask, data);
2888 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2894 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2897 * INIT_MACRO opcode: 0x6F ('o')
2899 * offset (8 bit): opcode
2900 * offset + 1 (8 bit): macro number
2902 * Look up macro index "macro number" in the macro index table.
2903 * The macro index table entry has 1 byte for the index in the macro
2904 * table, and 1 byte for the number of times to repeat the macro.
2905 * The macro table entry has 4 bytes for the register address and
2906 * 4 bytes for the value to write to that register
2909 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2910 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2911 uint8_t macro_tbl_idx = bios->data[tmp];
2912 uint8_t count = bios->data[tmp + 1];
2916 if (!iexec->execute)
2919 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2921 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2923 for (i = 0; i < count; i++) {
2924 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2926 reg = ROM32(bios->data[macroentryptr]);
2927 data = ROM32(bios->data[macroentryptr + 4]);
2929 bios_wr32(bios, reg, data);
2936 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2939 * INIT_DONE opcode: 0x71 ('q')
2941 * offset (8 bit): opcode
2943 * End the current script
2946 /* mild retval abuse to stop parsing this table */
2951 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2954 * INIT_RESUME opcode: 0x72 ('r')
2956 * offset (8 bit): opcode
2958 * End the current execute / no-execute condition
2964 iexec->execute = true;
2965 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2971 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2974 * INIT_TIME opcode: 0x74 ('t')
2976 * offset (8 bit): opcode
2977 * offset + 1 (16 bit): time
2979 * Sleep for "time" microseconds.
2982 unsigned time = ROM16(bios->data[offset + 1]);
2984 if (!iexec->execute)
2987 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2993 mdelay((time + 900) / 1000);
2999 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3002 * INIT_CONDITION opcode: 0x75 ('u')
3004 * offset (8 bit): opcode
3005 * offset + 1 (8 bit): condition number
3007 * Check condition "condition number" in the condition table.
3008 * If condition not met skip subsequent opcodes until condition is
3009 * inverted (INIT_NOT), or we hit INIT_RESUME
3012 uint8_t cond = bios->data[offset + 1];
3014 if (!iexec->execute)
3017 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
3019 if (bios_condition_met(bios, offset, cond))
3020 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3022 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3023 iexec->execute = false;
3030 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3033 * INIT_IO_CONDITION opcode: 0x76
3035 * offset (8 bit): opcode
3036 * offset + 1 (8 bit): condition number
3038 * Check condition "condition number" in the io condition table.
3039 * If condition not met skip subsequent opcodes until condition is
3040 * inverted (INIT_NOT), or we hit INIT_RESUME
3043 uint8_t cond = bios->data[offset + 1];
3045 if (!iexec->execute)
3048 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
3050 if (io_condition_met(bios, offset, cond))
3051 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3053 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3054 iexec->execute = false;
3061 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3064 * INIT_INDEX_IO opcode: 0x78 ('x')
3066 * offset (8 bit): opcode
3067 * offset + 1 (16 bit): CRTC port
3068 * offset + 3 (8 bit): CRTC index
3069 * offset + 4 (8 bit): mask
3070 * offset + 5 (8 bit): data
3072 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
3073 * OR with "data", write-back
3076 uint16_t crtcport = ROM16(bios->data[offset + 1]);
3077 uint8_t crtcindex = bios->data[offset + 3];
3078 uint8_t mask = bios->data[offset + 4];
3079 uint8_t data = bios->data[offset + 5];
3082 if (!iexec->execute)
3085 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3087 offset, crtcport, crtcindex, mask, data);
3089 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
3090 bios_idxprt_wr(bios, crtcport, crtcindex, value);
3096 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3099 * INIT_PLL opcode: 0x79 ('y')
3101 * offset (8 bit): opcode
3102 * offset + 1 (32 bit): register
3103 * offset + 5 (16 bit): freq
3105 * Set PLL register "register" to coefficients for frequency (10kHz)
3109 uint32_t reg = ROM32(bios->data[offset + 1]);
3110 uint16_t freq = ROM16(bios->data[offset + 5]);
3112 if (!iexec->execute)
3115 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3117 setPLL(bios, reg, freq * 10);
3123 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3126 * INIT_ZM_REG opcode: 0x7A ('z')
3128 * offset (8 bit): opcode
3129 * offset + 1 (32 bit): register
3130 * offset + 5 (32 bit): value
3132 * Assign "value" to "register"
3135 uint32_t reg = ROM32(bios->data[offset + 1]);
3136 uint32_t value = ROM32(bios->data[offset + 5]);
3138 if (!iexec->execute)
3141 if (reg == 0x000200)
3144 bios_wr32(bios, reg, value);
3150 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3151 struct init_exec *iexec)
3154 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3156 * offset (8 bit): opcode
3157 * offset + 1 (8 bit): PLL type
3158 * offset + 2 (32 bit): frequency 0
3160 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3161 * ram_restrict_table_ptr. The value read from there is used to select
3162 * a frequency from the table starting at 'frequency 0' to be
3163 * programmed into the PLL corresponding to 'type'.
3165 * The PLL limits table on cards using this opcode has a mapping of
3166 * 'type' to the relevant registers.
3169 struct drm_device *dev = bios->dev;
3170 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3171 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3172 uint8_t type = bios->data[offset + 1];
3173 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3174 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
3175 int len = 2 + bios->ram_restrict_group_count * 4;
3178 if (!iexec->execute)
3181 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3182 NV_ERROR(dev, "PLL limits table not version 3.x\n");
3183 return len; /* deliberate, allow default clocks to remain */
3186 entry = pll_limits + pll_limits[1];
3187 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3188 if (entry[0] == type) {
3189 uint32_t reg = ROM32(entry[3]);
3191 BIOSLOG(bios, "0x%04X: "
3192 "Type %02x Reg 0x%08x Freq %dKHz\n",
3193 offset, type, reg, freq);
3195 setPLL(bios, reg, freq);
3200 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
3205 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3208 * INIT_8C opcode: 0x8C ('')
3218 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3221 * INIT_8D opcode: 0x8D ('')
3231 init_gpio_unknv50(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3233 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
3236 /* Not a clue, needs de-magicing */
3237 r = nv50_gpio_ctl[gpio->line >> 4];
3238 s = (gpio->line & 0x0f);
3239 v = bios_rd32(bios, r) & ~(0x00010001 << s);
3240 switch ((gpio->entry & 0x06000000) >> 25) {
3242 v |= (0x00000001 << s);
3245 v |= (0x00010000 << s);
3251 bios_wr32(bios, r, v);
3255 init_gpio_unknvd0(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3259 v = bios_rd32(bios, 0x00d610 + (gpio->line * 4));
3261 v |= (gpio->entry & 0x00ff0000) >> 16;
3262 bios_wr32(bios, 0x00d610 + (gpio->line * 4), v);
3264 i = (gpio->entry & 0x1f000000) >> 24;
3266 v = bios_rd32(bios, 0x00d640 + ((i - 1) * 4));
3269 bios_wr32(bios, 0x00d640 + ((i - 1) * 4), v);
3274 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3277 * INIT_GPIO opcode: 0x8E ('')
3279 * offset (8 bit): opcode
3281 * Loop over all entries in the DCB GPIO table, and initialise
3282 * each GPIO according to various values listed in each entry
3285 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
3286 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
3289 if (dev_priv->card_type < NV_50) {
3290 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
3294 if (!iexec->execute)
3297 for (i = 0; i < bios->dcb.gpio.entries; i++) {
3298 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
3300 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
3302 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
3303 offset, gpio->tag, gpio->state_default);
3308 pgpio->set(bios->dev, gpio->tag, gpio->state_default);
3309 if (dev_priv->card_type < NV_D0)
3310 init_gpio_unknv50(bios, gpio);
3312 init_gpio_unknvd0(bios, gpio);
3319 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3320 struct init_exec *iexec)
3323 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3325 * offset (8 bit): opcode
3326 * offset + 1 (32 bit): reg
3327 * offset + 5 (8 bit): regincrement
3328 * offset + 6 (8 bit): count
3329 * offset + 7 (32 bit): value 1,1
3332 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3333 * ram_restrict_table_ptr. The value read from here is 'n', and
3334 * "value 1,n" gets written to "reg". This repeats "count" times and on
3335 * each iteration 'm', "reg" increases by "regincrement" and
3336 * "value m,n" is used. The extent of n is limited by a number read
3337 * from the 'M' BIT table, herein called "blocklen"
3340 uint32_t reg = ROM32(bios->data[offset + 1]);
3341 uint8_t regincrement = bios->data[offset + 5];
3342 uint8_t count = bios->data[offset + 6];
3343 uint32_t strap_ramcfg, data;
3344 /* previously set by 'M' BIT table */
3345 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3346 int len = 7 + count * blocklen;
3350 /* critical! to know the length of the opcode */;
3353 "0x%04X: Zero block length - has the M table "
3354 "been parsed?\n", offset);
3358 if (!iexec->execute)
3361 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3362 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3364 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3365 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3366 offset, reg, regincrement, count, strap_ramcfg, index);
3368 for (i = 0; i < count; i++) {
3369 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3371 bios_wr32(bios, reg, data);
3373 reg += regincrement;
3380 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3383 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3385 * offset (8 bit): opcode
3386 * offset + 1 (32 bit): src reg
3387 * offset + 5 (32 bit): dst reg
3389 * Put contents of "src reg" into "dst reg"
3392 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3393 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3395 if (!iexec->execute)
3398 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3404 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3405 struct init_exec *iexec)
3408 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3410 * offset (8 bit): opcode
3411 * offset + 1 (32 bit): dst reg
3412 * offset + 5 (8 bit): count
3413 * offset + 6 (32 bit): data 1
3416 * For each of "count" values write "data n" to "dst reg"
3419 uint32_t reg = ROM32(bios->data[offset + 1]);
3420 uint8_t count = bios->data[offset + 5];
3421 int len = 6 + count * 4;
3424 if (!iexec->execute)
3427 for (i = 0; i < count; i++) {
3428 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3429 bios_wr32(bios, reg, data);
3436 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3439 * INIT_RESERVED opcode: 0x92 ('')
3441 * offset (8 bit): opcode
3443 * Seemingly does nothing
3450 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3453 * INIT_96 opcode: 0x96 ('')
3455 * offset (8 bit): opcode
3456 * offset + 1 (32 bit): sreg
3457 * offset + 5 (8 bit): sshift
3458 * offset + 6 (8 bit): smask
3459 * offset + 7 (8 bit): index
3460 * offset + 8 (32 bit): reg
3461 * offset + 12 (32 bit): mask
3462 * offset + 16 (8 bit): shift
3466 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3467 uint32_t reg = ROM32(bios->data[offset + 8]);
3468 uint32_t mask = ROM32(bios->data[offset + 12]);
3471 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3472 if (bios->data[offset + 5] < 0x80)
3473 val >>= bios->data[offset + 5];
3475 val <<= (0x100 - bios->data[offset + 5]);
3476 val &= bios->data[offset + 6];
3478 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3479 val <<= bios->data[offset + 16];
3481 if (!iexec->execute)
3484 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
3489 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3492 * INIT_97 opcode: 0x97 ('')
3494 * offset (8 bit): opcode
3495 * offset + 1 (32 bit): register
3496 * offset + 5 (32 bit): mask
3497 * offset + 9 (32 bit): value
3499 * Adds "value" to "register" preserving the fields specified
3503 uint32_t reg = ROM32(bios->data[offset + 1]);
3504 uint32_t mask = ROM32(bios->data[offset + 5]);
3505 uint32_t add = ROM32(bios->data[offset + 9]);
3508 val = bios_rd32(bios, reg);
3509 val = (val & mask) | ((val + add) & ~mask);
3511 if (!iexec->execute)
3514 bios_wr32(bios, reg, val);
3519 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3522 * INIT_AUXCH opcode: 0x98 ('')
3524 * offset (8 bit): opcode
3525 * offset + 1 (32 bit): address
3526 * offset + 5 (8 bit): count
3527 * offset + 6 (8 bit): mask 0
3528 * offset + 7 (8 bit): data 0
3533 struct drm_device *dev = bios->dev;
3534 struct nouveau_i2c_chan *auxch;
3535 uint32_t addr = ROM32(bios->data[offset + 1]);
3536 uint8_t count = bios->data[offset + 5];
3537 int len = 6 + count * 2;
3540 if (!bios->display.output) {
3541 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
3545 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3547 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3548 bios->display.output->i2c_index);
3552 if (!iexec->execute)
3556 for (i = 0; i < count; i++, offset += 2) {
3559 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3561 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
3565 data &= bios->data[offset + 0];
3566 data |= bios->data[offset + 1];
3568 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3570 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
3579 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3582 * INIT_ZM_AUXCH opcode: 0x99 ('')
3584 * offset (8 bit): opcode
3585 * offset + 1 (32 bit): address
3586 * offset + 5 (8 bit): count
3587 * offset + 6 (8 bit): data 0
3592 struct drm_device *dev = bios->dev;
3593 struct nouveau_i2c_chan *auxch;
3594 uint32_t addr = ROM32(bios->data[offset + 1]);
3595 uint8_t count = bios->data[offset + 5];
3596 int len = 6 + count;
3599 if (!bios->display.output) {
3600 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
3604 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3606 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3607 bios->display.output->i2c_index);
3611 if (!iexec->execute)
3615 for (i = 0; i < count; i++, offset++) {
3616 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3618 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
3627 init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3630 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3632 * offset (8 bit): opcode
3633 * offset + 1 (8 bit): DCB I2C table entry index
3634 * offset + 2 (8 bit): I2C slave address
3635 * offset + 3 (16 bit): I2C register
3636 * offset + 5 (8 bit): mask
3637 * offset + 6 (8 bit): data
3639 * Read the register given by "I2C register" on the device addressed
3640 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3641 * entry index". Compare the result AND "mask" to "data".
3642 * If they're not equal, skip subsequent opcodes until condition is
3643 * inverted (INIT_NOT), or we hit INIT_RESUME
3646 uint8_t i2c_index = bios->data[offset + 1];
3647 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3648 uint8_t reglo = bios->data[offset + 3];
3649 uint8_t reghi = bios->data[offset + 4];
3650 uint8_t mask = bios->data[offset + 5];
3651 uint8_t data = bios->data[offset + 6];
3652 struct nouveau_i2c_chan *chan;
3653 uint8_t buf0[2] = { reghi, reglo };
3655 struct i2c_msg msg[2] = {
3656 { i2c_address, 0, 1, buf0 },
3657 { i2c_address, I2C_M_RD, 1, buf1 },
3661 /* no execute check by design */
3663 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3664 offset, i2c_index, i2c_address);
3666 chan = init_i2c_device_find(bios->dev, i2c_index);
3671 ret = i2c_transfer(&chan->adapter, msg, 2);
3673 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3674 "Mask: 0x%02X, Data: 0x%02X\n",
3675 offset, reghi, reglo, mask, data);
3680 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3681 "Mask: 0x%02X, Data: 0x%02X\n",
3682 offset, reghi, reglo, buf1[0], mask, data);
3684 iexec->execute = ((buf1[0] & mask) == data);
3689 static struct init_tbl_entry itbl_entry[] = {
3690 /* command name , id , length , offset , mult , command handler */
3691 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3692 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3693 { "INIT_REPEAT" , 0x33, init_repeat },
3694 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3695 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3696 { "INIT_COPY" , 0x37, init_copy },
3697 { "INIT_NOT" , 0x38, init_not },
3698 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
3699 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3700 { "INIT_OP_3B" , 0x3B, init_op_3b },
3701 { "INIT_OP_3C" , 0x3C, init_op_3c },
3702 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3703 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3704 { "INIT_PLL2" , 0x4B, init_pll2 },
3705 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3706 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3707 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3708 { "INIT_TMDS" , 0x4F, init_tmds },
3709 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3710 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3711 { "INIT_CR" , 0x52, init_cr },
3712 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3713 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3714 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3715 { "INIT_LTIME" , 0x57, init_ltime },
3716 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3717 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3718 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3719 { "INIT_JUMP" , 0x5C, init_jump },
3720 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3721 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3722 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3723 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3724 { "INIT_RESET" , 0x65, init_reset },
3725 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3726 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3727 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3728 { "INIT_IO" , 0x69, init_io },
3729 { "INIT_SUB" , 0x6B, init_sub },
3730 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3731 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3732 { "INIT_MACRO" , 0x6F, init_macro },
3733 { "INIT_DONE" , 0x71, init_done },
3734 { "INIT_RESUME" , 0x72, init_resume },
3735 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3736 { "INIT_TIME" , 0x74, init_time },
3737 { "INIT_CONDITION" , 0x75, init_condition },
3738 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3739 { "INIT_INDEX_IO" , 0x78, init_index_io },
3740 { "INIT_PLL" , 0x79, init_pll },
3741 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3742 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3743 { "INIT_8C" , 0x8C, init_8c },
3744 { "INIT_8D" , 0x8D, init_8d },
3745 { "INIT_GPIO" , 0x8E, init_gpio },
3746 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3747 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3748 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3749 { "INIT_RESERVED" , 0x92, init_reserved },
3750 { "INIT_96" , 0x96, init_96 },
3751 { "INIT_97" , 0x97, init_97 },
3752 { "INIT_AUXCH" , 0x98, init_auxch },
3753 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3754 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
3758 #define MAX_TABLE_OPS 1000
3761 parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3764 * Parses all commands in an init table.
3766 * We start out executing all commands found in the init table. Some
3767 * opcodes may change the status of iexec->execute to SKIP, which will
3768 * cause the following opcodes to perform no operation until the value
3769 * is changed back to EXECUTE.
3772 int count = 0, i, ret;
3775 /* catch NULL script pointers */
3780 * Loop until INIT_DONE causes us to break out of the loop
3781 * (or until offset > bios length just in case... )
3782 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3784 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3785 id = bios->data[offset];
3787 /* Find matching id in itbl_entry */
3788 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3791 if (!itbl_entry[i].name) {
3793 "0x%04X: Init table command not found: "
3794 "0x%02X\n", offset, id);
3798 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3799 itbl_entry[i].id, itbl_entry[i].name);
3801 /* execute eventual command handler */
3802 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3804 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3805 "table opcode: %s %d\n", offset,
3806 itbl_entry[i].name, ret);
3813 * Add the offset of the current command including all data
3814 * of that command. The offset will then be pointing on the
3820 if (offset >= bios->length)
3822 "Offset 0x%04X greater than known bios image length. "
3823 "Corrupt image?\n", offset);
3824 if (count >= MAX_TABLE_OPS)
3826 "More than %d opcodes to a table is unlikely, "
3827 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3833 parse_init_tables(struct nvbios *bios)
3835 /* Loops and calls parse_init_table() for each present table. */
3839 struct init_exec iexec = {true, false};
3841 if (bios->old_style_init) {
3842 if (bios->init_script_tbls_ptr)
3843 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3844 if (bios->extra_init_script_tbl_ptr)
3845 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3850 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3852 "Parsing VBIOS init table %d at offset 0x%04X\n",
3854 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3856 parse_init_table(bios, table, &iexec);
3861 static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3863 int compare_record_len, i = 0;
3864 uint16_t compareclk, scriptptr = 0;
3866 if (bios->major_version < 5) /* pre BIT */
3867 compare_record_len = 3;
3869 compare_record_len = 4;
3872 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3873 if (pxclk >= compareclk * 10) {
3874 if (bios->major_version < 5) {
3875 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3876 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3878 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3882 } while (compareclk);
3888 run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3889 struct dcb_entry *dcbent, int head, bool dl)
3891 struct drm_nouveau_private *dev_priv = dev->dev_private;
3892 struct nvbios *bios = &dev_priv->vbios;
3893 struct init_exec iexec = {true, false};
3895 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3897 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3898 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3899 /* note: if dcb entries have been merged, index may be misleading */
3900 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3901 parse_init_table(bios, scriptptr, &iexec);
3903 nv04_dfp_bind_head(dev, dcbent, head, dl);
3906 static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3908 struct drm_nouveau_private *dev_priv = dev->dev_private;
3909 struct nvbios *bios = &dev_priv->vbios;
3910 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3911 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3913 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3916 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3918 if (script == LVDS_PANEL_OFF) {
3919 /* off-on delay in ms */
3920 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3923 /* Powerbook specific quirks */
3924 if (script == LVDS_RESET &&
3925 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3926 dev->pci_device == 0x0329))
3927 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3933 static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3936 * The BIT LVDS table's header has the information to setup the
3937 * necessary registers. Following the standard 4 byte header are:
3938 * A bitmask byte and a dual-link transition pxclk value for use in
3939 * selecting the init script when not using straps; 4 script pointers
3940 * for panel power, selected by output and on/off; and 8 table pointers
3941 * for panel init, the needed one determined by output, and bits in the
3942 * conf byte. These tables are similar to the TMDS tables, consisting
3943 * of a list of pxclks and script pointers.
3945 struct drm_nouveau_private *dev_priv = dev->dev_private;
3946 struct nvbios *bios = &dev_priv->vbios;
3947 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3948 uint16_t scriptptr = 0, clktable;
3951 * For now we assume version 3.0 table - g80 support will need some
3958 case LVDS_BACKLIGHT_ON:
3960 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3962 case LVDS_BACKLIGHT_OFF:
3963 case LVDS_PANEL_OFF:
3964 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3967 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3968 if (dcbent->or == 4)
3971 if (dcbent->lvdsconf.use_straps_for_mode) {
3972 if (bios->fp.dual_link)
3974 if (bios->fp.if_is_24bit)
3978 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
3980 if (bios->fp.dual_link) {
3985 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3989 clktable = ROM16(bios->data[clktable]);
3991 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3994 scriptptr = clkcmptable(bios, clktable, pxclk);
3998 NV_ERROR(dev, "LVDS output init script not found\n");
4001 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
4006 int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
4009 * LVDS operations are multiplexed in an effort to present a single API
4010 * which works with two vastly differing underlying structures.
4011 * This acts as the demux
4014 struct drm_nouveau_private *dev_priv = dev->dev_private;
4015 struct nvbios *bios = &dev_priv->vbios;
4016 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
4017 uint32_t sel_clk_binding, sel_clk;
4020 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
4021 (lvds_ver >= 0x30 && script == LVDS_INIT))
4024 if (!bios->fp.lvds_init_run) {
4025 bios->fp.lvds_init_run = true;
4026 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
4029 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
4030 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
4031 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
4032 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
4034 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
4036 /* don't let script change pll->head binding */
4037 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4039 if (lvds_ver < 0x30)
4040 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
4042 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
4044 bios->fp.last_script_invoc = (script << 1 | head);
4046 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4047 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4048 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
4049 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
4054 struct lvdstableheader {
4055 uint8_t lvds_ver, headerlen, recordlen;
4058 static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
4061 * BMP version (0xa) LVDS table has a simple header of version and
4062 * record length. The BIT LVDS table has the typical BIT table header:
4063 * version byte, header length byte, record length byte, and a byte for
4064 * the maximum number of records that can be held in the table.
4067 uint8_t lvds_ver, headerlen, recordlen;
4069 memset(lth, 0, sizeof(struct lvdstableheader));
4071 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
4072 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
4076 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
4079 case 0x0a: /* pre NV40 */
4081 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4083 case 0x30: /* NV4x */
4084 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4085 if (headerlen < 0x1f) {
4086 NV_ERROR(dev, "LVDS table header not understood\n");
4089 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4091 case 0x40: /* G80/G90 */
4092 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4093 if (headerlen < 0x7) {
4094 NV_ERROR(dev, "LVDS table header not understood\n");
4097 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4101 "LVDS table revision %d.%d not currently supported\n",
4102 lvds_ver >> 4, lvds_ver & 0xf);
4106 lth->lvds_ver = lvds_ver;
4107 lth->headerlen = headerlen;
4108 lth->recordlen = recordlen;
4114 get_fp_strap(struct drm_device *dev, struct nvbios *bios)
4116 struct drm_nouveau_private *dev_priv = dev->dev_private;
4119 * The fp strap is normally dictated by the "User Strap" in
4120 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
4121 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
4122 * by the PCI subsystem ID during POST, but not before the previous user
4123 * strap has been committed to CR58 for CR57=0xf on head A, which may be
4124 * read and used instead
4127 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
4128 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
4130 if (dev_priv->card_type >= NV_50)
4131 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
4133 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4136 static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4139 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4140 int ret, ofs, fpstrapping;
4141 struct lvdstableheader lth;
4143 if (bios->fp.fptablepointer == 0x0) {
4144 /* Apple cards don't have the fp table; the laptops use DDC */
4145 /* The table is also missing on some x86 IGPs */
4147 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4149 bios->digital_min_front_porch = 0x4b;
4153 fptable = &bios->data[bios->fp.fptablepointer];
4154 fptable_ver = fptable[0];
4156 switch (fptable_ver) {
4158 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4159 * version field, and miss one of the spread spectrum/PWM bytes.
4160 * This could affect early GF2Go parts (not seen any appropriate ROMs
4161 * though). Here we assume that a version of 0x05 matches this case
4162 * (combining with a BMP version check would be better), as the
4163 * common case for the panel type field is 0x0005, and that is in
4164 * fact what we are reading the first byte of.
4166 case 0x05: /* some NV10, 11, 15, 16 */
4170 case 0x10: /* some NV15/16, and NV11+ */
4174 case 0x20: /* NV40+ */
4175 headerlen = fptable[1];
4176 recordlen = fptable[2];
4177 fpentries = fptable[3];
4179 * fptable[4] is the minimum
4180 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4182 bios->digital_min_front_porch = fptable[4];
4187 "FP table revision %d.%d not currently supported\n",
4188 fptable_ver >> 4, fptable_ver & 0xf);
4192 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4195 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
4199 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4200 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4202 bios->fp.xlatwidth = lth.recordlen;
4204 if (bios->fp.fpxlatetableptr == 0x0) {
4205 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4209 fpstrapping = get_fp_strap(dev, bios);
4211 fpindex = bios->data[bios->fp.fpxlatetableptr +
4212 fpstrapping * bios->fp.xlatwidth];
4214 if (fpindex > fpentries) {
4215 NV_ERROR(dev, "Bad flat panel table index\n");
4219 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4220 if (lth.lvds_ver > 0x10)
4221 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
4224 * If either the strap or xlated fpindex value are 0xf there is no
4225 * panel using a strap-derived bios mode present. this condition
4226 * includes, but is different from, the DDC panel indicator above
4228 if (fpstrapping == 0xf || fpindex == 0xf)
4231 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4232 recordlen * fpindex + ofs;
4234 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4235 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4236 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4237 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4242 bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4244 struct drm_nouveau_private *dev_priv = dev->dev_private;
4245 struct nvbios *bios = &dev_priv->vbios;
4246 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4248 if (!mode) /* just checking whether we can produce a mode */
4249 return bios->fp.mode_ptr;
4251 memset(mode, 0, sizeof(struct drm_display_mode));
4253 * For version 1.0 (version in byte 0):
4254 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4255 * single/dual link, and type (TFT etc.)
4256 * bytes 3-6 are bits per colour in RGBX
4258 mode->clock = ROM16(mode_entry[7]) * 10;
4259 /* bytes 9-10 is HActive */
4260 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4262 * bytes 13-14 is HValid Start
4263 * bytes 15-16 is HValid End
4265 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4266 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4267 mode->htotal = ROM16(mode_entry[21]) + 1;
4268 /* bytes 23-24, 27-30 similarly, but vertical */
4269 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4270 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4271 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4272 mode->vtotal = ROM16(mode_entry[35]) + 1;
4273 mode->flags |= (mode_entry[37] & 0x10) ?
4274 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4275 mode->flags |= (mode_entry[37] & 0x1) ?
4276 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4278 * bytes 38-39 relate to spread spectrum settings
4279 * bytes 40-43 are something to do with PWM
4282 mode->status = MODE_OK;
4283 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4284 drm_mode_set_name(mode);
4285 return bios->fp.mode_ptr;
4288 int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4291 * The LVDS table header is (mostly) described in
4292 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4293 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4294 * straps are not being used for the panel, this specifies the frequency
4295 * at which modes should be set up in the dual link style.
4297 * Following the header, the BMP (ver 0xa) table has several records,
4298 * indexed by a separate xlat table, indexed in turn by the fp strap in
4299 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4300 * numbers for use by INIT_SUB which controlled panel init and power,
4301 * and finally a dword of ms to sleep between power off and on
4304 * In the BIT versions, the table following the header serves as an
4305 * integrated config and xlat table: the records in the table are
4306 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4307 * two bytes - the first as a config byte, the second for indexing the
4308 * fp mode table pointed to by the BIT 'D' table
4310 * DDC is not used until after card init, so selecting the correct table
4311 * entry and setting the dual link flag for EDID equipped panels,
4312 * requiring tests against the native-mode pixel clock, cannot be done
4313 * until later, when this function should be called with non-zero pxclk
4315 struct drm_nouveau_private *dev_priv = dev->dev_private;
4316 struct nvbios *bios = &dev_priv->vbios;
4317 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4318 struct lvdstableheader lth;
4320 int ret, chip_version = bios->chip_version;
4322 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
4326 switch (lth.lvds_ver) {
4327 case 0x0a: /* pre NV40 */
4328 lvdsmanufacturerindex = bios->data[
4329 bios->fp.fpxlatemanufacturertableptr +
4332 /* we're done if this isn't the EDID panel case */
4336 if (chip_version < 0x25) {
4339 * It seems the old style lvds script pointer is reused
4340 * to select 18/24 bit colour depth for EDID panels.
4342 lvdsmanufacturerindex =
4343 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4345 if (pxclk >= bios->fp.duallink_transition_clk)
4346 lvdsmanufacturerindex++;
4347 } else if (chip_version < 0x30) {
4348 /* nv28 behaviour (off-chip encoder)
4350 * nv28 does a complex dance of first using byte 121 of
4351 * the EDID to choose the lvdsmanufacturerindex, then
4352 * later attempting to match the EDID manufacturer and
4353 * product IDs in a table (signature 'pidt' (panel id
4354 * table?)), setting an lvdsmanufacturerindex of 0 and
4355 * an fp strap of the match index (or 0xf if none)
4357 lvdsmanufacturerindex = 0;
4359 /* nv31, nv34 behaviour */
4360 lvdsmanufacturerindex = 0;
4361 if (pxclk >= bios->fp.duallink_transition_clk)
4362 lvdsmanufacturerindex = 2;
4363 if (pxclk >= 140000)
4364 lvdsmanufacturerindex = 3;
4368 * nvidia set the high nibble of (cr57=f, cr58) to
4369 * lvdsmanufacturerindex in this case; we don't
4372 case 0x30: /* NV4x */
4373 case 0x40: /* G80/G90 */
4374 lvdsmanufacturerindex = fpstrapping;
4377 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4381 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4382 switch (lth.lvds_ver) {
4384 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4385 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4386 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4387 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4388 *if_is_24bit = bios->data[lvdsofs] & 16;
4393 * No sign of the "power off for reset" or "reset for panel
4394 * on" bits, but it's safer to assume we should
4396 bios->fp.power_off_for_reset = true;
4397 bios->fp.reset_after_pclk_change = true;
4400 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
4401 * over-written, and if_is_24bit isn't used
4403 bios->fp.dual_link = bios->data[lvdsofs] & 1;
4404 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4405 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4406 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4410 /* Dell Latitude D620 reports a too-high value for the dual-link
4411 * transition freq, causing us to program the panel incorrectly.
4413 * It doesn't appear the VBIOS actually uses its transition freq
4414 * (90000kHz), instead it uses the "Number of LVDS channels" field
4415 * out of the panel ID structure (http://www.spwg.org/).
4417 * For the moment, a quirk will do :)
4419 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
4420 bios->fp.duallink_transition_clk = 80000;
4422 /* set dual_link flag for EDID case */
4423 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4424 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4426 *dl = bios->fp.dual_link;
4431 /* BIT 'U'/'d' table encoder subtables have hashes matching them to
4432 * a particular set of encoders.
4434 * This function returns true if a particular DCB entry matches.
4437 bios_encoder_match(struct dcb_entry *dcb, u32 hash)
4439 if ((hash & 0x000000f0) != (dcb->location << 4))
4441 if ((hash & 0x0000000f) != dcb->type)
4443 if (!(hash & (dcb->or << 16)))
4446 switch (dcb->type) {
4450 if (hash & 0x00c00000) {
4451 if (!(hash & (dcb->sorconf.link << 22)))
4460 nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4461 struct dcb_entry *dcbent, int crtc)
4464 * The display script table is located by the BIT 'U' table.
4466 * It contains an array of pointers to various tables describing
4467 * a particular output type. The first 32-bits of the output
4468 * tables contains similar information to a DCB entry, and is
4469 * used to decide whether that particular table is suitable for
4470 * the output you want to access.
4472 * The "record header length" field here seems to indicate the
4473 * offset of the first configuration entry in the output tables.
4474 * This is 10 on most cards I've seen, but 12 has been witnessed
4475 * on DP cards, and there's another script pointer within the
4478 * offset + 0 ( 8 bits): version
4479 * offset + 1 ( 8 bits): header length
4480 * offset + 2 ( 8 bits): record length
4481 * offset + 3 ( 8 bits): number of records
4482 * offset + 4 ( 8 bits): record header length
4483 * offset + 5 (16 bits): pointer to first output script table
4486 struct drm_nouveau_private *dev_priv = dev->dev_private;
4487 struct nvbios *bios = &dev_priv->vbios;
4488 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4489 uint8_t *otable = NULL;
4493 if (!bios->display.script_table_ptr) {
4494 NV_ERROR(dev, "No pointer to output script table\n");
4499 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4500 * so until they are, we really don't need to care.
4502 if (table[0] < 0x20)
4505 if (table[0] != 0x20 && table[0] != 0x21) {
4506 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4512 * The output script tables describing a particular output type
4515 * offset + 0 (32 bits): output this table matches (hash of DCB)
4516 * offset + 4 ( 8 bits): unknown
4517 * offset + 5 ( 8 bits): number of configurations
4518 * offset + 6 (16 bits): pointer to some script
4519 * offset + 8 (16 bits): pointer to some script
4522 * offset + 10 : configuration 0
4525 * offset + 10 : pointer to some script
4526 * offset + 12 : configuration 0
4528 * Each config entry is as follows:
4530 * offset + 0 (16 bits): unknown, assumed to be a match value
4531 * offset + 2 (16 bits): pointer to script table (clock set?)
4532 * offset + 4 (16 bits): pointer to script table (reset?)
4534 * There doesn't appear to be a count value to say how many
4535 * entries exist in each script table, instead, a 0 value in
4536 * the first 16-bit word seems to indicate both the end of the
4537 * list and the default entry. The second 16-bit word in the
4538 * script tables is a pointer to the script to execute.
4541 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
4542 dcbent->type, dcbent->location, dcbent->or);
4543 for (i = 0; i < table[3]; i++) {
4544 otable = ROMPTR(bios, table[table[1] + (i * table[2])]);
4545 if (otable && bios_encoder_match(dcbent, ROM32(otable[0])))
4550 NV_DEBUG_KMS(dev, "failed to match any output table\n");
4554 if (pclk < -2 || pclk > 0) {
4555 /* Try to find matching script table entry */
4556 for (i = 0; i < otable[5]; i++) {
4557 if (ROM16(otable[table[4] + i*6]) == type)
4561 if (i == otable[5]) {
4562 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4564 type, dcbent->type, dcbent->or);
4570 script = ROM16(otable[6]);
4572 NV_DEBUG_KMS(dev, "output script 0 not found\n");
4576 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
4577 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4580 script = ROM16(otable[8]);
4582 NV_DEBUG_KMS(dev, "output script 1 not found\n");
4586 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
4587 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4591 script = ROM16(otable[10]);
4595 NV_DEBUG_KMS(dev, "output script 2 not found\n");
4599 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
4600 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4603 script = ROM16(otable[table[4] + i*6 + 2]);
4605 script = clkcmptable(bios, script, pclk);
4607 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
4611 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
4612 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4615 script = ROM16(otable[table[4] + i*6 + 4]);
4617 script = clkcmptable(bios, script, -pclk);
4619 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
4623 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
4624 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4631 int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4634 * the pxclk parameter is in kHz
4636 * This runs the TMDS regs setting code found on BIT bios cards
4638 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4639 * ffs(or) == 3, use the second.
4642 struct drm_nouveau_private *dev_priv = dev->dev_private;
4643 struct nvbios *bios = &dev_priv->vbios;
4644 int cv = bios->chip_version;
4645 uint16_t clktable = 0, scriptptr;
4646 uint32_t sel_clk_binding, sel_clk;
4648 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4649 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4650 dcbent->location != DCB_LOC_ON_CHIP)
4653 switch (ffs(dcbent->or)) {
4655 clktable = bios->tmds.output0_script_ptr;
4659 clktable = bios->tmds.output1_script_ptr;
4664 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4668 scriptptr = clkcmptable(bios, clktable, pxclk);
4671 NV_ERROR(dev, "TMDS output init script not found\n");
4675 /* don't let script change pll->head binding */
4676 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4677 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4678 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4679 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4684 struct pll_mapping {
4689 static struct pll_mapping nv04_pll_mapping[] = {
4690 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4691 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4692 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4693 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4697 static struct pll_mapping nv40_pll_mapping[] = {
4698 { PLL_CORE , 0x004000 },
4699 { PLL_MEMORY, 0x004020 },
4700 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4701 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4705 static struct pll_mapping nv50_pll_mapping[] = {
4706 { PLL_CORE , 0x004028 },
4707 { PLL_SHADER, 0x004020 },
4708 { PLL_UNK03 , 0x004000 },
4709 { PLL_MEMORY, 0x004008 },
4710 { PLL_UNK40 , 0x00e810 },
4711 { PLL_UNK41 , 0x00e818 },
4712 { PLL_UNK42 , 0x00e824 },
4713 { PLL_VPLL0 , 0x614100 },
4714 { PLL_VPLL1 , 0x614900 },
4718 static struct pll_mapping nv84_pll_mapping[] = {
4719 { PLL_CORE , 0x004028 },
4720 { PLL_SHADER, 0x004020 },
4721 { PLL_MEMORY, 0x004008 },
4722 { PLL_UNK05 , 0x004030 },
4723 { PLL_UNK41 , 0x00e818 },
4724 { PLL_VPLL0 , 0x614100 },
4725 { PLL_VPLL1 , 0x614900 },
4730 get_pll_register(struct drm_device *dev, enum pll_types type)
4732 struct drm_nouveau_private *dev_priv = dev->dev_private;
4733 struct nvbios *bios = &dev_priv->vbios;
4734 struct pll_mapping *map;
4737 if (dev_priv->card_type < NV_40)
4738 map = nv04_pll_mapping;
4740 if (dev_priv->card_type < NV_50)
4741 map = nv40_pll_mapping;
4743 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4745 if (plim[0] >= 0x30) {
4746 u8 *entry = plim + plim[1];
4747 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4748 if (entry[0] == type)
4749 return ROM32(entry[3]);
4755 if (dev_priv->chipset == 0x50)
4756 map = nv50_pll_mapping;
4758 map = nv84_pll_mapping;
4762 if (map->type == type)
4770 int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4775 * Version 0x10: NV30, NV31
4776 * One byte header (version), one record of 24 bytes
4777 * Version 0x11: NV36 - Not implemented
4778 * Seems to have same record style as 0x10, but 3 records rather than 1
4779 * Version 0x20: Found on Geforce 6 cards
4780 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4781 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4782 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4783 * length in general, some (integrated) have an extra configuration byte
4784 * Version 0x30: Found on Geforce 8, separates the register mapping
4785 * from the limits tables.
4788 struct drm_nouveau_private *dev_priv = dev->dev_private;
4789 struct nvbios *bios = &dev_priv->vbios;
4790 int cv = bios->chip_version, pllindex = 0;
4791 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4792 uint32_t crystal_strap_mask, crystal_straps;
4794 if (!bios->pll_limit_tbl_ptr) {
4795 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4797 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4801 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4803 crystal_strap_mask = 1 << 6;
4804 /* open coded dev->twoHeads test */
4805 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4806 crystal_strap_mask |= 1 << 22;
4807 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4810 switch (pll_lim_ver) {
4812 * We use version 0 to indicate a pre limit table bios (single stage
4813 * pll) and load the hard coded limits instead.
4820 * Strictly v0x11 has 3 entries, but the last two don't seem
4832 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4833 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4834 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4837 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4838 "supported\n", pll_lim_ver);
4842 /* initialize all members to zero */
4843 memset(pll_lim, 0, sizeof(struct pll_lims));
4845 /* if we were passed a type rather than a register, figure
4846 * out the register and store it
4848 if (limit_match > PLL_MAX)
4849 pll_lim->reg = limit_match;
4851 pll_lim->reg = get_pll_register(dev, limit_match);
4856 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4857 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4859 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4860 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4861 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4862 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4863 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4864 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4865 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4867 /* these values taken from nv30/31/36 */
4868 pll_lim->vco1.min_n = 0x1;
4870 pll_lim->vco1.min_n = 0x5;
4871 pll_lim->vco1.max_n = 0xff;
4872 pll_lim->vco1.min_m = 0x1;
4873 pll_lim->vco1.max_m = 0xd;
4874 pll_lim->vco2.min_n = 0x4;
4876 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4877 * table version (apart from nv35)), N2 is compared to
4878 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4881 pll_lim->vco2.max_n = 0x28;
4882 if (cv == 0x30 || cv == 0x35)
4883 /* only 5 bits available for N2 on nv30/35 */
4884 pll_lim->vco2.max_n = 0x1f;
4885 pll_lim->vco2.min_m = 0x1;
4886 pll_lim->vco2.max_m = 0x4;
4887 pll_lim->max_log2p = 0x7;
4888 pll_lim->max_usable_log2p = 0x6;
4889 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4890 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4895 * First entry is default match, if nothing better. warn if
4898 if (ROM32(bios->data[plloffs]))
4899 NV_WARN(dev, "Default PLL limit entry has non-zero "
4900 "register field\n");
4902 for (i = 1; i < entries; i++)
4903 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
4908 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4909 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4910 "limits table", pll_lim->reg);
4914 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4916 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4917 pllindex ? pll_lim->reg : 0);
4920 * Frequencies are stored in tables in MHz, kHz are more
4921 * useful, so we convert.
4924 /* What output frequencies can each VCO generate? */
4925 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4926 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4927 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4928 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4930 /* What input frequencies they accept (past the m-divider)? */
4931 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4932 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4933 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4934 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4936 /* What values are accepted as multiplier and divider? */
4937 pll_lim->vco1.min_n = pll_rec[20];
4938 pll_lim->vco1.max_n = pll_rec[21];
4939 pll_lim->vco1.min_m = pll_rec[22];
4940 pll_lim->vco1.max_m = pll_rec[23];
4941 pll_lim->vco2.min_n = pll_rec[24];
4942 pll_lim->vco2.max_n = pll_rec[25];
4943 pll_lim->vco2.min_m = pll_rec[26];
4944 pll_lim->vco2.max_m = pll_rec[27];
4946 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4947 if (pll_lim->max_log2p > 0x7)
4948 /* pll decoding in nv_hw.c assumes never > 7 */
4949 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4950 pll_lim->max_log2p);
4952 pll_lim->max_usable_log2p = 0x6;
4953 pll_lim->log2p_bias = pll_rec[30];
4955 if (recordlen > 0x22)
4956 pll_lim->refclk = ROM32(pll_rec[31]);
4958 if (recordlen > 0x23 && pll_rec[35])
4960 "Bits set in PLL configuration byte (%x)\n",
4963 /* C51 special not seen elsewhere */
4964 if (cv == 0x51 && !pll_lim->refclk) {
4965 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4967 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4968 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
4969 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4970 pll_lim->refclk = 200000;
4972 pll_lim->refclk = 25000;
4975 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4976 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4977 uint8_t *record = NULL;
4980 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4983 for (i = 0; i < entries; i++, entry += recordlen) {
4984 if (ROM32(entry[3]) == pll_lim->reg) {
4985 record = &bios->data[ROM16(entry[1])];
4991 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4992 "limits table", pll_lim->reg);
4996 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4997 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4998 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4999 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
5000 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
5001 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
5002 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
5003 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
5004 pll_lim->vco1.min_n = record[16];
5005 pll_lim->vco1.max_n = record[17];
5006 pll_lim->vco1.min_m = record[18];
5007 pll_lim->vco1.max_m = record[19];
5008 pll_lim->vco2.min_n = record[20];
5009 pll_lim->vco2.max_n = record[21];
5010 pll_lim->vco2.min_m = record[22];
5011 pll_lim->vco2.max_m = record[23];
5012 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
5013 pll_lim->log2p_bias = record[27];
5014 pll_lim->refclk = ROM32(record[28]);
5015 } else if (pll_lim_ver) { /* ver 0x40 */
5016 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
5017 uint8_t *record = NULL;
5020 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
5023 for (i = 0; i < entries; i++, entry += recordlen) {
5024 if (ROM32(entry[3]) == pll_lim->reg) {
5025 record = &bios->data[ROM16(entry[1])];
5031 NV_ERROR(dev, "Register 0x%08x not found in PLL "
5032 "limits table", pll_lim->reg);
5036 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
5037 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
5038 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
5039 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
5040 pll_lim->vco1.min_m = record[8];
5041 pll_lim->vco1.max_m = record[9];
5042 pll_lim->vco1.min_n = record[10];
5043 pll_lim->vco1.max_n = record[11];
5044 pll_lim->min_p = record[12];
5045 pll_lim->max_p = record[13];
5046 pll_lim->refclk = ROM16(entry[9]) * 1000;
5050 * By now any valid limit table ought to have set a max frequency for
5051 * vco1, so if it's zero it's either a pre limit table bios, or one
5052 * with an empty limit table (seen on nv18)
5054 if (!pll_lim->vco1.maxfreq) {
5055 pll_lim->vco1.minfreq = bios->fminvco;
5056 pll_lim->vco1.maxfreq = bios->fmaxvco;
5057 pll_lim->vco1.min_inputfreq = 0;
5058 pll_lim->vco1.max_inputfreq = INT_MAX;
5059 pll_lim->vco1.min_n = 0x1;
5060 pll_lim->vco1.max_n = 0xff;
5061 pll_lim->vco1.min_m = 0x1;
5062 if (crystal_straps == 0) {
5063 /* nv05 does this, nv11 doesn't, nv10 unknown */
5065 pll_lim->vco1.min_m = 0x7;
5066 pll_lim->vco1.max_m = 0xd;
5069 pll_lim->vco1.min_m = 0x8;
5070 pll_lim->vco1.max_m = 0xe;
5072 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
5073 pll_lim->max_log2p = 4;
5075 pll_lim->max_log2p = 5;
5076 pll_lim->max_usable_log2p = pll_lim->max_log2p;
5079 if (!pll_lim->refclk)
5080 switch (crystal_straps) {
5082 pll_lim->refclk = 13500;
5085 pll_lim->refclk = 14318;
5088 pll_lim->refclk = 27000;
5090 case (1 << 22 | 1 << 6):
5091 pll_lim->refclk = 25000;
5095 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
5096 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
5097 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
5098 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
5099 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
5100 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
5101 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
5102 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
5103 if (pll_lim->vco2.maxfreq) {
5104 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
5105 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
5106 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
5107 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
5108 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
5109 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
5110 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
5111 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
5113 if (!pll_lim->max_p) {
5114 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
5115 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
5117 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
5118 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
5120 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
5125 static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
5128 * offset + 0 (8 bits): Micro version
5129 * offset + 1 (8 bits): Minor version
5130 * offset + 2 (8 bits): Chip version
5131 * offset + 3 (8 bits): Major version
5134 bios->major_version = bios->data[offset + 3];
5135 bios->chip_version = bios->data[offset + 2];
5136 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
5137 bios->data[offset + 3], bios->data[offset + 2],
5138 bios->data[offset + 1], bios->data[offset]);
5141 static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
5144 * Parses the init table segment for pointers used in script execution.
5146 * offset + 0 (16 bits): init script tables pointer
5147 * offset + 2 (16 bits): macro index table pointer
5148 * offset + 4 (16 bits): macro table pointer
5149 * offset + 6 (16 bits): condition table pointer
5150 * offset + 8 (16 bits): io condition table pointer
5151 * offset + 10 (16 bits): io flag condition table pointer
5152 * offset + 12 (16 bits): init function table pointer
5155 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5156 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5157 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5158 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5159 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5160 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5161 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5164 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5167 * Parses the load detect values for g80 cards.
5169 * offset + 0 (16 bits): loadval table pointer
5172 uint16_t load_table_ptr;
5173 uint8_t version, headerlen, entrylen, num_entries;
5175 if (bitentry->length != 3) {
5176 NV_ERROR(dev, "Do not understand BIT A table\n");
5180 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5182 if (load_table_ptr == 0x0) {
5183 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
5187 version = bios->data[load_table_ptr];
5189 if (version != 0x10) {
5190 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5191 version >> 4, version & 0xF);
5195 headerlen = bios->data[load_table_ptr + 1];
5196 entrylen = bios->data[load_table_ptr + 2];
5197 num_entries = bios->data[load_table_ptr + 3];
5199 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5200 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5204 /* First entry is normal dac, 2nd tv-out perhaps? */
5205 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
5210 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5213 * offset + 8 (16 bits): PLL limits table pointer
5215 * There's more in here, but that's unknown.
5218 if (bitentry->length < 10) {
5219 NV_ERROR(dev, "Do not understand BIT C table\n");
5223 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5228 static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5231 * Parses the flat panel table segment that the bit entry points to.
5232 * Starting at bitentry->offset:
5234 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5235 * records beginning with a freq.
5236 * offset + 2 (16 bits): mode table pointer
5239 if (bitentry->length != 4) {
5240 NV_ERROR(dev, "Do not understand BIT display table\n");
5244 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5249 static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5252 * Parses the init table segment that the bit entry points to.
5254 * See parse_script_table_pointers for layout
5257 if (bitentry->length < 14) {
5258 NV_ERROR(dev, "Do not understand init table\n");
5262 parse_script_table_pointers(bios, bitentry->offset);
5264 if (bitentry->length >= 16)
5265 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5266 if (bitentry->length >= 18)
5267 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5272 static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5275 * BIT 'i' (info?) table
5277 * offset + 0 (32 bits): BIOS version dword (as in B table)
5278 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5279 * offset + 13 (16 bits): pointer to table containing DAC load
5280 * detection comparison values
5282 * There's other things in the table, purpose unknown
5285 uint16_t daccmpoffset;
5286 uint8_t dacver, dacheaderlen;
5288 if (bitentry->length < 6) {
5289 NV_ERROR(dev, "BIT i table too short for needed information\n");
5293 parse_bios_version(dev, bios, bitentry->offset);
5296 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5297 * Quadro identity crisis), other bits possibly as for BMP feature byte
5299 bios->feature_byte = bios->data[bitentry->offset + 5];
5300 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5302 if (bitentry->length < 15) {
5303 NV_WARN(dev, "BIT i table not long enough for DAC load "
5304 "detection comparison table\n");
5308 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5310 /* doesn't exist on g80 */
5315 * The first value in the table, following the header, is the
5316 * comparison value, the second entry is a comparison value for
5317 * TV load detection.
5320 dacver = bios->data[daccmpoffset];
5321 dacheaderlen = bios->data[daccmpoffset + 1];
5323 if (dacver != 0x00 && dacver != 0x10) {
5324 NV_WARN(dev, "DAC load detection comparison table version "
5325 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5329 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5330 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
5335 static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5338 * Parses the LVDS table segment that the bit entry points to.
5339 * Starting at bitentry->offset:
5341 * offset + 0 (16 bits): LVDS strap xlate table pointer
5344 if (bitentry->length != 2) {
5345 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5350 * No idea if it's still called the LVDS manufacturer table, but
5351 * the concept's close enough.
5353 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5359 parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5360 struct bit_entry *bitentry)
5363 * offset + 2 (8 bits): number of options in an
5364 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5365 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5366 * restrict option selection
5368 * There's a bunch of bits in this table other than the RAM restrict
5369 * stuff that we don't use - their use currently unknown
5373 * Older bios versions don't have a sufficiently long table for
5376 if (bitentry->length < 0x5)
5379 if (bitentry->version < 2) {
5380 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5381 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
5383 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5384 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
5390 static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5393 * Parses the pointer to the TMDS table
5395 * Starting at bitentry->offset:
5397 * offset + 0 (16 bits): TMDS table pointer
5399 * The TMDS table is typically found just before the DCB table, with a
5400 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5403 * At offset +7 is a pointer to a script, which I don't know how to
5405 * At offset +9 is a pointer to another script, likewise
5406 * Offset +11 has a pointer to a table where the first word is a pxclk
5407 * frequency and the second word a pointer to a script, which should be
5408 * run if the comparison pxclk frequency is less than the pxclk desired.
5409 * This repeats for decreasing comparison frequencies
5410 * Offset +13 has a pointer to a similar table
5411 * The selection of table (and possibly +7/+9 script) is dictated by
5412 * "or" from the DCB.
5415 uint16_t tmdstableptr, script1, script2;
5417 if (bitentry->length != 2) {
5418 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5422 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5423 if (!tmdstableptr) {
5424 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5428 NV_INFO(dev, "TMDS table version %d.%d\n",
5429 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5431 /* nv50+ has v2.0, but we don't parse it atm */
5432 if (bios->data[tmdstableptr] != 0x11)
5436 * These two scripts are odd: they don't seem to get run even when
5437 * they are not stubbed.
5439 script1 = ROM16(bios->data[tmdstableptr + 7]);
5440 script2 = ROM16(bios->data[tmdstableptr + 9]);
5441 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5442 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5444 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5445 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5451 parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5452 struct bit_entry *bitentry)
5455 * Parses the pointer to the G80 output script tables
5457 * Starting at bitentry->offset:
5459 * offset + 0 (16 bits): output script table pointer
5462 uint16_t outputscripttableptr;
5464 if (bitentry->length != 3) {
5465 NV_ERROR(dev, "Do not understand BIT U table\n");
5469 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5470 bios->display.script_table_ptr = outputscripttableptr;
5476 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5479 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5482 bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5484 struct drm_nouveau_private *dev_priv = dev->dev_private;
5485 struct nvbios *bios = &dev_priv->vbios;
5488 entries = bios->data[bios->offset + 10];
5489 entry = &bios->data[bios->offset + 12];
5491 if (entry[0] == id) {
5493 bit->version = entry[1];
5494 bit->length = ROM16(entry[2]);
5495 bit->offset = ROM16(entry[4]);
5496 bit->data = ROMPTR(bios, entry[4]);
5500 entry += bios->data[bios->offset + 9];
5507 parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5508 struct bit_table *table)
5510 struct drm_device *dev = bios->dev;
5511 struct bit_entry bitentry;
5513 if (bit_table(dev, table->id, &bitentry) == 0)
5514 return table->parse_fn(dev, bios, &bitentry);
5516 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5521 parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5526 * The only restriction on parsing order currently is having 'i' first
5527 * for use of bios->*_version or bios->feature_byte while parsing;
5528 * functions shouldn't be actually *doing* anything apart from pulling
5529 * data from the image into the bios struct, thus no interdependencies
5531 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5532 if (ret) /* info? */
5534 if (bios->major_version >= 0x60) /* g80+ */
5535 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5536 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5539 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5540 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5543 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5544 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5545 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5546 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5551 static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5554 * Parses the BMP structure for useful things, but does not act on them
5556 * offset + 5: BMP major version
5557 * offset + 6: BMP minor version
5558 * offset + 9: BMP feature byte
5559 * offset + 10: BCD encoded BIOS version
5561 * offset + 18: init script table pointer (for bios versions < 5.10h)
5562 * offset + 20: extra init script table pointer (for bios
5565 * offset + 24: memory init table pointer (used on early bios versions)
5566 * offset + 26: SDR memory sequencing setup data table
5567 * offset + 28: DDR memory sequencing setup data table
5569 * offset + 54: index of I2C CRTC pair to use for CRT output
5570 * offset + 55: index of I2C CRTC pair to use for TV output
5571 * offset + 56: index of I2C CRTC pair to use for flat panel output
5572 * offset + 58: write CRTC index for I2C pair 0
5573 * offset + 59: read CRTC index for I2C pair 0
5574 * offset + 60: write CRTC index for I2C pair 1
5575 * offset + 61: read CRTC index for I2C pair 1
5577 * offset + 67: maximum internal PLL frequency (single stage PLL)
5578 * offset + 71: minimum internal PLL frequency (single stage PLL)
5580 * offset + 75: script table pointers, as described in
5581 * parse_script_table_pointers
5583 * offset + 89: TMDS single link output A table pointer
5584 * offset + 91: TMDS single link output B table pointer
5585 * offset + 95: LVDS single link output A table pointer
5586 * offset + 105: flat panel timings table pointer
5587 * offset + 107: flat panel strapping translation table pointer
5588 * offset + 117: LVDS manufacturer panel config table pointer
5589 * offset + 119: LVDS manufacturer strapping translation table pointer
5591 * offset + 142: PLL limits table pointer
5593 * offset + 156: minimum pixel clock for LVDS dual link
5596 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5598 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5600 /* load needed defaults in case we can't parse this info */
5601 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5602 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5603 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5604 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
5605 bios->digital_min_front_porch = 0x4b;
5606 bios->fmaxvco = 256000;
5607 bios->fminvco = 128000;
5608 bios->fp.duallink_transition_clk = 90000;
5610 bmp_version_major = bmp[5];
5611 bmp_version_minor = bmp[6];
5613 NV_TRACE(dev, "BMP version %d.%d\n",
5614 bmp_version_major, bmp_version_minor);
5617 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5618 * pointer on early versions
5620 if (bmp_version_major < 5)
5621 *(uint16_t *)&bios->data[0x36] = 0;
5624 * Seems that the minor version was 1 for all major versions prior
5625 * to 5. Version 6 could theoretically exist, but I suspect BIT
5628 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5629 NV_ERROR(dev, "You have an unsupported BMP version. "
5630 "Please send in your bios\n");
5634 if (bmp_version_major == 0)
5635 /* nothing that's currently useful in this version */
5637 else if (bmp_version_major == 1)
5638 bmplength = 44; /* exact for 1.01 */
5639 else if (bmp_version_major == 2)
5640 bmplength = 48; /* exact for 2.01 */
5641 else if (bmp_version_major == 3)
5643 /* guessed - mem init tables added in this version */
5644 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5645 /* don't know if 5.0 exists... */
5647 /* guessed - BMP I2C indices added in version 4*/
5648 else if (bmp_version_minor < 0x6)
5649 bmplength = 67; /* exact for 5.01 */
5650 else if (bmp_version_minor < 0x10)
5651 bmplength = 75; /* exact for 5.06 */
5652 else if (bmp_version_minor == 0x10)
5653 bmplength = 89; /* exact for 5.10h */
5654 else if (bmp_version_minor < 0x14)
5655 bmplength = 118; /* exact for 5.11h */
5656 else if (bmp_version_minor < 0x24)
5658 * Not sure of version where pll limits came in;
5659 * certainly exist by 0x24 though.
5661 /* length not exact: this is long enough to get lvds members */
5663 else if (bmp_version_minor < 0x27)
5665 * Length not exact: this is long enough to get pll limit
5671 * Length not exact: this is long enough to get dual link
5677 if (nv_cksum(bmp, 8)) {
5678 NV_ERROR(dev, "Bad BMP checksum\n");
5683 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5684 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5685 * (not nv10gl), bit 5 that the flat panel tables are present, and
5688 bios->feature_byte = bmp[9];
5690 parse_bios_version(dev, bios, offset + 10);
5692 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5693 bios->old_style_init = true;
5694 legacy_scripts_offset = 18;
5695 if (bmp_version_major < 2)
5696 legacy_scripts_offset -= 4;
5697 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5698 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5700 if (bmp_version_major > 2) { /* appears in BMP 3 */
5701 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5702 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5703 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5706 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5708 legacy_i2c_offset = offset + 54;
5709 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5710 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5711 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
5712 if (bios->data[legacy_i2c_offset + 4])
5713 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5714 if (bios->data[legacy_i2c_offset + 5])
5715 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5716 if (bios->data[legacy_i2c_offset + 6])
5717 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5718 if (bios->data[legacy_i2c_offset + 7])
5719 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
5721 if (bmplength > 74) {
5722 bios->fmaxvco = ROM32(bmp[67]);
5723 bios->fminvco = ROM32(bmp[71]);
5726 parse_script_table_pointers(bios, offset + 75);
5727 if (bmplength > 94) {
5728 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5729 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5731 * Never observed in use with lvds scripts, but is reused for
5732 * 18/24 bit panel interface default for EDID equipped panels
5733 * (if_is_24bit not set directly to avoid any oscillation).
5735 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5737 if (bmplength > 108) {
5738 bios->fp.fptablepointer = ROM16(bmp[105]);
5739 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5740 bios->fp.xlatwidth = 1;
5742 if (bmplength > 120) {
5743 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5744 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5746 if (bmplength > 143)
5747 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5749 if (bmplength > 157)
5750 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5755 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5759 for (i = 0; i <= (n - len); i++) {
5760 for (j = 0; j < len; j++)
5761 if (data[i + j] != str[j])
5770 static struct dcb_gpio_entry *
5771 new_gpio_entry(struct nvbios *bios)
5773 struct drm_device *dev = bios->dev;
5774 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
5776 if (gpio->entries >= DCB_MAX_NUM_GPIO_ENTRIES) {
5777 NV_ERROR(dev, "exceeded maximum number of gpio entries!!\n");
5781 return &gpio->entry[gpio->entries++];
5784 struct dcb_gpio_entry *
5785 nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5787 struct drm_nouveau_private *dev_priv = dev->dev_private;
5788 struct nvbios *bios = &dev_priv->vbios;
5791 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5792 if (bios->dcb.gpio.entry[i].tag != tag)
5795 return &bios->dcb.gpio.entry[i];
5802 parse_dcb_gpio_table(struct nvbios *bios)
5804 struct drm_device *dev = bios->dev;
5805 struct dcb_gpio_entry *e;
5806 u8 headerlen, entries, recordlen;
5807 u8 *dcb, *gpio = NULL, *entry;
5810 dcb = ROMPTR(bios, bios->data[0x36]);
5811 if (dcb[0] >= 0x30) {
5812 gpio = ROMPTR(bios, dcb[10]);
5816 headerlen = gpio[1];
5818 recordlen = gpio[3];
5820 if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) {
5821 gpio = ROMPTR(bios, dcb[-15]);
5827 recordlen = gpio[1];
5829 if (dcb[0] >= 0x22) {
5830 /* No GPIO table present, parse the TVDAC GPIO data. */
5831 uint8_t *tvdac_gpio = &dcb[-5];
5833 if (tvdac_gpio[0] & 1) {
5834 e = new_gpio_entry(bios);
5835 e->tag = DCB_GPIO_TVDAC0;
5836 e->line = tvdac_gpio[1] >> 4;
5837 e->invert = tvdac_gpio[0] & 2;
5842 NV_DEBUG(dev, "no/unknown gpio table on DCB 0x%02x\n", dcb[0]);
5846 entry = gpio + headerlen;
5847 for (i = 0; i < entries; i++, entry += recordlen) {
5848 e = new_gpio_entry(bios);
5852 if (gpio[0] < 0x40) {
5853 e->entry = ROM16(entry[0]);
5854 e->tag = (e->entry & 0x07e0) >> 5;
5855 if (e->tag == 0x3f) {
5856 bios->dcb.gpio.entries--;
5860 e->line = (e->entry & 0x001f);
5861 e->invert = ((e->entry & 0xf800) >> 11) != 4;
5863 e->entry = ROM32(entry[0]);
5864 e->tag = (e->entry & 0x0000ff00) >> 8;
5865 if (e->tag == 0xff) {
5866 bios->dcb.gpio.entries--;
5870 e->line = (e->entry & 0x0000001f) >> 0;
5871 if (gpio[0] == 0x40) {
5872 e->state_default = (e->entry & 0x01000000) >> 24;
5873 e->state[0] = (e->entry & 0x18000000) >> 27;
5874 e->state[1] = (e->entry & 0x60000000) >> 29;
5876 e->state_default = (e->entry & 0x00000080) >> 7;
5877 e->state[0] = (entry[4] >> 4) & 3;
5878 e->state[1] = (entry[4] >> 6) & 3;
5884 /* Apple iMac G4 NV18 */
5885 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) {
5886 e = new_gpio_entry(bios);
5888 e->tag = DCB_GPIO_TVDAC0;
5894 struct dcb_connector_table_entry *
5895 nouveau_bios_connector_entry(struct drm_device *dev, int index)
5897 struct drm_nouveau_private *dev_priv = dev->dev_private;
5898 struct nvbios *bios = &dev_priv->vbios;
5899 struct dcb_connector_table_entry *cte;
5901 if (index >= bios->dcb.connector.entries)
5904 cte = &bios->dcb.connector.entry[index];
5905 if (cte->type == 0xff)
5911 static enum dcb_connector_type
5912 divine_connector_type(struct nvbios *bios, int index)
5914 struct dcb_table *dcb = &bios->dcb;
5915 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5918 for (i = 0; i < dcb->entries; i++) {
5919 if (dcb->entry[i].connector == index)
5920 encoders |= (1 << dcb->entry[i].type);
5923 if (encoders & (1 << OUTPUT_DP)) {
5924 if (encoders & (1 << OUTPUT_TMDS))
5925 type = DCB_CONNECTOR_DP;
5927 type = DCB_CONNECTOR_eDP;
5929 if (encoders & (1 << OUTPUT_TMDS)) {
5930 if (encoders & (1 << OUTPUT_ANALOG))
5931 type = DCB_CONNECTOR_DVI_I;
5933 type = DCB_CONNECTOR_DVI_D;
5935 if (encoders & (1 << OUTPUT_ANALOG)) {
5936 type = DCB_CONNECTOR_VGA;
5938 if (encoders & (1 << OUTPUT_LVDS)) {
5939 type = DCB_CONNECTOR_LVDS;
5941 if (encoders & (1 << OUTPUT_TV)) {
5942 type = DCB_CONNECTOR_TV_0;
5949 apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5951 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5952 struct drm_device *dev = bios->dev;
5954 /* Gigabyte NX85T */
5955 if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) {
5956 if (cte->type == DCB_CONNECTOR_HDMI_1)
5957 cte->type = DCB_CONNECTOR_DVI_I;
5960 /* Gigabyte GV-NX86T512H */
5961 if (nv_match_device(dev, 0x0402, 0x1458, 0x3455)) {
5962 if (cte->type == DCB_CONNECTOR_HDMI_1)
5963 cte->type = DCB_CONNECTOR_DVI_I;
5967 static const u8 hpd_gpio[16] = {
5968 0xff, 0x07, 0x08, 0xff, 0xff, 0x51, 0x52, 0xff,
5969 0xff, 0xff, 0xff, 0xff, 0xff, 0x5e, 0x5f, 0x60,
5973 parse_dcb_connector_table(struct nvbios *bios)
5975 struct drm_device *dev = bios->dev;
5976 struct dcb_connector_table *ct = &bios->dcb.connector;
5977 struct dcb_connector_table_entry *cte;
5978 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
5982 if (!bios->dcb.connector_table_ptr) {
5983 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
5987 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5988 conntab[0], conntab[1], conntab[2], conntab[3]);
5989 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5990 (conntab[3] != 2 && conntab[3] != 4)) {
5991 NV_ERROR(dev, " Unknown! Please report.\n");
5995 ct->entries = conntab[2];
5997 entry = conntab + conntab[1];
5998 cte = &ct->entry[0];
5999 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
6001 if (conntab[3] == 2)
6002 cte->entry = ROM16(entry[0]);
6004 cte->entry = ROM32(entry[0]);
6006 cte->type = (cte->entry & 0x000000ff) >> 0;
6007 cte->index2 = (cte->entry & 0x00000f00) >> 8;
6009 cte->gpio_tag = ffs((cte->entry & 0x07033000) >> 12);
6010 cte->gpio_tag = hpd_gpio[cte->gpio_tag];
6012 if (cte->type == 0xff)
6015 apply_dcb_connector_quirks(bios, i);
6017 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
6018 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
6020 /* check for known types, fallback to guessing the type
6021 * from attached encoders if we hit an unknown.
6023 switch (cte->type) {
6024 case DCB_CONNECTOR_VGA:
6025 case DCB_CONNECTOR_TV_0:
6026 case DCB_CONNECTOR_TV_1:
6027 case DCB_CONNECTOR_TV_3:
6028 case DCB_CONNECTOR_DVI_I:
6029 case DCB_CONNECTOR_DVI_D:
6030 case DCB_CONNECTOR_LVDS:
6031 case DCB_CONNECTOR_LVDS_SPWG:
6032 case DCB_CONNECTOR_DP:
6033 case DCB_CONNECTOR_eDP:
6034 case DCB_CONNECTOR_HDMI_0:
6035 case DCB_CONNECTOR_HDMI_1:
6038 cte->type = divine_connector_type(bios, cte->index);
6039 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
6043 if (nouveau_override_conntype) {
6044 int type = divine_connector_type(bios, cte->index);
6045 if (type != cte->type)
6046 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
6052 static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6054 struct dcb_entry *entry = &dcb->entry[dcb->entries];
6056 memset(entry, 0, sizeof(struct dcb_entry));
6057 entry->index = dcb->entries++;
6062 static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
6065 struct dcb_entry *entry = new_dcb_entry(dcb);
6068 entry->i2c_index = i2c;
6069 entry->heads = heads;
6070 if (type != OUTPUT_ANALOG)
6071 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
6076 parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6077 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6079 entry->type = conn & 0xf;
6080 entry->i2c_index = (conn >> 4) & 0xf;
6081 entry->heads = (conn >> 8) & 0xf;
6082 if (dcb->version >= 0x40)
6083 entry->connector = (conn >> 12) & 0xf;
6084 entry->bus = (conn >> 16) & 0xf;
6085 entry->location = (conn >> 20) & 0x3;
6086 entry->or = (conn >> 24) & 0xf;
6088 switch (entry->type) {
6091 * Although the rest of a CRT conf dword is usually
6092 * zeros, mac biosen have stuff there so we must mask
6094 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6095 (conf & 0xffff) * 10 :
6096 (conf & 0xff) * 10000;
6102 entry->lvdsconf.use_straps_for_mode = true;
6103 if (dcb->version < 0x22) {
6106 * The laptop in bug 14567 lies and claims to not use
6107 * straps when it does, so assume all DCB 2.0 laptops
6108 * use straps, until a broken EDID using one is produced
6110 entry->lvdsconf.use_straps_for_mode = true;
6112 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
6113 * mean the same thing (probably wrong, but might work)
6115 if (conf & 0x4 || conf & 0x8)
6116 entry->lvdsconf.use_power_scripts = true;
6120 entry->lvdsconf.use_acpi_for_edid = true;
6122 entry->lvdsconf.use_power_scripts = true;
6123 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6127 * Until we even try to use these on G8x, it's
6128 * useless reporting unknown bits. They all are.
6130 if (dcb->version >= 0x40)
6133 NV_ERROR(dev, "Unknown LVDS configuration bits, "
6140 if (dcb->version >= 0x30)
6141 entry->tvconf.has_component_output = conf & (0x8 << 4);
6143 entry->tvconf.has_component_output = false;
6148 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
6149 switch ((conf & 0x00e00000) >> 21) {
6151 entry->dpconf.link_bw = 162000;
6154 entry->dpconf.link_bw = 270000;
6157 switch ((conf & 0x0f000000) >> 24) {
6159 entry->dpconf.link_nr = 4;
6162 entry->dpconf.link_nr = 2;
6165 entry->dpconf.link_nr = 1;
6170 if (dcb->version >= 0x40)
6171 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
6172 else if (dcb->version >= 0x30)
6173 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
6174 else if (dcb->version >= 0x22)
6175 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
6179 /* weird g80 mobile type that "nv" treats as a terminator */
6186 if (dcb->version < 0x40) {
6187 /* Normal entries consist of a single bit, but dual link has
6188 * the next most significant bit set too
6190 entry->duallink_possible =
6191 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
6193 entry->duallink_possible = (entry->sorconf.link == 3);
6196 /* unsure what DCB version introduces this, 3.0? */
6197 if (conf & 0x100000)
6198 entry->i2c_upper_default = true;
6204 parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6205 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6207 switch (conn & 0x0000000f) {
6209 entry->type = OUTPUT_ANALOG;
6212 entry->type = OUTPUT_TV;
6217 entry->type = OUTPUT_LVDS;
6219 entry->type = OUTPUT_TMDS;
6222 entry->type = OUTPUT_LVDS;
6225 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
6229 entry->i2c_index = (conn & 0x0003c000) >> 14;
6230 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
6231 entry->or = entry->heads; /* same as heads, hopefully safe enough */
6232 entry->location = (conn & 0x01e00000) >> 21;
6233 entry->bus = (conn & 0x0e000000) >> 25;
6234 entry->duallink_possible = false;
6236 switch (entry->type) {
6238 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
6241 entry->tvconf.has_component_output = false;
6244 if ((conn & 0x00003f00) >> 8 != 0x10)
6245 entry->lvdsconf.use_straps_for_mode = true;
6246 entry->lvdsconf.use_power_scripts = true;
6255 static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6256 uint32_t conn, uint32_t conf)
6258 struct dcb_entry *entry = new_dcb_entry(dcb);
6261 if (dcb->version >= 0x20)
6262 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6264 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6268 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6269 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6275 void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6278 * DCB v2.0 lists each output combination separately.
6279 * Here we merge compatible entries to have fewer outputs, with
6283 int i, newentries = 0;
6285 for (i = 0; i < dcb->entries; i++) {
6286 struct dcb_entry *ient = &dcb->entry[i];
6289 for (j = i + 1; j < dcb->entries; j++) {
6290 struct dcb_entry *jent = &dcb->entry[j];
6292 if (jent->type == 100) /* already merged entry */
6295 /* merge heads field when all other fields the same */
6296 if (jent->i2c_index == ient->i2c_index &&
6297 jent->type == ient->type &&
6298 jent->location == ient->location &&
6299 jent->or == ient->or) {
6300 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
6302 ient->heads |= jent->heads;
6303 jent->type = 100; /* dummy value */
6308 /* Compact entries merged into others out of dcb */
6309 for (i = 0; i < dcb->entries; i++) {
6310 if (dcb->entry[i].type == 100)
6313 if (newentries != i) {
6314 dcb->entry[newentries] = dcb->entry[i];
6315 dcb->entry[newentries].index = newentries;
6320 dcb->entries = newentries;
6324 apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6326 struct drm_nouveau_private *dev_priv = dev->dev_private;
6327 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6329 /* Dell Precision M6300
6330 * DCB entry 2: 02025312 00000010
6331 * DCB entry 3: 02026312 00000020
6333 * Identical, except apparently a different connector on a
6334 * different SOR link. Not a clue how we're supposed to know
6335 * which one is in use if it even shares an i2c line...
6337 * Ignore the connector on the second SOR link to prevent
6338 * nasty problems until this is sorted (assuming it's not a
6341 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
6342 if (*conn == 0x02026312 && *conf == 0x00000020)
6348 * DCB reports an LVDS output that should be TMDS:
6349 * DCB entry 1: f2005014 ffffffff
6351 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
6352 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
6353 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
6360 * So many things wrong here, replace the entire encoder table..
6362 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6364 *conn = 0x02001300; /* VGA, connector 1 */
6368 *conn = 0x01010312; /* DVI, connector 0 */
6372 *conn = 0x01010310; /* VGA, connector 0 */
6376 *conn = 0x02022362; /* HDMI, connector 2 */
6379 *conn = 0x0000000e; /* EOL */
6384 /* Some other twisted XFX board (rhbz#694914)
6386 * The DVI/VGA encoder combo that's supposed to represent the
6387 * DVI-I connector actually point at two different ones, and
6388 * the HDMI connector ends up paired with the VGA instead.
6390 * Connector table is missing anything for VGA at all, pointing it
6391 * an invalid conntab entry 2 so we figure it out ourself.
6393 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
6395 *conn = 0x02002300; /* VGA, connector 2 */
6399 *conn = 0x01010312; /* DVI, connector 0 */
6403 *conn = 0x04020310; /* VGA, connector 0 */
6407 *conn = 0x02021322; /* HDMI, connector 1 */
6410 *conn = 0x0000000e; /* EOL */
6419 fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6421 struct dcb_table *dcb = &bios->dcb;
6422 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6425 /* Apple iMac G4 NV17 */
6426 if (of_machine_is_compatible("PowerMac4,5")) {
6427 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6428 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6433 /* Make up some sane defaults */
6434 fabricate_dcb_output(dcb, OUTPUT_ANALOG, LEGACY_I2C_CRT, 1, 1);
6436 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6437 fabricate_dcb_output(dcb, OUTPUT_TV, LEGACY_I2C_TV,
6440 else if (bios->tmds.output0_script_ptr ||
6441 bios->tmds.output1_script_ptr)
6442 fabricate_dcb_output(dcb, OUTPUT_TMDS, LEGACY_I2C_PANEL,
6447 parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6449 struct drm_nouveau_private *dev_priv = dev->dev_private;
6450 struct dcb_table *dcb = &bios->dcb;
6451 uint16_t dcbptr = 0, i2ctabptr = 0;
6453 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
6454 bool configblock = true;
6455 int recordlength = 8, confofs = 4;
6458 /* get the offset from 0x36 */
6459 if (dev_priv->card_type > NV_04) {
6460 dcbptr = ROM16(bios->data[0x36]);
6461 if (dcbptr == 0x0000)
6462 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
6465 /* this situation likely means a really old card, pre DCB */
6466 if (dcbptr == 0x0) {
6467 fabricate_dcb_encoder_table(dev, bios);
6471 dcbtable = &bios->data[dcbptr];
6473 /* get DCB version */
6474 dcb->version = dcbtable[0];
6475 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
6476 dcb->version >> 4, dcb->version & 0xf);
6478 if (dcb->version >= 0x20) { /* NV17+ */
6481 if (dcb->version >= 0x30) { /* NV40+ */
6482 headerlen = dcbtable[1];
6483 entries = dcbtable[2];
6484 recordlength = dcbtable[3];
6485 i2ctabptr = ROM16(dcbtable[4]);
6486 sig = ROM32(dcbtable[6]);
6487 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
6488 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6490 i2ctabptr = ROM16(dcbtable[2]);
6491 sig = ROM32(dcbtable[4]);
6495 if (sig != 0x4edcbdcb) {
6496 NV_ERROR(dev, "Bad Display Configuration Block "
6497 "signature (%08X)\n", sig);
6500 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6501 char sig[8] = { 0 };
6503 strncpy(sig, (char *)&dcbtable[-7], 7);
6504 i2ctabptr = ROM16(dcbtable[2]);
6508 if (strcmp(sig, "DEV_REC")) {
6509 NV_ERROR(dev, "Bad Display Configuration Block "
6510 "signature (%s)\n", sig);
6515 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
6516 * has the same single (crt) entry, even when tv-out present, so
6517 * the conclusion is this version cannot really be used.
6518 * v1.2 tables (some NV6/10, and NV15+) normally have the same
6519 * 5 entries, which are not specific to the card and so no use.
6520 * v1.2 does have an I2C table that read_dcb_i2c_table can
6521 * handle, but cards exist (nv11 in #14821) with a bad i2c table
6522 * pointer, so use the indices parsed in parse_bmp_structure.
6523 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
6525 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
6526 "adding all possible outputs\n");
6527 fabricate_dcb_encoder_table(dev, bios);
6532 NV_WARN(dev, "No pointer to DCB I2C port table\n");
6534 dcb->i2c_table = &bios->data[i2ctabptr];
6535 if (dcb->version >= 0x30)
6536 dcb->i2c_default_indices = dcb->i2c_table[4];
6539 * Parse the "management" I2C bus, used for hardware
6540 * monitoring and some external TMDS transmitters.
6542 if (dcb->version >= 0x22) {
6543 int idx = (dcb->version >= 0x40 ?
6544 dcb->i2c_default_indices & 0xf :
6547 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6548 idx, &dcb->i2c[idx]);
6552 if (entries > DCB_MAX_NUM_ENTRIES)
6553 entries = DCB_MAX_NUM_ENTRIES;
6555 for (i = 0; i < entries; i++) {
6556 uint32_t connection, config = 0;
6558 connection = ROM32(dcbtable[headerlen + recordlength * i]);
6560 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
6562 /* seen on an NV11 with DCB v1.5 */
6563 if (connection == 0x00000000)
6566 /* seen on an NV17 with DCB v2.0 */
6567 if (connection == 0xffffffff)
6570 if ((connection & 0x0000000f) == 0x0000000f)
6573 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config))
6576 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
6577 dcb->entries, connection, config);
6579 if (!parse_dcb_entry(dev, dcb, connection, config))
6584 * apart for v2.1+ not being known for requiring merging, this
6585 * guarantees dcbent->index is the index of the entry in the rom image
6587 if (dcb->version < 0x21)
6588 merge_like_dcb_entries(dev, dcb);
6593 parse_dcb_gpio_table(bios);
6594 parse_dcb_connector_table(bios);
6599 fixup_legacy_connector(struct nvbios *bios)
6601 struct dcb_table *dcb = &bios->dcb;
6602 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6605 * DCB 3.0 also has the table in most cases, but there are some cards
6606 * where the table is filled with stub entries, and the DCB entriy
6607 * indices are all 0. We don't need the connector indices on pre-G80
6608 * chips (yet?) so limit the use to DCB 4.0 and above.
6610 if (dcb->version >= 0x40)
6613 dcb->connector.entries = 0;
6616 * No known connector info before v3.0, so make it up. the rule here
6617 * is: anything on the same i2c bus is considered to be on the same
6618 * connector. any output without an associated i2c bus is assigned
6619 * its own unique connector index.
6621 for (i = 0; i < dcb->entries; i++) {
6623 * Ignore the I2C index for on-chip TV-out, as there
6624 * are cards with bogus values (nv31m in bug 23212),
6625 * and it's otherwise useless.
6627 if (dcb->entry[i].type == OUTPUT_TV &&
6628 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6629 dcb->entry[i].i2c_index = 0xf;
6630 i2c = dcb->entry[i].i2c_index;
6632 if (i2c_conn[i2c]) {
6633 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6637 dcb->entry[i].connector = dcb->connector.entries++;
6639 i2c_conn[i2c] = dcb->connector.entries;
6642 /* Fake the connector table as well as just connector indices */
6643 for (i = 0; i < dcb->connector.entries; i++) {
6644 dcb->connector.entry[i].index = i;
6645 dcb->connector.entry[i].type = divine_connector_type(bios, i);
6646 dcb->connector.entry[i].gpio_tag = 0xff;
6651 fixup_legacy_i2c(struct nvbios *bios)
6653 struct dcb_table *dcb = &bios->dcb;
6656 for (i = 0; i < dcb->entries; i++) {
6657 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
6658 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
6659 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
6660 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
6661 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
6662 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
6666 static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6669 * The header following the "HWSQ" signature has the number of entries,
6670 * and the entry size
6672 * An entry consists of a dword to write to the sequencer control reg
6673 * (0x00001304), followed by the ucode bytes, written sequentially,
6674 * starting at reg 0x00001400
6677 uint8_t bytes_to_write;
6678 uint16_t hwsq_entry_offset;
6681 if (bios->data[hwsq_offset] <= entry) {
6682 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6683 "requested entry\n");
6687 bytes_to_write = bios->data[hwsq_offset + 1];
6689 if (bytes_to_write != 36) {
6690 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6694 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6696 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6698 /* set sequencer control */
6699 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6700 bytes_to_write -= 4;
6703 for (i = 0; i < bytes_to_write; i += 4)
6704 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6706 /* twiddle NV_PBUS_DEBUG_4 */
6707 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6712 static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6713 struct nvbios *bios)
6716 * BMP based cards, from NV17, need a microcode loading to correctly
6717 * control the GPIO etc for LVDS panels
6719 * BIT based cards seem to do this directly in the init scripts
6721 * The microcode entries are found by the "HWSQ" signature.
6724 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6725 const int sz = sizeof(hwsq_signature);
6728 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6732 /* always use entry 0? */
6733 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6736 uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6738 struct drm_nouveau_private *dev_priv = dev->dev_private;
6739 struct nvbios *bios = &dev_priv->vbios;
6740 const uint8_t edid_sig[] = {
6741 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6742 uint16_t offset = 0;
6744 int searchlen = NV_PROM_SIZE;
6747 return bios->fp.edid;
6750 newoffset = findstr(&bios->data[offset], searchlen,
6754 offset += newoffset;
6755 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6758 searchlen -= offset;
6762 NV_TRACE(dev, "Found EDID in BIOS\n");
6764 return bios->fp.edid = &bios->data[offset];
6768 nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6769 struct dcb_entry *dcbent, int crtc)
6771 struct drm_nouveau_private *dev_priv = dev->dev_private;
6772 struct nvbios *bios = &dev_priv->vbios;
6773 struct init_exec iexec = { true, false };
6775 spin_lock_bh(&bios->lock);
6776 bios->display.output = dcbent;
6777 bios->display.crtc = crtc;
6778 parse_init_table(bios, table, &iexec);
6779 bios->display.output = NULL;
6780 spin_unlock_bh(&bios->lock);
6784 nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
6786 struct drm_nouveau_private *dev_priv = dev->dev_private;
6787 struct nvbios *bios = &dev_priv->vbios;
6788 struct init_exec iexec = { true, false };
6790 parse_init_table(bios, table, &iexec);
6793 static bool NVInitVBIOS(struct drm_device *dev)
6795 struct drm_nouveau_private *dev_priv = dev->dev_private;
6796 struct nvbios *bios = &dev_priv->vbios;
6798 memset(bios, 0, sizeof(struct nvbios));
6799 spin_lock_init(&bios->lock);
6802 if (!NVShadowVBIOS(dev, bios->data))
6805 bios->length = NV_PROM_SIZE;
6809 static int nouveau_parse_vbios_struct(struct drm_device *dev)
6811 struct drm_nouveau_private *dev_priv = dev->dev_private;
6812 struct nvbios *bios = &dev_priv->vbios;
6813 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6814 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6817 offset = findstr(bios->data, bios->length,
6818 bit_signature, sizeof(bit_signature));
6820 NV_TRACE(dev, "BIT BIOS found\n");
6821 bios->type = NVBIOS_BIT;
6822 bios->offset = offset;
6823 return parse_bit_structure(bios, offset + 6);
6826 offset = findstr(bios->data, bios->length,
6827 bmp_signature, sizeof(bmp_signature));
6829 NV_TRACE(dev, "BMP BIOS found\n");
6830 bios->type = NVBIOS_BMP;
6831 bios->offset = offset;
6832 return parse_bmp_structure(dev, bios, offset);
6835 NV_ERROR(dev, "No known BIOS signature found\n");
6840 nouveau_run_vbios_init(struct drm_device *dev)
6842 struct drm_nouveau_private *dev_priv = dev->dev_private;
6843 struct nvbios *bios = &dev_priv->vbios;
6846 /* Reset the BIOS head to 0. */
6847 bios->state.crtchead = 0;
6849 if (bios->major_version < 5) /* BMP only */
6850 load_nv17_hw_sequencer_ucode(dev, bios);
6852 if (bios->execute) {
6853 bios->fp.last_script_invoc = 0;
6854 bios->fp.lvds_init_run = false;
6857 parse_init_tables(bios);
6860 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6861 * parser will run this right after the init tables, the binary
6862 * driver appears to run it at some point later.
6864 if (bios->some_script_ptr) {
6865 struct init_exec iexec = {true, false};
6867 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6868 bios->some_script_ptr);
6869 parse_init_table(bios, bios->some_script_ptr, &iexec);
6872 if (dev_priv->card_type >= NV_50) {
6873 for (i = 0; i < bios->dcb.entries; i++) {
6874 nouveau_bios_run_display_table(dev, 0, 0,
6875 &bios->dcb.entry[i], -1);
6883 nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6885 struct drm_nouveau_private *dev_priv = dev->dev_private;
6886 struct nvbios *bios = &dev_priv->vbios;
6887 struct dcb_i2c_entry *entry;
6890 entry = &bios->dcb.i2c[0];
6891 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6892 nouveau_i2c_fini(dev, entry);
6896 nouveau_bios_posted(struct drm_device *dev)
6898 struct drm_nouveau_private *dev_priv = dev->dev_private;
6901 if (dev_priv->card_type >= NV_50) {
6902 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6903 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6908 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6909 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6910 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6911 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6912 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
6914 return (htotal != 0);
6918 nouveau_bios_init(struct drm_device *dev)
6920 struct drm_nouveau_private *dev_priv = dev->dev_private;
6921 struct nvbios *bios = &dev_priv->vbios;
6924 if (!NVInitVBIOS(dev))
6927 ret = nouveau_parse_vbios_struct(dev);
6931 ret = parse_dcb_table(dev, bios);
6935 fixup_legacy_i2c(bios);
6936 fixup_legacy_connector(bios);
6938 if (!bios->major_version) /* we don't run version 0 bios */
6941 /* init script execution disabled */
6942 bios->execute = false;
6944 /* ... unless card isn't POSTed already */
6945 if (!nouveau_bios_posted(dev)) {
6946 NV_INFO(dev, "Adaptor not initialised, "
6947 "running VBIOS init tables.\n");
6948 bios->execute = true;
6950 if (nouveau_force_post)
6951 bios->execute = true;
6953 ret = nouveau_run_vbios_init(dev);
6957 /* feature_byte on BMP is poor, but init always sets CR4B */
6958 if (bios->major_version < 5)
6959 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6961 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6962 if (bios->is_mobile || bios->major_version >= 5)
6963 ret = parse_fp_mode_table(dev, bios);
6965 /* allow subsequent scripts to execute */
6966 bios->execute = true;
6972 nouveau_bios_takedown(struct drm_device *dev)
6974 nouveau_bios_i2c_devices_takedown(dev);