drivers/gpu/drm/msm/adreno/adreno_device.c

   1 /*
   2  * Copyright (C) 2013-2014 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "adreno_gpu.h"
  21
  22 #define ANY_ID 0xff
  23
  24 bool hang_debug = false;
  25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  26 module_param_named(hang_debug, hang_debug, bool, 0600);
  27
  28 static const struct adreno_info gpulist[] = {
  29         {
  30                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  31                 .revn  = 305,
  32                 .name  = "A305",
  33                 .pm4fw = "/*(DEBLOBBED)*/",
  34                 .pfpfw = "/*(DEBLOBBED)*/",
  35                 .gmem  = SZ_256K,
  36                 .init  = a3xx_gpu_init,
  37         }, {
  38                 .rev   = ADRENO_REV(3, 0, 6, 0),
  39                 .revn  = 307,        /* because a305c is revn==306 */
  40                 .name  = "A306",
  41                 .pm4fw = "/*(DEBLOBBED)*/",
  42                 .pfpfw = "/*(DEBLOBBED)*/",
  43                 .gmem  = SZ_128K,
  44                 .init  = a3xx_gpu_init,
  45         }, {
  46                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  47                 .revn  = 320,
  48                 .name  = "A320",
  49                 .pm4fw = "/*(DEBLOBBED)*/",
  50                 .pfpfw = "/*(DEBLOBBED)*/",
  51                 .gmem  = SZ_512K,
  52                 .init  = a3xx_gpu_init,
  53         }, {
  54                 .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
  55                 .revn  = 330,
  56                 .name  = "A330",
  57                 .pm4fw = "/*(DEBLOBBED)*/",
  58                 .pfpfw = "/*(DEBLOBBED)*/",
  59                 .gmem  = SZ_1M,
  60                 .init  = a3xx_gpu_init,
  61         }, {
  62                 .rev   = ADRENO_REV(4, 2, 0, ANY_ID),
  63                 .revn  = 420,
  64                 .name  = "A420",
  65                 .pm4fw = "/*(DEBLOBBED)*/",
  66                 .pfpfw = "/*(DEBLOBBED)*/",
  67                 .gmem  = (SZ_1M + SZ_512K),
  68                 .init  = a4xx_gpu_init,
  69         }, {
  70                 .rev   = ADRENO_REV(4, 3, 0, ANY_ID),
  71                 .revn  = 430,
  72                 .name  = "A430",
  73                 .pm4fw = "/*(DEBLOBBED)*/",
  74                 .pfpfw = "/*(DEBLOBBED)*/",
  75                 .gmem  = (SZ_1M + SZ_512K),
  76                 .init  = a4xx_gpu_init,
  77         }, {
  78                 .rev = ADRENO_REV(5, 3, 0, ANY_ID),
  79                 .revn = 530,
  80                 .name = "A530",
  81                 .pm4fw = "/*(DEBLOBBED)*/",
  82                 .pfpfw = "/*(DEBLOBBED)*/",
  83                 .gmem = SZ_1M,
  84                 .init = a5xx_gpu_init,
  85                 .gpmufw = "/*(DEBLOBBED)*/",
  86         },
  87 };
  88
  89 /*(DEBLOBBED)*/
  90
  91 static inline bool _rev_match(uint8_t entry, uint8_t id)
  92 {
  93         return (entry == ANY_ID) || (entry == id);
  94 }
  95
  96 const struct adreno_info *adreno_info(struct adreno_rev rev)
  97 {
  98         int i;
  99
 100         /* identify gpu: */
 101         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
 102                 const struct adreno_info *info = &gpulist[i];
 103                 if (_rev_match(info->rev.core, rev.core) &&
 104                                 _rev_match(info->rev.major, rev.major) &&
 105                                 _rev_match(info->rev.minor, rev.minor) &&
 106                                 _rev_match(info->rev.patchid, rev.patchid))
 107                         return info;
 108         }
 109
 110         return NULL;
 111 }
 112
 113 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
 114 {
 115         struct msm_drm_private *priv = dev->dev_private;
 116         struct platform_device *pdev = priv->gpu_pdev;
 117         struct adreno_platform_config *config;
 118         struct adreno_rev rev;
 119         const struct adreno_info *info;
 120         struct msm_gpu *gpu = NULL;
 121
 122         if (!pdev) {
 123                 dev_err(dev->dev, "no adreno device\n");
 124                 return NULL;
 125         }
 126
 127         config = pdev->dev.platform_data;
 128         rev = config->rev;
 129         info = adreno_info(config->rev);
 130
 131         if (!info) {
 132                 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 133                                 rev.core, rev.major, rev.minor, rev.patchid);
 134                 return NULL;
 135         }
 136
 137         DBG("Found GPU: %u.%u.%u.%u",  rev.core, rev.major,
 138                         rev.minor, rev.patchid);
 139
 140         gpu = info->init(dev);
 141         if (IS_ERR(gpu)) {
 142                 dev_warn(dev->dev, "failed to load adreno gpu\n");
 143                 gpu = NULL;
 144                 /* not fatal */
 145         }
 146
 147         if (gpu) {
 148                 int ret;
 149                 mutex_lock(&dev->struct_mutex);
 150                 gpu->funcs->pm_resume(gpu);
 151                 mutex_unlock(&dev->struct_mutex);
 152
 153                 disable_irq(gpu->irq);
 154
 155                 ret = gpu->funcs->hw_init(gpu);
 156                 if (ret) {
 157                         dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
 158                         gpu->funcs->destroy(gpu);
 159                         gpu = NULL;
 160                 } else {
 161                         enable_irq(gpu->irq);
 162                         /* give inactive pm a chance to kick in: */
 163                         msm_gpu_retire(gpu);
 164                 }
 165         }
 166
 167         return gpu;
 168 }
 169
 170 static void set_gpu_pdev(struct drm_device *dev,
 171                 struct platform_device *pdev)
 172 {
 173         struct msm_drm_private *priv = dev->dev_private;
 174         priv->gpu_pdev = pdev;
 175 }
 176
 177 static const struct {
 178         const char *str;
 179         uint32_t flag;
 180 } quirks[] = {
 181         { "qcom,gpu-quirk-two-pass-use-wfi", ADRENO_QUIRK_TWO_PASS_USE_WFI },
 182         { "qcom,gpu-quirk-fault-detect-mask", ADRENO_QUIRK_FAULT_DETECT_MASK },
 183 };
 184
 185 static int adreno_bind(struct device *dev, struct device *master, void *data)
 186 {
 187         static struct adreno_platform_config config = {};
 188         struct device_node *child, *node = dev->of_node;
 189         u32 val;
 190         int ret, i;
 191
 192         ret = of_property_read_u32(node, "qcom,chipid", &val);
 193         if (ret) {
 194                 dev_err(dev, "could not find chipid: %d\n", ret);
 195                 return ret;
 196         }
 197
 198         config.rev = ADRENO_REV((val >> 24) & 0xff,
 199                         (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
 200
 201         /* find clock rates: */
 202         config.fast_rate = 0;
 203         config.slow_rate = ~0;
 204         for_each_child_of_node(node, child) {
 205                 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
 206                         struct device_node *pwrlvl;
 207                         for_each_child_of_node(child, pwrlvl) {
 208                                 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
 209                                 if (ret) {
 210                                         dev_err(dev, "could not find gpu-freq: %d\n", ret);
 211                                         return ret;
 212                                 }
 213                                 config.fast_rate = max(config.fast_rate, val);
 214                                 config.slow_rate = min(config.slow_rate, val);
 215                         }
 216                 }
 217         }
 218
 219         if (!config.fast_rate) {
 220                 dev_err(dev, "could not find clk rates\n");
 221                 return -ENXIO;
 222         }
 223
 224         for (i = 0; i < ARRAY_SIZE(quirks); i++)
 225                 if (of_property_read_bool(node, quirks[i].str))
 226                         config.quirks |= quirks[i].flag;
 227
 228         dev->platform_data = &config;
 229         set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
 230         return 0;
 231 }
 232
 233 static void adreno_unbind(struct device *dev, struct device *master,
 234                 void *data)
 235 {
 236         set_gpu_pdev(dev_get_drvdata(master), NULL);
 237 }
 238
 239 static const struct component_ops a3xx_ops = {
 240                 .bind   = adreno_bind,
 241                 .unbind = adreno_unbind,
 242 };
 243
 244 static int adreno_probe(struct platform_device *pdev)
 245 {
 246         return component_add(&pdev->dev, &a3xx_ops);
 247 }
 248
 249 static int adreno_remove(struct platform_device *pdev)
 250 {
 251         component_del(&pdev->dev, &a3xx_ops);
 252         return 0;
 253 }
 254
 255 static const struct of_device_id dt_match[] = {
 256         { .compatible = "qcom,adreno-3xx" },
 257         /* for backwards compat w/ downstream kgsl DT files: */
 258         { .compatible = "qcom,kgsl-3d0" },
 259         {}
 260 };
 261
 262 static struct platform_driver adreno_driver = {
 263         .probe = adreno_probe,
 264         .remove = adreno_remove,
 265         .driver = {
 266                 .name = "adreno",
 267                 .of_match_table = dt_match,
 268         },
 269 };
 270
 271 void __init adreno_register(void)
 272 {
 273         platform_driver_register(&adreno_driver);
 274 }
 275
 276 void __exit adreno_unregister(void)
 277 {
 278         platform_driver_unregister(&adreno_driver);
 279 }