4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
21 Copyright (C) 2013-2016 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
49 RB5_R4G4B4A4_UNORM = 8,
50 RB5_R5G5B5A1_UNORM = 10,
51 RB5_R5G6B5_UNORM = 14,
53 RB5_R8G8B8A8_UNORM = 48,
54 RB5_R8G8B8_UNORM = 49,
55 RB5_R8G8B8A8_UINT = 51,
56 RB5_R10G10B10A2_UINT = 58,
57 RB5_R16G16_FLOAT = 69,
59 RB5_R16G16B16A16_FLOAT = 98,
60 RB5_R32G32_FLOAT = 103,
61 RB5_R32G32B32A32_FLOAT = 130,
84 VFMT5_8_8_8_UNORM = 33,
85 VFMT5_8_8_8_SNORM = 34,
86 VFMT5_8_8_8_UINT = 35,
87 VFMT5_8_8_8_SINT = 36,
88 VFMT5_8_8_8_8_UNORM = 48,
89 VFMT5_8_8_8_8_SNORM = 50,
90 VFMT5_8_8_8_8_UINT = 51,
91 VFMT5_8_8_8_8_SINT = 52,
92 VFMT5_16_16_UNORM = 67,
93 VFMT5_16_16_SNORM = 68,
94 VFMT5_16_16_FLOAT = 69,
95 VFMT5_16_16_UINT = 70,
96 VFMT5_16_16_SINT = 71,
103 VFMT5_16_16_16_UNORM = 88,
104 VFMT5_16_16_16_SNORM = 89,
105 VFMT5_16_16_16_FLOAT = 90,
106 VFMT5_16_16_16_UINT = 91,
107 VFMT5_16_16_16_SINT = 92,
108 VFMT5_16_16_16_16_UNORM = 96,
109 VFMT5_16_16_16_16_SNORM = 97,
110 VFMT5_16_16_16_16_FLOAT = 98,
111 VFMT5_16_16_16_16_UINT = 99,
112 VFMT5_16_16_16_16_SINT = 100,
113 VFMT5_32_32_UNORM = 101,
114 VFMT5_32_32_SNORM = 102,
115 VFMT5_32_32_FLOAT = 103,
116 VFMT5_32_32_UINT = 104,
117 VFMT5_32_32_SINT = 105,
118 VFMT5_32_32_FIXED = 106,
119 VFMT5_32_32_32_UNORM = 112,
120 VFMT5_32_32_32_SNORM = 113,
121 VFMT5_32_32_32_UINT = 114,
122 VFMT5_32_32_32_SINT = 115,
123 VFMT5_32_32_32_FLOAT = 116,
124 VFMT5_32_32_32_FIXED = 117,
125 VFMT5_32_32_32_32_UNORM = 128,
126 VFMT5_32_32_32_32_SNORM = 129,
127 VFMT5_32_32_32_32_FLOAT = 130,
128 VFMT5_32_32_32_32_UINT = 131,
129 VFMT5_32_32_32_32_SINT = 132,
130 VFMT5_32_32_32_32_FIXED = 133,
136 TFMT5_4_4_4_4_UNORM = 8,
137 TFMT5_5_5_5_1_UNORM = 10,
138 TFMT5_5_6_5_UNORM = 14,
139 TFMT5_8_8_UNORM = 15,
140 TFMT5_8_8_SNORM = 16,
141 TFMT5_L8_A8_UNORM = 19,
143 TFMT5_8_8_8_8_UNORM = 48,
144 TFMT5_8_8_8_UNORM = 49,
145 TFMT5_8_8_8_SNORM = 50,
146 TFMT5_9_9_9_E5_FLOAT = 53,
147 TFMT5_10_10_10_2_UNORM = 54,
148 TFMT5_11_11_10_FLOAT = 66,
149 TFMT5_16_16_FLOAT = 69,
151 TFMT5_16_16_16_16_FLOAT = 98,
152 TFMT5_32_32_FLOAT = 103,
153 TFMT5_32_32_32_32_FLOAT = 130,
154 TFMT5_X8Z24_UNORM = 160,
157 enum a5xx_tex_fetchsize {
165 enum a5xx_depth_format {
185 enum a5xx_tex_filter {
186 A5XX_TEX_NEAREST = 0,
191 enum a5xx_tex_clamp {
193 A5XX_TEX_CLAMP_TO_EDGE = 1,
194 A5XX_TEX_MIRROR_REPEAT = 2,
195 A5XX_TEX_CLAMP_TO_BORDER = 3,
196 A5XX_TEX_MIRROR_CLAMP = 4,
199 enum a5xx_tex_aniso {
200 A5XX_TEX_ANISO_1 = 0,
201 A5XX_TEX_ANISO_2 = 1,
202 A5XX_TEX_ANISO_4 = 2,
203 A5XX_TEX_ANISO_8 = 3,
204 A5XX_TEX_ANISO_16 = 4,
223 #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
224 #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
225 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
226 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
227 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
228 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
229 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
230 #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
231 #define A5XX_INT0_CP_SW 0x00000100
232 #define A5XX_INT0_CP_HW_ERROR 0x00000200
233 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
234 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
235 #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
236 #define A5XX_INT0_CP_IB2 0x00002000
237 #define A5XX_INT0_CP_IB1 0x00004000
238 #define A5XX_INT0_CP_RB 0x00008000
239 #define A5XX_INT0_CP_UNUSED_1 0x00010000
240 #define A5XX_INT0_CP_RB_DONE_TS 0x00020000
241 #define A5XX_INT0_CP_WT_DONE_TS 0x00040000
242 #define A5XX_INT0_UNKNOWN_1 0x00080000
243 #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
244 #define A5XX_INT0_UNUSED_2 0x00200000
245 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
246 #define A5XX_INT0_MISC_HANG_DETECT 0x00800000
247 #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
248 #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
249 #define A5XX_INT0_DEBBUS_INTR_0 0x04000000
250 #define A5XX_INT0_DEBBUS_INTR_1 0x08000000
251 #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
252 #define A5XX_INT0_GPMU_FIRMWARE 0x20000000
253 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
254 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
255 #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
256 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
257 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
258 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
259 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
260 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
261 #define REG_A5XX_CP_RB_BASE 0x00000800
263 #define REG_A5XX_CP_RB_BASE_HI 0x00000801
265 #define REG_A5XX_CP_RB_CNTL 0x00000802
267 #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
269 #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
271 #define REG_A5XX_CP_RB_RPTR 0x00000806
273 #define REG_A5XX_CP_RB_WPTR 0x00000807
275 #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
277 #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
279 #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
281 #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
283 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
285 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
287 #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
289 #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
291 #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
293 #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
295 #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
297 #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
299 #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
301 #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
303 #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
305 #define REG_A5XX_CP_MERCIU_SIZE 0x00000826
307 #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
309 #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
311 #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
313 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
315 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
317 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
319 #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
321 #define REG_A5XX_CP_CNTL 0x00000831
323 #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
325 #define REG_A5XX_CP_CHICKEN_DBG 0x00000833
327 #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
329 #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
331 #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
333 #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
335 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
337 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
339 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
341 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
343 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
345 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
347 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
349 #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
351 #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
353 #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
355 #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
357 #define REG_A5XX_CP_HW_FAULT 0x00000b1a
359 #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
361 #define REG_A5XX_CP_IB1_BASE 0x00000b1f
363 #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
365 #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
367 #define REG_A5XX_CP_IB2_BASE 0x00000b22
369 #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
371 #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
373 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
375 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
377 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
379 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
380 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
381 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
382 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
384 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
386 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
387 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
388 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
390 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
392 #define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
393 #define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
395 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
397 #define REG_A5XX_CP_AHB_FAULT 0x00000b1b
399 #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
401 #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
403 #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
405 #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
407 #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
409 #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
411 #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
413 #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
415 #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
417 #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
419 #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
421 #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
423 #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
425 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
427 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
429 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
431 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
433 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
435 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
437 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
439 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
441 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
443 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
445 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
447 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
449 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
451 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
453 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
455 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
457 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
459 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
461 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
463 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
465 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
467 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
469 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
471 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
473 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
475 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
477 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
479 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
481 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
483 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
485 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
487 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
489 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
491 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
493 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
495 #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
497 #define REG_A5XX_RBBM_INT_0_MASK 0x00000038
498 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
499 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
500 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
501 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
502 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
503 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
504 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
505 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
506 #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
507 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
508 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
509 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
510 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
511 #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
512 #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
513 #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
514 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
515 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
516 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
517 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
518 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
519 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
520 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
521 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
522 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
523 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
524 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
525 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
526 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
528 #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
530 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
532 #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
534 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
536 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
538 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
540 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
542 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
544 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
546 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
548 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
550 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
552 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
554 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
556 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
558 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
560 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
562 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
564 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
566 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
568 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
570 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
572 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
574 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
576 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
578 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
580 #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
582 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
584 #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
586 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
588 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
590 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
592 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
594 #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
596 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
598 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
600 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
602 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
604 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
606 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
608 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
610 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
612 #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
614 #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
616 #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
618 #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
620 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
622 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
624 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
626 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
628 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
630 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
632 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
634 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
636 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
638 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
640 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
642 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
644 #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
646 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
648 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
650 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
652 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
654 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
656 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
658 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
660 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
662 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
664 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
666 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
668 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
670 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
672 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
674 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
676 #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
678 #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
680 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
682 #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
684 #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
686 #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
688 #define REG_A5XX_RBBM_AHB_CMD 0x00000096
690 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
692 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
694 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
696 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
698 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
700 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
702 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
704 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
706 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
708 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
710 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
712 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
714 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
716 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
718 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
720 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
722 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
724 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
726 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
728 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
730 #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
732 #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
734 #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
736 #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
738 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
740 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
742 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
744 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
746 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
748 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
750 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
752 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
754 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
756 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
758 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
760 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
762 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
764 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
766 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
768 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
770 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
772 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
774 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
776 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
778 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
780 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
782 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
784 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
786 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
788 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
790 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
792 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
794 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
796 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
798 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
800 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
802 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
804 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
806 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
808 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
810 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
812 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
814 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
816 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
818 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
820 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
822 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
824 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
826 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
828 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
830 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
832 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
834 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
836 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
838 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
840 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
842 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
844 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
846 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
848 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
850 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
852 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
854 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
856 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
858 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
860 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
862 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
864 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
866 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
868 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
870 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
872 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
874 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
876 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
878 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
880 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
882 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
884 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
886 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
888 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
890 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
892 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
894 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
896 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
898 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
900 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
902 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
904 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
906 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
908 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
910 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
912 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
914 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
916 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
918 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
920 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
922 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
924 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
926 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
928 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
930 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
932 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
934 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
936 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
938 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
940 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
942 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
944 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
946 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
948 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
950 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
952 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
954 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
956 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
958 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
960 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
962 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
964 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
966 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
968 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
970 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
972 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
974 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
976 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
978 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
980 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
982 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
984 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
986 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
988 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
990 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
992 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
994 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
996 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
998 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
1000 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
1002 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
1004 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
1006 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
1008 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
1010 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
1012 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
1014 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
1016 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
1018 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
1020 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
1022 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
1024 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
1026 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
1028 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
1030 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
1032 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
1034 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
1036 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
1038 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
1040 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
1042 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
1044 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
1046 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
1048 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
1050 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
1052 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
1054 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
1056 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
1058 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
1060 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
1062 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
1064 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
1066 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
1068 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
1070 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
1072 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
1074 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
1076 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
1078 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
1080 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
1082 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
1084 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
1086 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
1088 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
1090 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
1092 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
1094 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
1096 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
1098 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
1100 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
1102 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
1104 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
1106 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
1108 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
1110 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
1112 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
1114 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
1116 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
1118 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
1120 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
1122 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
1124 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
1126 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
1128 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
1130 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
1132 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
1134 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
1136 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
1138 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
1140 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
1142 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
1144 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
1146 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
1148 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
1150 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
1152 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1154 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1156 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1158 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1160 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
1162 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
1164 #define REG_A5XX_RBBM_STATUS 0x000004f5
1165 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
1166 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
1167 #define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1168 #define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
1169 #define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
1170 #define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
1171 #define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
1172 #define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
1173 #define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
1174 #define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
1175 #define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
1176 #define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1177 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1178 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
1179 #define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
1180 #define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
1181 #define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
1182 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
1183 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
1184 #define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
1185 #define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
1186 #define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
1187 #define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
1188 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
1189 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
1190 #define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
1191 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
1192 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
1193 #define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
1194 #define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1195 #define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1196 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
1198 #define REG_A5XX_RBBM_STATUS3 0x00000530
1200 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
1202 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
1204 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
1206 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
1208 #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
1210 #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
1212 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
1214 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
1216 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
1218 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
1220 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
1222 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
1224 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1226 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1228 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1230 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1232 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
1234 #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
1236 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
1238 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
1240 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
1242 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
1244 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
1246 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
1248 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
1250 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
1252 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
1254 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
1256 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
1258 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
1260 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
1262 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
1264 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
1266 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
1268 #define REG_A5XX_RBBM_ISDB_CNT 0x00000533
1270 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
1272 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1274 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1276 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1278 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1280 #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1282 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
1284 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
1286 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
1288 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
1290 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1292 #define REG_A5XX_VSC_PIPE_DATA_LENGTH_0 0x00000c00
1294 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
1296 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
1298 #define REG_A5XX_VSC_BIN_SIZE 0x00000cdd
1299 #define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE 0x80000000
1300 #define A5XX_VSC_BIN_SIZE_X__MASK 0x00007fff
1301 #define A5XX_VSC_BIN_SIZE_X__SHIFT 0
1302 static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val)
1304 return ((val) << A5XX_VSC_BIN_SIZE_X__SHIFT) & A5XX_VSC_BIN_SIZE_X__MASK;
1306 #define A5XX_VSC_BIN_SIZE_Y__MASK 0x7fff0000
1307 #define A5XX_VSC_BIN_SIZE_Y__SHIFT 16
1308 static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
1310 return ((val) << A5XX_VSC_BIN_SIZE_Y__SHIFT) & A5XX_VSC_BIN_SIZE_Y__MASK;
1313 #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
1315 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
1317 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
1319 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
1321 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
1323 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
1325 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
1327 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
1329 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
1331 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
1333 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
1335 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
1337 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
1339 #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
1341 #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
1343 #define REG_A5XX_RB_MODE_CNTL 0x00000cc6
1345 #define REG_A5XX_RB_CCU_CNTL 0x00000cc7
1347 #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
1349 #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
1351 #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
1353 #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
1355 #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
1357 #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
1359 #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
1361 #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
1363 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
1365 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
1367 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
1369 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
1371 #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
1373 #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
1375 #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
1377 #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
1379 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
1381 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
1383 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
1385 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
1387 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
1389 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
1391 #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
1392 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
1394 #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
1396 #define REG_A5XX_PC_MODE_CNTL 0x00000d02
1398 #define REG_A5XX_UNKNOWN_0D08 0x00000d08
1400 #define REG_A5XX_UNKNOWN_0D09 0x00000d09
1402 #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
1404 #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
1406 #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
1408 #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
1410 #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
1412 #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
1414 #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
1416 #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
1418 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
1420 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
1422 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
1424 #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
1426 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
1428 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
1430 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
1432 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
1434 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
1436 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
1438 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
1440 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
1442 #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
1444 #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
1446 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
1448 #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
1450 #define REG_A5XX_VFD_MODE_CNTL 0x00000e42
1452 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
1454 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
1456 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
1458 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
1460 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
1462 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
1464 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
1466 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
1468 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
1470 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
1472 #define REG_A5XX_VPC_MODE_CNTL 0x00000e62
1474 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
1476 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
1478 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
1480 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
1482 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
1484 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
1486 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
1488 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
1490 #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
1492 #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
1494 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
1496 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
1498 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
1500 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
1502 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
1504 #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
1506 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
1508 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
1510 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
1512 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
1514 #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
1516 #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
1518 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
1520 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
1522 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
1524 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
1526 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
1528 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
1530 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
1532 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
1534 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
1536 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
1538 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
1540 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
1542 #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
1544 #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
1546 #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
1548 #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
1550 #define REG_A5XX_SP_MODE_CNTL 0x00000ec2
1552 #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
1554 #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
1556 #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
1558 #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
1560 #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
1562 #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
1564 #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
1566 #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
1568 #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
1570 #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
1572 #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
1574 #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
1576 #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
1578 #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
1580 #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
1582 #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
1584 #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
1586 #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
1588 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
1590 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
1592 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
1594 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
1596 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
1598 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
1600 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
1602 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
1604 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
1606 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
1608 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
1610 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
1612 #define REG_A5XX_VBIF_VERSION 0x00003000
1614 #define REG_A5XX_VBIF_CLKON 0x00003001
1616 #define REG_A5XX_VBIF_ABIT_SORT 0x00003028
1618 #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
1620 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
1622 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1624 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
1626 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
1628 #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
1630 #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
1632 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
1634 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
1636 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
1638 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
1640 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
1642 #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
1644 #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
1646 #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
1648 #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
1650 #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
1652 #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
1654 #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
1656 #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
1658 #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
1660 #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
1662 #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
1664 #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
1666 #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
1668 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
1670 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
1672 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
1674 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
1676 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
1678 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
1680 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
1682 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
1684 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
1686 #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
1688 #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
1690 #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
1692 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
1694 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
1696 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
1697 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
1699 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
1700 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
1702 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
1704 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
1706 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
1708 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
1710 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
1712 #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
1714 #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
1716 #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
1718 #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
1720 #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
1722 #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
1724 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
1726 #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
1728 #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
1730 #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
1732 #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
1734 #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
1736 #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
1738 #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
1740 #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
1742 #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
1744 #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
1746 #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
1748 #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
1750 #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
1752 #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
1754 #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
1756 #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
1758 #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
1760 #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
1762 #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
1764 #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
1766 #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
1768 #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
1770 #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
1772 #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
1774 #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
1776 #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
1778 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
1780 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
1782 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
1784 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
1786 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
1788 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
1790 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
1792 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
1794 #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
1796 #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
1798 #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
1800 #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
1802 #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
1804 #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
1806 #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
1808 #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
1810 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
1812 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
1814 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
1816 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
1818 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
1820 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
1822 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
1824 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
1826 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
1828 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
1830 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
1832 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
1834 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
1836 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
1838 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
1840 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
1842 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
1844 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
1846 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
1848 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
1850 #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
1852 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
1854 #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
1856 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
1858 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
1860 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
1862 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
1864 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
1866 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
1868 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
1870 #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
1872 #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
1874 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
1876 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
1878 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
1880 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
1882 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
1884 #define REG_A5XX_GDPM_CONFIG1 0x0000b80c
1886 #define REG_A5XX_GDPM_CONFIG2 0x0000b80d
1888 #define REG_A5XX_GDPM_INT_EN 0x0000b80f
1890 #define REG_A5XX_GDPM_INT_MASK 0x0000b811
1892 #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
1894 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
1896 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
1898 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
1900 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
1902 #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
1904 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
1906 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000
1908 #define REG_A5XX_UNKNOWN_E001 0x0000e001
1910 #define REG_A5XX_UNKNOWN_E004 0x0000e004
1912 #define REG_A5XX_GRAS_CNTL 0x0000e005
1913 #define A5XX_GRAS_CNTL_VARYING 0x00000001
1915 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
1916 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
1917 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
1918 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
1920 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
1922 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
1923 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
1924 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
1926 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
1929 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
1930 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
1931 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
1932 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
1934 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
1937 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
1938 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
1939 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
1940 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
1942 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
1945 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
1946 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
1947 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
1948 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
1950 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
1953 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
1954 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
1955 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
1956 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
1958 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
1961 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
1962 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
1963 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
1964 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
1966 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
1969 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
1970 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
1971 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
1972 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
1974 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
1977 #define REG_A5XX_GRAS_SU_CNTL 0x0000e090
1978 #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
1979 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
1980 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
1981 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
1983 return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
1985 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
1986 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
1988 #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
1989 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
1990 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
1991 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
1993 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
1995 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
1996 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
1997 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
1999 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2002 #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
2003 #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2004 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
2005 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
2007 return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
2010 #define REG_A5XX_UNKNOWN_E093 0x0000e093
2012 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
2013 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_ALPHA_TEST_ENABLE 0x00000001
2015 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
2016 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2017 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2018 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2020 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2023 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
2024 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2025 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2026 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2028 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2031 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
2032 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2033 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2034 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2036 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2039 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
2040 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2041 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2042 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2044 return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2047 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
2049 #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
2050 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
2052 #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
2054 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
2055 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2056 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2057 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2059 return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
2062 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
2063 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2064 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2065 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2067 return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
2069 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2071 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
2073 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
2074 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2075 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2076 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2077 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2079 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2081 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2082 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2083 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2085 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2088 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
2089 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2090 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
2091 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
2092 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2094 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2096 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
2097 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
2098 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2100 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2103 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
2104 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2105 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
2106 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
2107 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2109 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2111 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
2112 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
2113 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2115 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2118 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
2119 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2120 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
2121 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
2122 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2124 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2126 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
2127 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
2128 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2130 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2133 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
2134 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2135 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2136 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2137 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2139 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2141 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2142 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2143 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2145 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2148 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
2149 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2150 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2151 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2152 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2154 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2156 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2157 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2158 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2160 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2163 #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
2165 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
2167 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
2169 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
2171 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
2173 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
2175 #define REG_A5XX_RB_CNTL 0x0000e140
2176 #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
2177 #define A5XX_RB_CNTL_WIDTH__SHIFT 0
2178 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
2180 return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
2182 #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
2183 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9
2184 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
2186 return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
2188 #define A5XX_RB_CNTL_BYPASS 0x00020000
2190 #define REG_A5XX_RB_RENDER_CNTL 0x0000e141
2191 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
2192 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
2193 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
2194 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
2195 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
2196 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
2198 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
2200 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
2201 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
2202 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
2204 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
2207 #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
2208 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2209 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2210 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2212 return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
2215 #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
2216 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2217 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2218 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2220 return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
2222 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2224 #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
2225 #define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
2226 #define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
2227 #define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
2228 #define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
2229 #define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
2231 #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
2232 #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
2234 #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
2235 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
2236 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
2237 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
2239 return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
2241 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
2243 #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
2244 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
2245 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
2246 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
2248 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
2250 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
2251 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
2252 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
2254 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
2256 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
2257 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
2258 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
2260 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
2262 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
2263 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
2264 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
2266 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
2268 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
2269 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
2270 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
2272 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
2274 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
2275 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
2276 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
2278 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
2280 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
2281 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
2282 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
2284 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
2286 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
2287 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
2288 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
2290 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
2293 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
2295 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
2296 #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
2297 #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
2298 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
2299 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
2300 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
2302 return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
2305 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
2306 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
2307 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
2308 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
2310 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
2312 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
2313 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
2314 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
2316 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
2318 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
2319 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
2320 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
2322 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
2324 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
2325 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
2326 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
2328 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
2330 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
2331 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
2332 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
2334 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
2336 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
2337 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
2338 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
2340 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
2343 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
2344 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
2345 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
2346 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
2348 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
2350 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
2351 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
2352 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
2354 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
2356 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
2357 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
2358 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
2360 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
2362 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
2364 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
2365 #define A5XX_RB_MRT_PITCH__MASK 0xffffffff
2366 #define A5XX_RB_MRT_PITCH__SHIFT 0
2367 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
2369 return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
2372 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
2373 #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
2374 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
2375 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
2377 return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
2380 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
2382 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
2384 #define REG_A5XX_RB_BLEND_RED 0x0000e1a0
2385 #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
2386 #define A5XX_RB_BLEND_RED_UINT__SHIFT 0
2387 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
2389 return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
2391 #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
2392 #define A5XX_RB_BLEND_RED_SINT__SHIFT 8
2393 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
2395 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
2397 #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
2398 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
2399 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
2401 return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
2404 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
2405 #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
2406 #define A5XX_RB_BLEND_RED_F32__SHIFT 0
2407 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
2409 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
2412 #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
2413 #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
2414 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
2415 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
2417 return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
2419 #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
2420 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
2421 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
2423 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
2425 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
2426 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
2427 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
2429 return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
2432 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
2433 #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
2434 #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
2435 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
2437 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
2440 #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
2441 #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
2442 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
2443 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
2445 return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
2447 #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
2448 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
2449 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
2451 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
2453 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
2454 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
2455 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
2457 return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
2460 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
2461 #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
2462 #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
2463 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
2465 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
2468 #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
2469 #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
2470 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
2471 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
2473 return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
2475 #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
2476 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
2477 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
2479 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
2481 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
2482 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
2483 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
2485 return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
2488 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
2489 #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
2490 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
2491 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
2493 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
2496 #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
2497 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
2498 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
2499 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
2501 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
2503 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
2504 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
2505 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
2506 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
2508 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
2511 #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
2512 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
2513 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
2514 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
2516 return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
2518 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
2519 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
2520 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
2521 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
2523 return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
2526 #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
2527 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2529 #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
2530 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
2531 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
2532 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
2533 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
2534 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
2536 return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
2538 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
2540 #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
2541 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2542 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2543 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2545 return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2548 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
2550 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
2552 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
2553 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
2554 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
2555 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
2557 return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
2560 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
2561 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
2562 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
2563 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
2565 return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
2568 #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
2569 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
2570 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
2571 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
2572 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
2573 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
2574 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
2576 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
2578 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
2579 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
2580 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
2582 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
2584 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
2585 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
2586 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
2588 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
2590 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
2591 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
2592 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
2594 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
2596 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
2597 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
2598 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
2600 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
2602 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
2603 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
2604 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
2606 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
2608 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
2609 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
2610 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
2612 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
2614 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
2615 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
2616 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
2618 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
2621 #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
2622 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
2624 #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
2626 #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
2628 #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
2629 #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
2630 #define A5XX_RB_STENCIL_PITCH__SHIFT 0
2631 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
2633 return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
2636 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
2637 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
2638 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
2639 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
2641 return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
2644 #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
2645 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
2646 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
2647 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
2649 return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
2651 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
2652 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
2653 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
2655 return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
2657 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
2658 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
2659 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
2661 return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
2664 #define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7
2666 #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
2667 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2668 #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
2669 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
2670 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
2672 return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
2674 #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
2675 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
2676 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
2678 return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
2681 #define REG_A5XX_RB_BLIT_CNTL 0x0000e210
2682 #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000003f
2683 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
2684 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
2686 return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
2689 #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
2690 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
2691 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
2692 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
2693 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
2695 return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
2697 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
2698 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
2699 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
2701 return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
2704 #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
2705 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
2706 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
2707 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
2708 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
2710 return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
2712 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
2713 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
2714 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
2716 return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
2719 #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
2721 #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
2723 #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
2725 #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
2726 #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
2727 #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
2728 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
2730 return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
2733 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
2734 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
2735 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
2736 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
2738 return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
2741 #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
2743 #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
2745 #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
2747 #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
2749 #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
2750 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
2751 #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
2752 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
2753 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
2755 return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
2758 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
2760 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
2762 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
2764 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
2766 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
2768 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
2770 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
2771 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
2772 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
2773 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
2775 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
2778 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
2779 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
2780 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
2781 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
2783 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
2786 #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
2788 #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
2790 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
2791 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
2792 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
2793 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
2795 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
2798 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
2799 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
2800 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
2801 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
2803 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
2806 #define REG_A5XX_VPC_CNTL_0 0x0000e280
2807 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
2808 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
2809 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
2811 return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
2813 #define A5XX_VPC_CNTL_0_VARYING 0x00000800
2815 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
2817 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
2819 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
2821 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
2823 #define REG_A5XX_UNKNOWN_E292 0x0000e292
2825 #define REG_A5XX_UNKNOWN_E293 0x0000e293
2827 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
2829 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
2831 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
2833 #define REG_A5XX_UNKNOWN_E29A 0x0000e29a
2835 #define REG_A5XX_VPC_PACK 0x0000e29d
2836 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
2837 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
2838 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
2840 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
2843 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
2845 #define REG_A5XX_UNKNOWN_E2A1 0x0000e2a1
2847 #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
2849 #define REG_A5XX_VPC_SO_BUFFER_BASE_LO_0 0x0000e2a7
2851 #define REG_A5XX_VPC_SO_BUFFER_BASE_HI_0 0x0000e2a8
2853 #define REG_A5XX_VPC_SO_BUFFER_SIZE_0 0x0000e2a9
2855 #define REG_A5XX_UNKNOWN_E2AB 0x0000e2ab
2857 #define REG_A5XX_VPC_SO_FLUSH_BASE_LO_0 0x0000e2ac
2859 #define REG_A5XX_VPC_SO_FLUSH_BASE_HI_0 0x0000e2ad
2861 #define REG_A5XX_UNKNOWN_E2AE 0x0000e2ae
2863 #define REG_A5XX_UNKNOWN_E2B2 0x0000e2b2
2865 #define REG_A5XX_UNKNOWN_E2B9 0x0000e2b9
2867 #define REG_A5XX_UNKNOWN_E2C0 0x0000e2c0
2869 #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
2870 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
2871 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
2872 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
2874 return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
2877 #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
2878 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
2880 #define REG_A5XX_PC_RASTER_CNTL 0x0000e388
2882 #define REG_A5XX_UNKNOWN_E389 0x0000e389
2884 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
2886 #define REG_A5XX_UNKNOWN_E38D 0x0000e38d
2888 #define REG_A5XX_PC_GS_PARAM 0x0000e38e
2890 #define REG_A5XX_PC_HS_PARAM 0x0000e38f
2892 #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
2894 #define REG_A5XX_VFD_CONTROL_0 0x0000e400
2895 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
2896 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
2897 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
2899 return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
2902 #define REG_A5XX_VFD_CONTROL_1 0x0000e401
2903 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
2904 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
2905 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
2907 return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
2909 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
2910 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
2911 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
2913 return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
2916 #define REG_A5XX_VFD_CONTROL_2 0x0000e402
2918 #define REG_A5XX_VFD_CONTROL_3 0x0000e403
2920 #define REG_A5XX_VFD_CONTROL_4 0x0000e404
2922 #define REG_A5XX_VFD_CONTROL_5 0x0000e405
2924 #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
2926 #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
2928 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
2930 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
2932 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
2934 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
2936 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
2938 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
2940 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
2941 #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
2942 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
2943 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
2945 return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
2947 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000
2948 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
2949 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
2951 return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
2953 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0xc0000000
2954 #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 30
2955 static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
2957 return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
2960 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
2962 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
2964 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
2965 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
2966 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
2967 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
2969 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
2971 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
2972 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
2973 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
2975 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
2978 #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
2980 #define REG_A5XX_SP_SP_CNTL 0x0000e580
2982 #define REG_A5XX_SP_VS_CONTROL_REG 0x0000e584
2983 #define A5XX_SP_VS_CONTROL_REG_ENABLED 0x00000001
2984 #define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
2985 #define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
2986 static inline uint32_t A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2988 return ((val) << A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2990 #define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
2991 #define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
2992 static inline uint32_t A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2994 return ((val) << A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2997 #define REG_A5XX_SP_FS_CONTROL_REG 0x0000e585
2998 #define A5XX_SP_FS_CONTROL_REG_ENABLED 0x00000001
2999 #define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3000 #define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3001 static inline uint32_t A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3003 return ((val) << A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3005 #define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3006 #define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3007 static inline uint32_t A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3009 return ((val) << A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3012 #define REG_A5XX_SP_HS_CONTROL_REG 0x0000e586
3013 #define A5XX_SP_HS_CONTROL_REG_ENABLED 0x00000001
3014 #define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3015 #define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3016 static inline uint32_t A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3018 return ((val) << A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3020 #define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3021 #define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3022 static inline uint32_t A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3024 return ((val) << A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3027 #define REG_A5XX_SP_DS_CONTROL_REG 0x0000e587
3028 #define A5XX_SP_DS_CONTROL_REG_ENABLED 0x00000001
3029 #define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3030 #define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3031 static inline uint32_t A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3033 return ((val) << A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3035 #define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3036 #define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3037 static inline uint32_t A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3039 return ((val) << A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3042 #define REG_A5XX_SP_GS_CONTROL_REG 0x0000e588
3043 #define A5XX_SP_GS_CONTROL_REG_ENABLED 0x00000001
3044 #define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3045 #define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3046 static inline uint32_t A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3048 return ((val) << A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3050 #define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3051 #define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3052 static inline uint32_t A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3054 return ((val) << A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3057 #define REG_A5XX_SP_CS_CONFIG 0x0000e589
3059 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
3061 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
3063 #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
3064 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3065 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3066 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3068 return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3070 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3071 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3072 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3074 return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3076 #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
3077 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
3079 #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
3080 #define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000001f
3081 #define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
3082 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
3084 return ((val >> 2) << A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
3087 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
3089 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
3090 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
3091 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
3092 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
3094 return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
3096 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
3097 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
3098 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
3100 return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
3102 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
3103 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
3104 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
3106 return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
3108 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
3109 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
3110 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
3112 return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
3115 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
3117 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
3118 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
3119 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
3120 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
3122 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
3124 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
3125 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
3126 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
3128 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
3130 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
3131 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
3132 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
3134 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
3136 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
3137 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
3138 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
3140 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
3143 #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
3145 #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
3147 #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
3149 #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
3150 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3151 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3152 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3154 return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3156 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3157 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3158 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3160 return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3162 #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
3163 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
3165 #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
3167 #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
3169 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
3171 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
3173 #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
3174 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
3175 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
3176 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
3178 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
3180 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
3181 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
3182 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
3184 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
3186 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
3187 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
3188 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
3190 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
3193 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
3195 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
3196 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
3197 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
3198 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
3200 return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
3202 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
3204 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
3206 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
3207 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
3208 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
3209 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
3211 return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
3214 #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
3216 #define REG_A5XX_SP_CS_CNTL_0 0x0000e5f0
3218 #define REG_A5XX_UNKNOWN_E600 0x0000e600
3220 #define REG_A5XX_UNKNOWN_E640 0x0000e640
3222 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
3223 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3224 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
3225 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3227 return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
3230 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
3231 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3232 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
3233 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3235 return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
3237 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3239 #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
3241 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
3243 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
3245 #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
3247 #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
3249 #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
3251 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
3253 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
3255 #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
3257 #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
3259 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
3261 #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
3263 #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
3264 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
3265 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
3266 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
3268 return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
3271 #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
3272 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
3273 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
3274 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
3276 return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
3279 #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
3280 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
3281 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
3282 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
3284 return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
3287 #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
3288 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
3289 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
3290 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
3292 return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
3294 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
3295 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
3296 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
3298 return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
3301 #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
3303 #define REG_A5XX_HLSQ_VS_CONTROL_REG 0x0000e78b
3304 #define A5XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00000001
3305 #define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3306 #define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3307 static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3309 return ((val) << A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3311 #define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3312 #define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3313 static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3315 return ((val) << A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3318 #define REG_A5XX_HLSQ_FS_CONTROL_REG 0x0000e78c
3319 #define A5XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00000001
3320 #define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3321 #define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3322 static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3324 return ((val) << A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3326 #define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3327 #define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3328 static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3330 return ((val) << A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3333 #define REG_A5XX_HLSQ_HS_CONTROL_REG 0x0000e78d
3334 #define A5XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00000001
3335 #define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3336 #define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3337 static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3339 return ((val) << A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3341 #define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3342 #define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3343 static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3345 return ((val) << A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3348 #define REG_A5XX_HLSQ_DS_CONTROL_REG 0x0000e78e
3349 #define A5XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00000001
3350 #define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3351 #define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3352 static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3354 return ((val) << A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3356 #define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3357 #define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3358 static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3360 return ((val) << A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3363 #define REG_A5XX_HLSQ_GS_CONTROL_REG 0x0000e78f
3364 #define A5XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00000001
3365 #define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3366 #define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3367 static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3369 return ((val) << A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3371 #define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3372 #define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3373 static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3375 return ((val) << A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3378 #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
3380 #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
3381 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
3382 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
3383 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
3385 return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
3388 #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
3389 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
3390 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
3391 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
3393 return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
3396 #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
3397 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
3398 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
3399 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
3401 return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
3404 #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
3405 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
3406 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
3407 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
3409 return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
3412 #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
3413 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
3414 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
3415 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
3417 return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
3420 #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
3421 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
3422 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
3423 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
3425 return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
3428 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
3430 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
3432 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
3434 #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
3436 #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
3438 #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
3440 #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
3442 #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
3444 #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
3446 #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
3448 #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
3450 #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
3452 #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
3454 #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
3456 #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
3458 #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
3460 #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
3462 #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
3464 #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
3466 #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
3468 #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
3470 #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
3472 #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
3474 #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
3476 #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
3478 #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
3480 #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
3482 #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
3484 #define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3 0x0000e7dc
3486 #define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_4 0x0000e7dd
3488 #define REG_A5XX_RB_2D_DST_FILL 0x00002101
3490 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107
3491 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
3492 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
3493 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3495 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
3497 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
3498 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
3499 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3501 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
3504 #define REG_A5XX_RB_2D_SRC_LO 0x00002108
3506 #define REG_A5XX_RB_2D_SRC_HI 0x00002109
3508 #define REG_A5XX_RB_2D_DST_INFO 0x00002110
3509 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3510 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3511 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3513 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
3515 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3516 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3517 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3519 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
3522 #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
3524 #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
3526 #define REG_A5XX_RB_2D_DST_LO 0x00002111
3528 #define REG_A5XX_RB_2D_DST_HI 0x00002112
3530 #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
3532 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
3534 #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
3535 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
3536 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
3537 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3539 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
3541 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
3542 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
3543 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3545 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
3548 #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
3549 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3550 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3551 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3553 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
3555 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3556 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3557 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3559 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
3562 #define REG_A5XX_TEX_SAMP_0 0x00000000
3563 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
3564 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
3565 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
3566 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
3568 return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
3570 #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
3571 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
3572 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
3574 return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
3576 #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
3577 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
3578 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
3580 return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
3582 #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
3583 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
3584 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
3586 return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
3588 #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
3589 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
3590 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
3592 return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
3594 #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
3595 #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
3596 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
3598 return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
3600 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
3601 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
3602 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
3604 return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
3607 #define REG_A5XX_TEX_SAMP_1 0x00000001
3608 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
3609 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
3610 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
3612 return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
3614 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
3615 #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
3616 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
3617 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
3618 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
3619 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
3621 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
3623 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
3624 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
3625 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
3627 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
3630 #define REG_A5XX_TEX_SAMP_2 0x00000002
3632 #define REG_A5XX_TEX_SAMP_3 0x00000003
3634 #define REG_A5XX_TEX_CONST_0 0x00000000
3635 #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
3636 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
3637 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
3639 return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
3641 #define A5XX_TEX_CONST_0_SRGB 0x00000004
3642 #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
3643 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
3644 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
3646 return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
3648 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
3649 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
3650 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
3652 return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
3654 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
3655 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
3656 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
3658 return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
3660 #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
3661 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
3662 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
3664 return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
3666 #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
3667 #define A5XX_TEX_CONST_0_FMT__SHIFT 22
3668 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
3670 return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
3672 #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
3673 #define A5XX_TEX_CONST_0_SWAP__SHIFT 30
3674 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
3676 return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
3679 #define REG_A5XX_TEX_CONST_1 0x00000001
3680 #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
3681 #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
3682 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
3684 return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
3686 #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
3687 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
3688 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
3690 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
3693 #define REG_A5XX_TEX_CONST_2 0x00000002
3694 #define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
3695 #define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
3696 static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val)
3698 return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK;
3700 #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
3701 #define A5XX_TEX_CONST_2_PITCH__SHIFT 7
3702 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
3704 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
3706 #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
3707 #define A5XX_TEX_CONST_2_TYPE__SHIFT 29
3708 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
3710 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
3713 #define REG_A5XX_TEX_CONST_3 0x00000003
3714 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
3715 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
3716 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
3718 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
3720 #define A5XX_TEX_CONST_3_FLAG 0x10000000
3722 #define REG_A5XX_TEX_CONST_4 0x00000004
3723 #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
3724 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
3725 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
3727 return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
3730 #define REG_A5XX_TEX_CONST_5 0x00000005
3731 #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
3732 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
3733 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
3735 return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
3737 #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
3738 #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
3739 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
3741 return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
3744 #define REG_A5XX_TEX_CONST_6 0x00000006
3746 #define REG_A5XX_TEX_CONST_7 0x00000007
3748 #define REG_A5XX_TEX_CONST_8 0x00000008
3750 #define REG_A5XX_TEX_CONST_9 0x00000009
3752 #define REG_A5XX_TEX_CONST_10 0x0000000a
3754 #define REG_A5XX_TEX_CONST_11 0x0000000b
3757 #endif /* A5XX_XML */