2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <linux/module.h>
30 #include <linux/pm_runtime.h>
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_fourcc.h>
34 #include <drm/drm_plane_helper.h>
36 #include "display/intel_atomic.h"
37 #include "display/intel_display_types.h"
38 #include "display/intel_fbc.h"
39 #include "display/intel_sprite.h"
43 #include "i915_trace.h"
45 #include "intel_sideband.h"
46 #include "../../../platform/x86/intel_ips.h"
51 * RC6 is a special power stage which allows the GPU to enter an very
52 * low-voltage mode when idle, using down to 0V while at this stage. This
53 * stage is entered automatically when the GPU is idle when RC6 support is
54 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
56 * There are different RC6 modes available in Intel GPU, which differentiate
57 * among each other with the latency required to enter and leave RC6 and
58 * voltage consumed by the GPU in different states.
60 * The combination of the following flags define which states GPU is allowed
61 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
62 * RC6pp is deepest RC6. Their support by hardware varies according to the
63 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
64 * which brings the most power savings; deeper states save more power, but
65 * require higher latency to switch to and wake up.
68 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
70 if (HAS_LLC(dev_priv)) {
72 * WaCompressedResourceDisplayNewHashMode:skl,kbl
73 * Display WA #0390: skl,kbl
75 * Must match Sampler, Pixel Back End, and Media. See
76 * WaCompressedResourceSamplerPbeMediaNewHashMode.
78 I915_WRITE(CHICKEN_PAR1_1,
79 I915_READ(CHICKEN_PAR1_1) |
80 SKL_DE_COMPRESSED_HASH_MODE);
83 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
84 I915_WRITE(CHICKEN_PAR1_1,
85 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
87 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
88 I915_WRITE(GEN8_CHICKEN_DCPR_1,
89 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
91 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
92 /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
93 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
95 DISP_FBC_MEMORY_WAKE);
97 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
98 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
99 ILK_DPFC_DISABLE_DUMMY0);
101 if (IS_SKYLAKE(dev_priv)) {
102 /* WaDisableDopClockGating */
103 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
104 & ~GEN7_DOP_CLOCK_GATE_ENABLE);
108 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
110 gen9_init_clock_gating(dev_priv);
112 /* WaDisableSDEUnitClockGating:bxt */
113 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
114 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
118 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
120 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
121 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
124 * Wa: Backlight PWM may stop in the asserted state, causing backlight
127 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
128 PWM1_GATING_DIS | PWM2_GATING_DIS);
131 * Lower the display internal timeout.
132 * This is needed to avoid any hard hangs when DSI port PLL
133 * is off and a MMIO access is attempted by any privilege
134 * application, using batch buffers or any other means.
136 I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
139 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
141 gen9_init_clock_gating(dev_priv);
144 * WaDisablePWMClockGating:glk
145 * Backlight PWM may stop in the asserted state, causing backlight
148 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
149 PWM1_GATING_DIS | PWM2_GATING_DIS);
151 /* WaDDIIOTimeout:glk */
152 if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
153 u32 val = I915_READ(CHICKEN_MISC_2);
154 val &= ~(GLK_CL0_PWR_DOWN |
157 I915_WRITE(CHICKEN_MISC_2, val);
162 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
166 tmp = I915_READ(CLKCFG);
168 switch (tmp & CLKCFG_FSB_MASK) {
170 dev_priv->fsb_freq = 533; /* 133*4 */
173 dev_priv->fsb_freq = 800; /* 200*4 */
176 dev_priv->fsb_freq = 667; /* 167*4 */
179 dev_priv->fsb_freq = 400; /* 100*4 */
183 switch (tmp & CLKCFG_MEM_MASK) {
185 dev_priv->mem_freq = 533;
188 dev_priv->mem_freq = 667;
191 dev_priv->mem_freq = 800;
195 /* detect pineview DDR3 setting */
196 tmp = I915_READ(CSHRDDR3CTL);
197 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
200 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
204 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
205 csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
207 switch (ddrpll & 0xff) {
209 dev_priv->mem_freq = 800;
212 dev_priv->mem_freq = 1066;
215 dev_priv->mem_freq = 1333;
218 dev_priv->mem_freq = 1600;
221 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
223 dev_priv->mem_freq = 0;
227 dev_priv->ips.r_t = dev_priv->mem_freq;
229 switch (csipll & 0x3ff) {
231 dev_priv->fsb_freq = 3200;
234 dev_priv->fsb_freq = 3733;
237 dev_priv->fsb_freq = 4266;
240 dev_priv->fsb_freq = 4800;
243 dev_priv->fsb_freq = 5333;
246 dev_priv->fsb_freq = 5866;
249 dev_priv->fsb_freq = 6400;
252 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
254 dev_priv->fsb_freq = 0;
258 if (dev_priv->fsb_freq == 3200) {
259 dev_priv->ips.c_m = 0;
260 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
261 dev_priv->ips.c_m = 1;
263 dev_priv->ips.c_m = 2;
267 static const struct cxsr_latency cxsr_latency_table[] = {
268 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
269 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
270 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
271 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
272 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
274 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
275 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
276 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
277 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
278 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
280 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
281 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
282 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
283 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
284 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
286 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
287 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
288 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
289 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
290 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
292 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
293 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
294 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
295 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
296 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
298 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
299 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
300 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
301 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
302 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
305 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
310 const struct cxsr_latency *latency;
313 if (fsb == 0 || mem == 0)
316 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
317 latency = &cxsr_latency_table[i];
318 if (is_desktop == latency->is_desktop &&
319 is_ddr3 == latency->is_ddr3 &&
320 fsb == latency->fsb_freq && mem == latency->mem_freq)
324 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
329 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
333 vlv_punit_get(dev_priv);
335 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
337 val &= ~FORCE_DDR_HIGH_FREQ;
339 val |= FORCE_DDR_HIGH_FREQ;
340 val &= ~FORCE_DDR_LOW_FREQ;
341 val |= FORCE_DDR_FREQ_REQ_ACK;
342 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
344 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
345 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
346 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
348 vlv_punit_put(dev_priv);
351 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
355 vlv_punit_get(dev_priv);
357 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
359 val |= DSP_MAXFIFO_PM5_ENABLE;
361 val &= ~DSP_MAXFIFO_PM5_ENABLE;
362 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
364 vlv_punit_put(dev_priv);
367 #define FW_WM(value, plane) \
368 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
370 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
375 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
376 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
377 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
378 POSTING_READ(FW_BLC_SELF_VLV);
379 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
380 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
381 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
382 POSTING_READ(FW_BLC_SELF);
383 } else if (IS_PINEVIEW(dev_priv)) {
384 val = I915_READ(DSPFW3);
385 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
387 val |= PINEVIEW_SELF_REFRESH_EN;
389 val &= ~PINEVIEW_SELF_REFRESH_EN;
390 I915_WRITE(DSPFW3, val);
391 POSTING_READ(DSPFW3);
392 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
393 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
394 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
395 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
396 I915_WRITE(FW_BLC_SELF, val);
397 POSTING_READ(FW_BLC_SELF);
398 } else if (IS_I915GM(dev_priv)) {
400 * FIXME can't find a bit like this for 915G, and
401 * and yet it does have the related watermark in
402 * FW_BLC_SELF. What's going on?
404 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
405 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
406 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
407 I915_WRITE(INSTPM, val);
408 POSTING_READ(INSTPM);
413 trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
415 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
416 enableddisabled(enable),
417 enableddisabled(was_enabled));
423 * intel_set_memory_cxsr - Configure CxSR state
424 * @dev_priv: i915 device
425 * @enable: Allow vs. disallow CxSR
427 * Allow or disallow the system to enter a special CxSR
428 * (C-state self refresh) state. What typically happens in CxSR mode
429 * is that several display FIFOs may get combined into a single larger
430 * FIFO for a particular plane (so called max FIFO mode) to allow the
431 * system to defer memory fetches longer, and the memory will enter
434 * Note that enabling CxSR does not guarantee that the system enter
435 * this special mode, nor does it guarantee that the system stays
436 * in that mode once entered. So this just allows/disallows the system
437 * to autonomously utilize the CxSR mode. Other factors such as core
438 * C-states will affect when/if the system actually enters/exits the
441 * Note that on VLV/CHV this actually only controls the max FIFO mode,
442 * and the system is free to enter/exit memory self refresh at any time
443 * even when the use of CxSR has been disallowed.
445 * While the system is actually in the CxSR/max FIFO mode, some plane
446 * control registers will not get latched on vblank. Thus in order to
447 * guarantee the system will respond to changes in the plane registers
448 * we must always disallow CxSR prior to making changes to those registers.
449 * Unfortunately the system will re-evaluate the CxSR conditions at
450 * frame start which happens after vblank start (which is when the plane
451 * registers would get latched), so we can't proceed with the plane update
452 * during the same frame where we disallowed CxSR.
454 * Certain platforms also have a deeper HPLL SR mode. Fortunately the
455 * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
456 * the hardware w.r.t. HPLL SR when writing to plane registers.
457 * Disallowing just CxSR is sufficient.
459 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
463 mutex_lock(&dev_priv->wm.wm_mutex);
464 ret = _intel_set_memory_cxsr(dev_priv, enable);
465 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
466 dev_priv->wm.vlv.cxsr = enable;
467 else if (IS_G4X(dev_priv))
468 dev_priv->wm.g4x.cxsr = enable;
469 mutex_unlock(&dev_priv->wm.wm_mutex);
475 * Latency for FIFO fetches is dependent on several factors:
476 * - memory configuration (speed, channels)
478 * - current MCH state
479 * It can be fairly high in some situations, so here we assume a fairly
480 * pessimal value. It's a tradeoff between extra memory fetches (if we
481 * set this value too high, the FIFO will fetch frequently to stay full)
482 * and power consumption (set it too low to save power and we might see
483 * FIFO underruns and display "flicker").
485 * A value of 5us seems to be a good balance; safe for very low end
486 * platforms but not overly aggressive on lower latency configs.
488 static const int pessimal_latency_ns = 5000;
490 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
491 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
493 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
495 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
496 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
497 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
498 enum pipe pipe = crtc->pipe;
499 int sprite0_start, sprite1_start;
502 u32 dsparb, dsparb2, dsparb3;
504 dsparb = I915_READ(DSPARB);
505 dsparb2 = I915_READ(DSPARB2);
506 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
507 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
510 dsparb = I915_READ(DSPARB);
511 dsparb2 = I915_READ(DSPARB2);
512 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
513 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
516 dsparb2 = I915_READ(DSPARB2);
517 dsparb3 = I915_READ(DSPARB3);
518 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
519 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
526 fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
527 fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
528 fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
529 fifo_state->plane[PLANE_CURSOR] = 63;
532 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
533 enum i9xx_plane_id i9xx_plane)
535 u32 dsparb = I915_READ(DSPARB);
538 size = dsparb & 0x7f;
539 if (i9xx_plane == PLANE_B)
540 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
542 DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
543 dsparb, plane_name(i9xx_plane), size);
548 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
549 enum i9xx_plane_id i9xx_plane)
551 u32 dsparb = I915_READ(DSPARB);
554 size = dsparb & 0x1ff;
555 if (i9xx_plane == PLANE_B)
556 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
557 size >>= 1; /* Convert to cachelines */
559 DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
560 dsparb, plane_name(i9xx_plane), size);
565 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
566 enum i9xx_plane_id i9xx_plane)
568 u32 dsparb = I915_READ(DSPARB);
571 size = dsparb & 0x7f;
572 size >>= 2; /* Convert to cachelines */
574 DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
575 dsparb, plane_name(i9xx_plane), size);
580 /* Pineview has different values for various configs */
581 static const struct intel_watermark_params pineview_display_wm = {
582 .fifo_size = PINEVIEW_DISPLAY_FIFO,
583 .max_wm = PINEVIEW_MAX_WM,
584 .default_wm = PINEVIEW_DFT_WM,
585 .guard_size = PINEVIEW_GUARD_WM,
586 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
588 static const struct intel_watermark_params pineview_display_hplloff_wm = {
589 .fifo_size = PINEVIEW_DISPLAY_FIFO,
590 .max_wm = PINEVIEW_MAX_WM,
591 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
592 .guard_size = PINEVIEW_GUARD_WM,
593 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
595 static const struct intel_watermark_params pineview_cursor_wm = {
596 .fifo_size = PINEVIEW_CURSOR_FIFO,
597 .max_wm = PINEVIEW_CURSOR_MAX_WM,
598 .default_wm = PINEVIEW_CURSOR_DFT_WM,
599 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
600 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
602 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
603 .fifo_size = PINEVIEW_CURSOR_FIFO,
604 .max_wm = PINEVIEW_CURSOR_MAX_WM,
605 .default_wm = PINEVIEW_CURSOR_DFT_WM,
606 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
607 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
609 static const struct intel_watermark_params i965_cursor_wm_info = {
610 .fifo_size = I965_CURSOR_FIFO,
611 .max_wm = I965_CURSOR_MAX_WM,
612 .default_wm = I965_CURSOR_DFT_WM,
614 .cacheline_size = I915_FIFO_LINE_SIZE,
616 static const struct intel_watermark_params i945_wm_info = {
617 .fifo_size = I945_FIFO_SIZE,
618 .max_wm = I915_MAX_WM,
621 .cacheline_size = I915_FIFO_LINE_SIZE,
623 static const struct intel_watermark_params i915_wm_info = {
624 .fifo_size = I915_FIFO_SIZE,
625 .max_wm = I915_MAX_WM,
628 .cacheline_size = I915_FIFO_LINE_SIZE,
630 static const struct intel_watermark_params i830_a_wm_info = {
631 .fifo_size = I855GM_FIFO_SIZE,
632 .max_wm = I915_MAX_WM,
635 .cacheline_size = I830_FIFO_LINE_SIZE,
637 static const struct intel_watermark_params i830_bc_wm_info = {
638 .fifo_size = I855GM_FIFO_SIZE,
639 .max_wm = I915_MAX_WM/2,
642 .cacheline_size = I830_FIFO_LINE_SIZE,
644 static const struct intel_watermark_params i845_wm_info = {
645 .fifo_size = I830_FIFO_SIZE,
646 .max_wm = I915_MAX_WM,
649 .cacheline_size = I830_FIFO_LINE_SIZE,
653 * intel_wm_method1 - Method 1 / "small buffer" watermark formula
654 * @pixel_rate: Pipe pixel rate in kHz
655 * @cpp: Plane bytes per pixel
656 * @latency: Memory wakeup latency in 0.1us units
658 * Compute the watermark using the method 1 or "small buffer"
659 * formula. The caller may additonally add extra cachelines
660 * to account for TLB misses and clock crossings.
662 * This method is concerned with the short term drain rate
663 * of the FIFO, ie. it does not account for blanking periods
664 * which would effectively reduce the average drain rate across
665 * a longer period. The name "small" refers to the fact the
666 * FIFO is relatively small compared to the amount of data
669 * The FIFO level vs. time graph might look something like:
673 * __---__---__ (- plane active, _ blanking)
676 * or perhaps like this:
679 * __----__----__ (- plane active, _ blanking)
683 * The watermark in bytes
685 static unsigned int intel_wm_method1(unsigned int pixel_rate,
687 unsigned int latency)
691 ret = mul_u32_u32(pixel_rate, cpp * latency);
692 ret = DIV_ROUND_UP_ULL(ret, 10000);
698 * intel_wm_method2 - Method 2 / "large buffer" watermark formula
699 * @pixel_rate: Pipe pixel rate in kHz
700 * @htotal: Pipe horizontal total
701 * @width: Plane width in pixels
702 * @cpp: Plane bytes per pixel
703 * @latency: Memory wakeup latency in 0.1us units
705 * Compute the watermark using the method 2 or "large buffer"
706 * formula. The caller may additonally add extra cachelines
707 * to account for TLB misses and clock crossings.
709 * This method is concerned with the long term drain rate
710 * of the FIFO, ie. it does account for blanking periods
711 * which effectively reduce the average drain rate across
712 * a longer period. The name "large" refers to the fact the
713 * FIFO is relatively large compared to the amount of data
716 * The FIFO level vs. time graph might look something like:
721 * __ --__--__--__--__--__--__ (- plane active, _ blanking)
725 * The watermark in bytes
727 static unsigned int intel_wm_method2(unsigned int pixel_rate,
731 unsigned int latency)
736 * FIXME remove once all users are computing
737 * watermarks in the correct place.
739 if (WARN_ON_ONCE(htotal == 0))
742 ret = (latency * pixel_rate) / (htotal * 10000);
743 ret = (ret + 1) * width * cpp;
749 * intel_calculate_wm - calculate watermark level
750 * @pixel_rate: pixel clock
751 * @wm: chip FIFO params
752 * @fifo_size: size of the FIFO buffer
753 * @cpp: bytes per pixel
754 * @latency_ns: memory latency for the platform
756 * Calculate the watermark level (the level at which the display plane will
757 * start fetching from memory again). Each chip has a different display
758 * FIFO size and allocation, so the caller needs to figure that out and pass
759 * in the correct intel_watermark_params structure.
761 * As the pixel clock runs, the FIFO will be drained at a rate that depends
762 * on the pixel size. When it reaches the watermark level, it'll start
763 * fetching FIFO line sized based chunks from memory until the FIFO fills
764 * past the watermark point. If the FIFO drains completely, a FIFO underrun
765 * will occur, and a display engine hang could result.
767 static unsigned int intel_calculate_wm(int pixel_rate,
768 const struct intel_watermark_params *wm,
769 int fifo_size, int cpp,
770 unsigned int latency_ns)
772 int entries, wm_size;
775 * Note: we need to make sure we don't overflow for various clock &
777 * clocks go from a few thousand to several hundred thousand.
778 * latency is usually a few thousand
780 entries = intel_wm_method1(pixel_rate, cpp,
782 entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
784 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
786 wm_size = fifo_size - entries;
787 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
789 /* Don't promote wm_size to unsigned... */
790 if (wm_size > wm->max_wm)
791 wm_size = wm->max_wm;
793 wm_size = wm->default_wm;
796 * Bspec seems to indicate that the value shouldn't be lower than
797 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
798 * Lets go for 8 which is the burst size since certain platforms
799 * already use a hardcoded 8 (which is what the spec says should be
808 static bool is_disabling(int old, int new, int threshold)
810 return old >= threshold && new < threshold;
813 static bool is_enabling(int old, int new, int threshold)
815 return old < threshold && new >= threshold;
818 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
820 return dev_priv->wm.max_level + 1;
823 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
824 const struct intel_plane_state *plane_state)
826 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
828 /* FIXME check the 'enable' instead */
829 if (!crtc_state->base.active)
833 * Treat cursor with fb as always visible since cursor updates
834 * can happen faster than the vrefresh rate, and the current
835 * watermark code doesn't handle that correctly. Cursor updates
836 * which set/clear the fb or change the cursor size are going
837 * to get throttled by intel_legacy_cursor_update() to work
838 * around this problem with the watermark code.
840 if (plane->id == PLANE_CURSOR)
841 return plane_state->base.fb != NULL;
843 return plane_state->base.visible;
846 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
848 struct intel_crtc *crtc, *enabled = NULL;
850 for_each_intel_crtc(&dev_priv->drm, crtc) {
851 if (intel_crtc_active(crtc)) {
861 static void pineview_update_wm(struct intel_crtc *unused_crtc)
863 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
864 struct intel_crtc *crtc;
865 const struct cxsr_latency *latency;
869 latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
874 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
875 intel_set_memory_cxsr(dev_priv, false);
879 crtc = single_enabled_crtc(dev_priv);
881 const struct drm_display_mode *adjusted_mode =
882 &crtc->config->base.adjusted_mode;
883 const struct drm_framebuffer *fb =
884 crtc->base.primary->state->fb;
885 int cpp = fb->format->cpp[0];
886 int clock = adjusted_mode->crtc_clock;
889 wm = intel_calculate_wm(clock, &pineview_display_wm,
890 pineview_display_wm.fifo_size,
891 cpp, latency->display_sr);
892 reg = I915_READ(DSPFW1);
893 reg &= ~DSPFW_SR_MASK;
894 reg |= FW_WM(wm, SR);
895 I915_WRITE(DSPFW1, reg);
896 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
899 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
900 pineview_display_wm.fifo_size,
901 4, latency->cursor_sr);
902 reg = I915_READ(DSPFW3);
903 reg &= ~DSPFW_CURSOR_SR_MASK;
904 reg |= FW_WM(wm, CURSOR_SR);
905 I915_WRITE(DSPFW3, reg);
907 /* Display HPLL off SR */
908 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
909 pineview_display_hplloff_wm.fifo_size,
910 cpp, latency->display_hpll_disable);
911 reg = I915_READ(DSPFW3);
912 reg &= ~DSPFW_HPLL_SR_MASK;
913 reg |= FW_WM(wm, HPLL_SR);
914 I915_WRITE(DSPFW3, reg);
916 /* cursor HPLL off SR */
917 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
918 pineview_display_hplloff_wm.fifo_size,
919 4, latency->cursor_hpll_disable);
920 reg = I915_READ(DSPFW3);
921 reg &= ~DSPFW_HPLL_CURSOR_MASK;
922 reg |= FW_WM(wm, HPLL_CURSOR);
923 I915_WRITE(DSPFW3, reg);
924 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
926 intel_set_memory_cxsr(dev_priv, true);
928 intel_set_memory_cxsr(dev_priv, false);
933 * Documentation says:
934 * "If the line size is small, the TLB fetches can get in the way of the
935 * data fetches, causing some lag in the pixel data return which is not
936 * accounted for in the above formulas. The following adjustment only
937 * needs to be applied if eight whole lines fit in the buffer at once.
938 * The WM is adjusted upwards by the difference between the FIFO size
939 * and the size of 8 whole lines. This adjustment is always performed
940 * in the actual pixel depth regardless of whether FBC is enabled or not."
942 static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
944 int tlb_miss = fifo_size * 64 - width * cpp * 8;
946 return max(0, tlb_miss);
949 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
950 const struct g4x_wm_values *wm)
954 for_each_pipe(dev_priv, pipe)
955 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
958 FW_WM(wm->sr.plane, SR) |
959 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
960 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
961 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
963 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
964 FW_WM(wm->sr.fbc, FBC_SR) |
965 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
966 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
967 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
968 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
970 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
971 FW_WM(wm->sr.cursor, CURSOR_SR) |
972 FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
973 FW_WM(wm->hpll.plane, HPLL_SR));
975 POSTING_READ(DSPFW1);
978 #define FW_WM_VLV(value, plane) \
979 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
981 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
982 const struct vlv_wm_values *wm)
986 for_each_pipe(dev_priv, pipe) {
987 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
989 I915_WRITE(VLV_DDL(pipe),
990 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
991 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
992 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
993 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
997 * Zero the (unused) WM1 watermarks, and also clear all the
998 * high order bits so that there are no out of bounds values
999 * present in the registers during the reprogramming.
1001 I915_WRITE(DSPHOWM, 0);
1002 I915_WRITE(DSPHOWM1, 0);
1003 I915_WRITE(DSPFW4, 0);
1004 I915_WRITE(DSPFW5, 0);
1005 I915_WRITE(DSPFW6, 0);
1008 FW_WM(wm->sr.plane, SR) |
1009 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1010 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1011 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1013 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1014 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1015 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1017 FW_WM(wm->sr.cursor, CURSOR_SR));
1019 if (IS_CHERRYVIEW(dev_priv)) {
1020 I915_WRITE(DSPFW7_CHV,
1021 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1022 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1023 I915_WRITE(DSPFW8_CHV,
1024 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1025 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1026 I915_WRITE(DSPFW9_CHV,
1027 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1028 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1030 FW_WM(wm->sr.plane >> 9, SR_HI) |
1031 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1032 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1033 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1034 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1035 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1036 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1037 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1038 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1039 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1042 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1043 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1045 FW_WM(wm->sr.plane >> 9, SR_HI) |
1046 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1047 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1048 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1049 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1050 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1051 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1054 POSTING_READ(DSPFW1);
1059 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1061 /* all latencies in usec */
1062 dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1063 dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1064 dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1066 dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1069 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1072 * DSPCNTR[13] supposedly controls whether the
1073 * primary plane can use the FIFO space otherwise
1074 * reserved for the sprite plane. It's not 100% clear
1075 * what the actual FIFO size is, but it looks like we
1076 * can happily set both primary and sprite watermarks
1077 * up to 127 cachelines. So that would seem to mean
1078 * that either DSPCNTR[13] doesn't do anything, or that
1079 * the total FIFO is >= 256 cachelines in size. Either
1080 * way, we don't seem to have to worry about this
1081 * repartitioning as the maximum watermark value the
1082 * register can hold for each plane is lower than the
1083 * minimum FIFO size.
1089 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1091 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1093 MISSING_CASE(plane_id);
1098 static int g4x_fbc_fifo_size(int level)
1101 case G4X_WM_LEVEL_SR:
1103 case G4X_WM_LEVEL_HPLL:
1106 MISSING_CASE(level);
1111 static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1112 const struct intel_plane_state *plane_state,
1115 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1116 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1117 const struct drm_display_mode *adjusted_mode =
1118 &crtc_state->base.adjusted_mode;
1119 unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1120 unsigned int clock, htotal, cpp, width, wm;
1125 if (!intel_wm_plane_visible(crtc_state, plane_state))
1128 cpp = plane_state->base.fb->format->cpp[0];
1131 * Not 100% sure which way ELK should go here as the
1132 * spec only says CL/CTG should assume 32bpp and BW
1133 * doesn't need to. But as these things followed the
1134 * mobile vs. desktop lines on gen3 as well, let's
1135 * assume ELK doesn't need this.
1137 * The spec also fails to list such a restriction for
1138 * the HPLL watermark, which seems a little strange.
1139 * Let's use 32bpp for the HPLL watermark as well.
1141 if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1142 level != G4X_WM_LEVEL_NORMAL)
1145 clock = adjusted_mode->crtc_clock;
1146 htotal = adjusted_mode->crtc_htotal;
1148 if (plane->id == PLANE_CURSOR)
1149 width = plane_state->base.crtc_w;
1151 width = drm_rect_width(&plane_state->base.dst);
1153 if (plane->id == PLANE_CURSOR) {
1154 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1155 } else if (plane->id == PLANE_PRIMARY &&
1156 level == G4X_WM_LEVEL_NORMAL) {
1157 wm = intel_wm_method1(clock, cpp, latency);
1159 unsigned int small, large;
1161 small = intel_wm_method1(clock, cpp, latency);
1162 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1164 wm = min(small, large);
1167 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1170 wm = DIV_ROUND_UP(wm, 64) + 2;
1172 return min_t(unsigned int, wm, USHRT_MAX);
1175 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1176 int level, enum plane_id plane_id, u16 value)
1178 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1181 for (; level < intel_wm_num_levels(dev_priv); level++) {
1182 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1184 dirty |= raw->plane[plane_id] != value;
1185 raw->plane[plane_id] = value;
1191 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1192 int level, u16 value)
1194 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1197 /* NORMAL level doesn't have an FBC watermark */
1198 level = max(level, G4X_WM_LEVEL_SR);
1200 for (; level < intel_wm_num_levels(dev_priv); level++) {
1201 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1203 dirty |= raw->fbc != value;
1210 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
1211 const struct intel_plane_state *plane_state,
1214 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1215 const struct intel_plane_state *plane_state)
1217 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1218 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1219 enum plane_id plane_id = plane->id;
1223 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1224 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1225 if (plane_id == PLANE_PRIMARY)
1226 dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1230 for (level = 0; level < num_levels; level++) {
1231 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1234 wm = g4x_compute_wm(crtc_state, plane_state, level);
1235 max_wm = g4x_plane_fifo_size(plane_id, level);
1240 dirty |= raw->plane[plane_id] != wm;
1241 raw->plane[plane_id] = wm;
1243 if (plane_id != PLANE_PRIMARY ||
1244 level == G4X_WM_LEVEL_NORMAL)
1247 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1248 raw->plane[plane_id]);
1249 max_wm = g4x_fbc_fifo_size(level);
1252 * FBC wm is not mandatory as we
1253 * can always just disable its use.
1258 dirty |= raw->fbc != wm;
1262 /* mark watermarks as invalid */
1263 dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1265 if (plane_id == PLANE_PRIMARY)
1266 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1270 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1272 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1273 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1274 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1276 if (plane_id == PLANE_PRIMARY)
1277 DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1278 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1279 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1285 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1286 enum plane_id plane_id, int level)
1288 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1290 return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1293 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1296 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1298 if (level > dev_priv->wm.max_level)
1301 return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1302 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1303 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1306 /* mark all levels starting from 'level' as invalid */
1307 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1308 struct g4x_wm_state *wm_state, int level)
1310 if (level <= G4X_WM_LEVEL_NORMAL) {
1311 enum plane_id plane_id;
1313 for_each_plane_id_on_crtc(crtc, plane_id)
1314 wm_state->wm.plane[plane_id] = USHRT_MAX;
1317 if (level <= G4X_WM_LEVEL_SR) {
1318 wm_state->cxsr = false;
1319 wm_state->sr.cursor = USHRT_MAX;
1320 wm_state->sr.plane = USHRT_MAX;
1321 wm_state->sr.fbc = USHRT_MAX;
1324 if (level <= G4X_WM_LEVEL_HPLL) {
1325 wm_state->hpll_en = false;
1326 wm_state->hpll.cursor = USHRT_MAX;
1327 wm_state->hpll.plane = USHRT_MAX;
1328 wm_state->hpll.fbc = USHRT_MAX;
1332 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1334 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1335 struct intel_atomic_state *state =
1336 to_intel_atomic_state(crtc_state->base.state);
1337 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1338 int num_active_planes = hweight32(crtc_state->active_planes &
1339 ~BIT(PLANE_CURSOR));
1340 const struct g4x_pipe_wm *raw;
1341 const struct intel_plane_state *old_plane_state;
1342 const struct intel_plane_state *new_plane_state;
1343 struct intel_plane *plane;
1344 enum plane_id plane_id;
1346 unsigned int dirty = 0;
1348 for_each_oldnew_intel_plane_in_state(state, plane,
1350 new_plane_state, i) {
1351 if (new_plane_state->base.crtc != &crtc->base &&
1352 old_plane_state->base.crtc != &crtc->base)
1355 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1356 dirty |= BIT(plane->id);
1362 level = G4X_WM_LEVEL_NORMAL;
1363 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1366 raw = &crtc_state->wm.g4x.raw[level];
1367 for_each_plane_id_on_crtc(crtc, plane_id)
1368 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1370 level = G4X_WM_LEVEL_SR;
1372 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1375 raw = &crtc_state->wm.g4x.raw[level];
1376 wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1377 wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1378 wm_state->sr.fbc = raw->fbc;
1380 wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1382 level = G4X_WM_LEVEL_HPLL;
1384 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1387 raw = &crtc_state->wm.g4x.raw[level];
1388 wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1389 wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1390 wm_state->hpll.fbc = raw->fbc;
1392 wm_state->hpll_en = wm_state->cxsr;
1397 if (level == G4X_WM_LEVEL_NORMAL)
1400 /* invalidate the higher levels */
1401 g4x_invalidate_wms(crtc, wm_state, level);
1404 * Determine if the FBC watermark(s) can be used. IF
1405 * this isn't the case we prefer to disable the FBC
1406 ( watermark(s) rather than disable the SR/HPLL
1407 * level(s) entirely.
1409 wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
1411 if (level >= G4X_WM_LEVEL_SR &&
1412 wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1413 wm_state->fbc_en = false;
1414 else if (level >= G4X_WM_LEVEL_HPLL &&
1415 wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1416 wm_state->fbc_en = false;
1421 static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
1423 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1424 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1425 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1426 struct intel_atomic_state *intel_state =
1427 to_intel_atomic_state(new_crtc_state->base.state);
1428 const struct intel_crtc_state *old_crtc_state =
1429 intel_atomic_get_old_crtc_state(intel_state, crtc);
1430 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
1431 enum plane_id plane_id;
1433 if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
1434 *intermediate = *optimal;
1436 intermediate->cxsr = false;
1437 intermediate->hpll_en = false;
1441 intermediate->cxsr = optimal->cxsr && active->cxsr &&
1442 !new_crtc_state->disable_cxsr;
1443 intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1444 !new_crtc_state->disable_cxsr;
1445 intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1447 for_each_plane_id_on_crtc(crtc, plane_id) {
1448 intermediate->wm.plane[plane_id] =
1449 max(optimal->wm.plane[plane_id],
1450 active->wm.plane[plane_id]);
1452 WARN_ON(intermediate->wm.plane[plane_id] >
1453 g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1456 intermediate->sr.plane = max(optimal->sr.plane,
1458 intermediate->sr.cursor = max(optimal->sr.cursor,
1460 intermediate->sr.fbc = max(optimal->sr.fbc,
1463 intermediate->hpll.plane = max(optimal->hpll.plane,
1464 active->hpll.plane);
1465 intermediate->hpll.cursor = max(optimal->hpll.cursor,
1466 active->hpll.cursor);
1467 intermediate->hpll.fbc = max(optimal->hpll.fbc,
1470 WARN_ON((intermediate->sr.plane >
1471 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1472 intermediate->sr.cursor >
1473 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1474 intermediate->cxsr);
1475 WARN_ON((intermediate->sr.plane >
1476 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1477 intermediate->sr.cursor >
1478 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1479 intermediate->hpll_en);
1481 WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1482 intermediate->fbc_en && intermediate->cxsr);
1483 WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1484 intermediate->fbc_en && intermediate->hpll_en);
1488 * If our intermediate WM are identical to the final WM, then we can
1489 * omit the post-vblank programming; only update if it's different.
1491 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1492 new_crtc_state->wm.need_postvbl_update = true;
1497 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1498 struct g4x_wm_values *wm)
1500 struct intel_crtc *crtc;
1501 int num_active_crtcs = 0;
1507 for_each_intel_crtc(&dev_priv->drm, crtc) {
1508 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1513 if (!wm_state->cxsr)
1515 if (!wm_state->hpll_en)
1516 wm->hpll_en = false;
1517 if (!wm_state->fbc_en)
1523 if (num_active_crtcs != 1) {
1525 wm->hpll_en = false;
1529 for_each_intel_crtc(&dev_priv->drm, crtc) {
1530 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1531 enum pipe pipe = crtc->pipe;
1533 wm->pipe[pipe] = wm_state->wm;
1534 if (crtc->active && wm->cxsr)
1535 wm->sr = wm_state->sr;
1536 if (crtc->active && wm->hpll_en)
1537 wm->hpll = wm_state->hpll;
1541 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1543 struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1544 struct g4x_wm_values new_wm = {};
1546 g4x_merge_wm(dev_priv, &new_wm);
1548 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1551 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1552 _intel_set_memory_cxsr(dev_priv, false);
1554 g4x_write_wm_values(dev_priv, &new_wm);
1556 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1557 _intel_set_memory_cxsr(dev_priv, true);
1562 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1563 struct intel_crtc_state *crtc_state)
1565 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1566 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1568 mutex_lock(&dev_priv->wm.wm_mutex);
1569 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1570 g4x_program_watermarks(dev_priv);
1571 mutex_unlock(&dev_priv->wm.wm_mutex);
1574 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1575 struct intel_crtc_state *crtc_state)
1577 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1578 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1580 if (!crtc_state->wm.need_postvbl_update)
1583 mutex_lock(&dev_priv->wm.wm_mutex);
1584 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1585 g4x_program_watermarks(dev_priv);
1586 mutex_unlock(&dev_priv->wm.wm_mutex);
1589 /* latency must be in 0.1us units. */
1590 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1591 unsigned int htotal,
1594 unsigned int latency)
1598 ret = intel_wm_method2(pixel_rate, htotal,
1599 width, cpp, latency);
1600 ret = DIV_ROUND_UP(ret, 64);
1605 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1607 /* all latencies in usec */
1608 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1610 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1612 if (IS_CHERRYVIEW(dev_priv)) {
1613 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1614 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1616 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1620 static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1621 const struct intel_plane_state *plane_state,
1624 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1625 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1626 const struct drm_display_mode *adjusted_mode =
1627 &crtc_state->base.adjusted_mode;
1628 unsigned int clock, htotal, cpp, width, wm;
1630 if (dev_priv->wm.pri_latency[level] == 0)
1633 if (!intel_wm_plane_visible(crtc_state, plane_state))
1636 cpp = plane_state->base.fb->format->cpp[0];
1637 clock = adjusted_mode->crtc_clock;
1638 htotal = adjusted_mode->crtc_htotal;
1639 width = crtc_state->pipe_src_w;
1641 if (plane->id == PLANE_CURSOR) {
1643 * FIXME the formula gives values that are
1644 * too big for the cursor FIFO, and hence we
1645 * would never be able to use cursors. For
1646 * now just hardcode the watermark.
1650 wm = vlv_wm_method2(clock, htotal, width, cpp,
1651 dev_priv->wm.pri_latency[level] * 10);
1654 return min_t(unsigned int, wm, USHRT_MAX);
1657 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1659 return (active_planes & (BIT(PLANE_SPRITE0) |
1660 BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1663 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1665 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1666 const struct g4x_pipe_wm *raw =
1667 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1668 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1669 unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1670 int num_active_planes = hweight32(active_planes);
1671 const int fifo_size = 511;
1672 int fifo_extra, fifo_left = fifo_size;
1673 int sprite0_fifo_extra = 0;
1674 unsigned int total_rate;
1675 enum plane_id plane_id;
1678 * When enabling sprite0 after sprite1 has already been enabled
1679 * we tend to get an underrun unless sprite0 already has some
1680 * FIFO space allcoated. Hence we always allocate at least one
1681 * cacheline for sprite0 whenever sprite1 is enabled.
1683 * All other plane enable sequences appear immune to this problem.
1685 if (vlv_need_sprite0_fifo_workaround(active_planes))
1686 sprite0_fifo_extra = 1;
1688 total_rate = raw->plane[PLANE_PRIMARY] +
1689 raw->plane[PLANE_SPRITE0] +
1690 raw->plane[PLANE_SPRITE1] +
1693 if (total_rate > fifo_size)
1696 if (total_rate == 0)
1699 for_each_plane_id_on_crtc(crtc, plane_id) {
1702 if ((active_planes & BIT(plane_id)) == 0) {
1703 fifo_state->plane[plane_id] = 0;
1707 rate = raw->plane[plane_id];
1708 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1709 fifo_left -= fifo_state->plane[plane_id];
1712 fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1713 fifo_left -= sprite0_fifo_extra;
1715 fifo_state->plane[PLANE_CURSOR] = 63;
1717 fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1719 /* spread the remainder evenly */
1720 for_each_plane_id_on_crtc(crtc, plane_id) {
1726 if ((active_planes & BIT(plane_id)) == 0)
1729 plane_extra = min(fifo_extra, fifo_left);
1730 fifo_state->plane[plane_id] += plane_extra;
1731 fifo_left -= plane_extra;
1734 WARN_ON(active_planes != 0 && fifo_left != 0);
1736 /* give it all to the first plane if none are active */
1737 if (active_planes == 0) {
1738 WARN_ON(fifo_left != fifo_size);
1739 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1745 /* mark all levels starting from 'level' as invalid */
1746 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1747 struct vlv_wm_state *wm_state, int level)
1749 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1751 for (; level < intel_wm_num_levels(dev_priv); level++) {
1752 enum plane_id plane_id;
1754 for_each_plane_id_on_crtc(crtc, plane_id)
1755 wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1757 wm_state->sr[level].cursor = USHRT_MAX;
1758 wm_state->sr[level].plane = USHRT_MAX;
1762 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1767 return fifo_size - wm;
1771 * Starting from 'level' set all higher
1772 * levels to 'value' in the "raw" watermarks.
1774 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1775 int level, enum plane_id plane_id, u16 value)
1777 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1778 int num_levels = intel_wm_num_levels(dev_priv);
1781 for (; level < num_levels; level++) {
1782 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1784 dirty |= raw->plane[plane_id] != value;
1785 raw->plane[plane_id] = value;
1791 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1792 const struct intel_plane_state *plane_state)
1794 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1795 enum plane_id plane_id = plane->id;
1796 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1800 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1801 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1805 for (level = 0; level < num_levels; level++) {
1806 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1807 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1808 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1813 dirty |= raw->plane[plane_id] != wm;
1814 raw->plane[plane_id] = wm;
1817 /* mark all higher levels as invalid */
1818 dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1822 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1824 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1825 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1826 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1831 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1832 enum plane_id plane_id, int level)
1834 const struct g4x_pipe_wm *raw =
1835 &crtc_state->wm.vlv.raw[level];
1836 const struct vlv_fifo_state *fifo_state =
1837 &crtc_state->wm.vlv.fifo_state;
1839 return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1842 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1844 return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1845 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1846 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1847 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1850 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1854 struct intel_atomic_state *state =
1855 to_intel_atomic_state(crtc_state->base.state);
1856 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1857 const struct vlv_fifo_state *fifo_state =
1858 &crtc_state->wm.vlv.fifo_state;
1859 int num_active_planes = hweight32(crtc_state->active_planes &
1860 ~BIT(PLANE_CURSOR));
1861 bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1862 const struct intel_plane_state *old_plane_state;
1863 const struct intel_plane_state *new_plane_state;
1864 struct intel_plane *plane;
1865 enum plane_id plane_id;
1867 unsigned int dirty = 0;
1869 for_each_oldnew_intel_plane_in_state(state, plane,
1871 new_plane_state, i) {
1872 if (new_plane_state->base.crtc != &crtc->base &&
1873 old_plane_state->base.crtc != &crtc->base)
1876 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1877 dirty |= BIT(plane->id);
1881 * DSPARB registers may have been reset due to the
1882 * power well being turned off. Make sure we restore
1883 * them to a consistent state even if no primary/sprite
1884 * planes are initially active.
1887 crtc_state->fifo_changed = true;
1892 /* cursor changes don't warrant a FIFO recompute */
1893 if (dirty & ~BIT(PLANE_CURSOR)) {
1894 const struct intel_crtc_state *old_crtc_state =
1895 intel_atomic_get_old_crtc_state(state, crtc);
1896 const struct vlv_fifo_state *old_fifo_state =
1897 &old_crtc_state->wm.vlv.fifo_state;
1899 ret = vlv_compute_fifo(crtc_state);
1903 if (needs_modeset ||
1904 memcmp(old_fifo_state, fifo_state,
1905 sizeof(*fifo_state)) != 0)
1906 crtc_state->fifo_changed = true;
1909 /* initially allow all levels */
1910 wm_state->num_levels = intel_wm_num_levels(dev_priv);
1912 * Note that enabling cxsr with no primary/sprite planes
1913 * enabled can wedge the pipe. Hence we only allow cxsr
1914 * with exactly one enabled primary/sprite plane.
1916 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1918 for (level = 0; level < wm_state->num_levels; level++) {
1919 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1920 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1922 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1925 for_each_plane_id_on_crtc(crtc, plane_id) {
1926 wm_state->wm[level].plane[plane_id] =
1927 vlv_invert_wm_value(raw->plane[plane_id],
1928 fifo_state->plane[plane_id]);
1931 wm_state->sr[level].plane =
1932 vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1933 raw->plane[PLANE_SPRITE0],
1934 raw->plane[PLANE_SPRITE1]),
1937 wm_state->sr[level].cursor =
1938 vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1945 /* limit to only levels we can actually handle */
1946 wm_state->num_levels = level;
1948 /* invalidate the higher levels */
1949 vlv_invalidate_wms(crtc, wm_state, level);
1954 #define VLV_FIFO(plane, value) \
1955 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1957 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1958 struct intel_crtc_state *crtc_state)
1960 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1961 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1962 struct intel_uncore *uncore = &dev_priv->uncore;
1963 const struct vlv_fifo_state *fifo_state =
1964 &crtc_state->wm.vlv.fifo_state;
1965 int sprite0_start, sprite1_start, fifo_size;
1967 if (!crtc_state->fifo_changed)
1970 sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1971 sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1972 fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1974 WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1975 WARN_ON(fifo_size != 511);
1977 trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1980 * uncore.lock serves a double purpose here. It allows us to
1981 * use the less expensive I915_{READ,WRITE}_FW() functions, and
1982 * it protects the DSPARB registers from getting clobbered by
1983 * parallel updates from multiple pipes.
1985 * intel_pipe_update_start() has already disabled interrupts
1986 * for us, so a plain spin_lock() is sufficient here.
1988 spin_lock(&uncore->lock);
1990 switch (crtc->pipe) {
1991 u32 dsparb, dsparb2, dsparb3;
1993 dsparb = intel_uncore_read_fw(uncore, DSPARB);
1994 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
1996 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1997 VLV_FIFO(SPRITEB, 0xff));
1998 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1999 VLV_FIFO(SPRITEB, sprite1_start));
2001 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
2002 VLV_FIFO(SPRITEB_HI, 0x1));
2003 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
2004 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
2006 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2007 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2010 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2011 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2013 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
2014 VLV_FIFO(SPRITED, 0xff));
2015 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
2016 VLV_FIFO(SPRITED, sprite1_start));
2018 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
2019 VLV_FIFO(SPRITED_HI, 0xff));
2020 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
2021 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
2023 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2024 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2027 dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
2028 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2030 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2031 VLV_FIFO(SPRITEF, 0xff));
2032 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2033 VLV_FIFO(SPRITEF, sprite1_start));
2035 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2036 VLV_FIFO(SPRITEF_HI, 0xff));
2037 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2038 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2040 intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
2041 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2047 intel_uncore_posting_read_fw(uncore, DSPARB);
2049 spin_unlock(&uncore->lock);
2054 static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
2056 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
2057 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
2058 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
2059 struct intel_atomic_state *intel_state =
2060 to_intel_atomic_state(new_crtc_state->base.state);
2061 const struct intel_crtc_state *old_crtc_state =
2062 intel_atomic_get_old_crtc_state(intel_state, crtc);
2063 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
2066 if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
2067 *intermediate = *optimal;
2069 intermediate->cxsr = false;
2073 intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2074 intermediate->cxsr = optimal->cxsr && active->cxsr &&
2075 !new_crtc_state->disable_cxsr;
2077 for (level = 0; level < intermediate->num_levels; level++) {
2078 enum plane_id plane_id;
2080 for_each_plane_id_on_crtc(crtc, plane_id) {
2081 intermediate->wm[level].plane[plane_id] =
2082 min(optimal->wm[level].plane[plane_id],
2083 active->wm[level].plane[plane_id]);
2086 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2087 active->sr[level].plane);
2088 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2089 active->sr[level].cursor);
2092 vlv_invalidate_wms(crtc, intermediate, level);
2096 * If our intermediate WM are identical to the final WM, then we can
2097 * omit the post-vblank programming; only update if it's different.
2099 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2100 new_crtc_state->wm.need_postvbl_update = true;
2105 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2106 struct vlv_wm_values *wm)
2108 struct intel_crtc *crtc;
2109 int num_active_crtcs = 0;
2111 wm->level = dev_priv->wm.max_level;
2114 for_each_intel_crtc(&dev_priv->drm, crtc) {
2115 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2120 if (!wm_state->cxsr)
2124 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2127 if (num_active_crtcs != 1)
2130 if (num_active_crtcs > 1)
2131 wm->level = VLV_WM_LEVEL_PM2;
2133 for_each_intel_crtc(&dev_priv->drm, crtc) {
2134 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2135 enum pipe pipe = crtc->pipe;
2137 wm->pipe[pipe] = wm_state->wm[wm->level];
2138 if (crtc->active && wm->cxsr)
2139 wm->sr = wm_state->sr[wm->level];
2141 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2142 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2143 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2144 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2148 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2150 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2151 struct vlv_wm_values new_wm = {};
2153 vlv_merge_wm(dev_priv, &new_wm);
2155 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2158 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2159 chv_set_memory_dvfs(dev_priv, false);
2161 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2162 chv_set_memory_pm5(dev_priv, false);
2164 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2165 _intel_set_memory_cxsr(dev_priv, false);
2167 vlv_write_wm_values(dev_priv, &new_wm);
2169 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2170 _intel_set_memory_cxsr(dev_priv, true);
2172 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2173 chv_set_memory_pm5(dev_priv, true);
2175 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2176 chv_set_memory_dvfs(dev_priv, true);
2181 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2182 struct intel_crtc_state *crtc_state)
2184 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2185 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2187 mutex_lock(&dev_priv->wm.wm_mutex);
2188 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2189 vlv_program_watermarks(dev_priv);
2190 mutex_unlock(&dev_priv->wm.wm_mutex);
2193 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2194 struct intel_crtc_state *crtc_state)
2196 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2197 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2199 if (!crtc_state->wm.need_postvbl_update)
2202 mutex_lock(&dev_priv->wm.wm_mutex);
2203 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2204 vlv_program_watermarks(dev_priv);
2205 mutex_unlock(&dev_priv->wm.wm_mutex);
2208 static void i965_update_wm(struct intel_crtc *unused_crtc)
2210 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2211 struct intel_crtc *crtc;
2216 /* Calc sr entries for one plane configs */
2217 crtc = single_enabled_crtc(dev_priv);
2219 /* self-refresh has much higher latency */
2220 static const int sr_latency_ns = 12000;
2221 const struct drm_display_mode *adjusted_mode =
2222 &crtc->config->base.adjusted_mode;
2223 const struct drm_framebuffer *fb =
2224 crtc->base.primary->state->fb;
2225 int clock = adjusted_mode->crtc_clock;
2226 int htotal = adjusted_mode->crtc_htotal;
2227 int hdisplay = crtc->config->pipe_src_w;
2228 int cpp = fb->format->cpp[0];
2231 entries = intel_wm_method2(clock, htotal,
2232 hdisplay, cpp, sr_latency_ns / 100);
2233 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2234 srwm = I965_FIFO_SIZE - entries;
2238 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2241 entries = intel_wm_method2(clock, htotal,
2242 crtc->base.cursor->state->crtc_w, 4,
2243 sr_latency_ns / 100);
2244 entries = DIV_ROUND_UP(entries,
2245 i965_cursor_wm_info.cacheline_size) +
2246 i965_cursor_wm_info.guard_size;
2248 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2249 if (cursor_sr > i965_cursor_wm_info.max_wm)
2250 cursor_sr = i965_cursor_wm_info.max_wm;
2252 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2253 "cursor %d\n", srwm, cursor_sr);
2255 cxsr_enabled = true;
2257 cxsr_enabled = false;
2258 /* Turn off self refresh if both pipes are enabled */
2259 intel_set_memory_cxsr(dev_priv, false);
2262 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2265 /* 965 has limitations... */
2266 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2270 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2271 FW_WM(8, PLANEC_OLD));
2272 /* update cursor SR watermark */
2273 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2276 intel_set_memory_cxsr(dev_priv, true);
2281 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2283 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2284 const struct intel_watermark_params *wm_info;
2289 int planea_wm, planeb_wm;
2290 struct intel_crtc *crtc, *enabled = NULL;
2292 if (IS_I945GM(dev_priv))
2293 wm_info = &i945_wm_info;
2294 else if (!IS_GEN(dev_priv, 2))
2295 wm_info = &i915_wm_info;
2297 wm_info = &i830_a_wm_info;
2299 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
2300 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
2301 if (intel_crtc_active(crtc)) {
2302 const struct drm_display_mode *adjusted_mode =
2303 &crtc->config->base.adjusted_mode;
2304 const struct drm_framebuffer *fb =
2305 crtc->base.primary->state->fb;
2308 if (IS_GEN(dev_priv, 2))
2311 cpp = fb->format->cpp[0];
2313 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2314 wm_info, fifo_size, cpp,
2315 pessimal_latency_ns);
2318 planea_wm = fifo_size - wm_info->guard_size;
2319 if (planea_wm > (long)wm_info->max_wm)
2320 planea_wm = wm_info->max_wm;
2323 if (IS_GEN(dev_priv, 2))
2324 wm_info = &i830_bc_wm_info;
2326 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
2327 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
2328 if (intel_crtc_active(crtc)) {
2329 const struct drm_display_mode *adjusted_mode =
2330 &crtc->config->base.adjusted_mode;
2331 const struct drm_framebuffer *fb =
2332 crtc->base.primary->state->fb;
2335 if (IS_GEN(dev_priv, 2))
2338 cpp = fb->format->cpp[0];
2340 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2341 wm_info, fifo_size, cpp,
2342 pessimal_latency_ns);
2343 if (enabled == NULL)
2348 planeb_wm = fifo_size - wm_info->guard_size;
2349 if (planeb_wm > (long)wm_info->max_wm)
2350 planeb_wm = wm_info->max_wm;
2353 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2355 if (IS_I915GM(dev_priv) && enabled) {
2356 struct drm_i915_gem_object *obj;
2358 obj = intel_fb_obj(enabled->base.primary->state->fb);
2360 /* self-refresh seems busted with untiled */
2361 if (!i915_gem_object_is_tiled(obj))
2366 * Overlay gets an aggressive default since video jitter is bad.
2370 /* Play safe and disable self-refresh before adjusting watermarks. */
2371 intel_set_memory_cxsr(dev_priv, false);
2373 /* Calc sr entries for one plane configs */
2374 if (HAS_FW_BLC(dev_priv) && enabled) {
2375 /* self-refresh has much higher latency */
2376 static const int sr_latency_ns = 6000;
2377 const struct drm_display_mode *adjusted_mode =
2378 &enabled->config->base.adjusted_mode;
2379 const struct drm_framebuffer *fb =
2380 enabled->base.primary->state->fb;
2381 int clock = adjusted_mode->crtc_clock;
2382 int htotal = adjusted_mode->crtc_htotal;
2383 int hdisplay = enabled->config->pipe_src_w;
2387 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2390 cpp = fb->format->cpp[0];
2392 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2393 sr_latency_ns / 100);
2394 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2395 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
2396 srwm = wm_info->fifo_size - entries;
2400 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2401 I915_WRITE(FW_BLC_SELF,
2402 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2404 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2407 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2408 planea_wm, planeb_wm, cwm, srwm);
2410 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2411 fwater_hi = (cwm & 0x1f);
2413 /* Set request length to 8 cachelines per fetch */
2414 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2415 fwater_hi = fwater_hi | (1 << 8);
2417 I915_WRITE(FW_BLC, fwater_lo);
2418 I915_WRITE(FW_BLC2, fwater_hi);
2421 intel_set_memory_cxsr(dev_priv, true);
2424 static void i845_update_wm(struct intel_crtc *unused_crtc)
2426 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2427 struct intel_crtc *crtc;
2428 const struct drm_display_mode *adjusted_mode;
2432 crtc = single_enabled_crtc(dev_priv);
2436 adjusted_mode = &crtc->config->base.adjusted_mode;
2437 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2439 dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
2440 4, pessimal_latency_ns);
2441 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2442 fwater_lo |= (3<<8) | planea_wm;
2444 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2446 I915_WRITE(FW_BLC, fwater_lo);
2449 /* latency must be in 0.1us units. */
2450 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2452 unsigned int latency)
2456 ret = intel_wm_method1(pixel_rate, cpp, latency);
2457 ret = DIV_ROUND_UP(ret, 64) + 2;
2462 /* latency must be in 0.1us units. */
2463 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2464 unsigned int htotal,
2467 unsigned int latency)
2471 ret = intel_wm_method2(pixel_rate, htotal,
2472 width, cpp, latency);
2473 ret = DIV_ROUND_UP(ret, 64) + 2;
2478 static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
2481 * Neither of these should be possible since this function shouldn't be
2482 * called if the CRTC is off or the plane is invisible. But let's be
2483 * extra paranoid to avoid a potential divide-by-zero if we screw up
2484 * elsewhere in the driver.
2488 if (WARN_ON(!horiz_pixels))
2491 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2494 struct ilk_wm_maximums {
2502 * For both WM_PIPE and WM_LP.
2503 * mem_value must be in 0.1us units.
2505 static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
2506 const struct intel_plane_state *plane_state,
2507 u32 mem_value, bool is_lp)
2509 u32 method1, method2;
2515 if (!intel_wm_plane_visible(crtc_state, plane_state))
2518 cpp = plane_state->base.fb->format->cpp[0];
2520 method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2525 method2 = ilk_wm_method2(crtc_state->pixel_rate,
2526 crtc_state->base.adjusted_mode.crtc_htotal,
2527 drm_rect_width(&plane_state->base.dst),
2530 return min(method1, method2);
2534 * For both WM_PIPE and WM_LP.
2535 * mem_value must be in 0.1us units.
2537 static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
2538 const struct intel_plane_state *plane_state,
2541 u32 method1, method2;
2547 if (!intel_wm_plane_visible(crtc_state, plane_state))
2550 cpp = plane_state->base.fb->format->cpp[0];
2552 method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2553 method2 = ilk_wm_method2(crtc_state->pixel_rate,
2554 crtc_state->base.adjusted_mode.crtc_htotal,
2555 drm_rect_width(&plane_state->base.dst),
2557 return min(method1, method2);
2561 * For both WM_PIPE and WM_LP.
2562 * mem_value must be in 0.1us units.
2564 static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
2565 const struct intel_plane_state *plane_state,
2573 if (!intel_wm_plane_visible(crtc_state, plane_state))
2576 cpp = plane_state->base.fb->format->cpp[0];
2578 return ilk_wm_method2(crtc_state->pixel_rate,
2579 crtc_state->base.adjusted_mode.crtc_htotal,
2580 plane_state->base.crtc_w, cpp, mem_value);
2583 /* Only for WM_LP. */
2584 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
2585 const struct intel_plane_state *plane_state,
2590 if (!intel_wm_plane_visible(crtc_state, plane_state))
2593 cpp = plane_state->base.fb->format->cpp[0];
2595 return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
2599 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2601 if (INTEL_GEN(dev_priv) >= 8)
2603 else if (INTEL_GEN(dev_priv) >= 7)
2610 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2611 int level, bool is_sprite)
2613 if (INTEL_GEN(dev_priv) >= 8)
2614 /* BDW primary/sprite plane watermarks */
2615 return level == 0 ? 255 : 2047;
2616 else if (INTEL_GEN(dev_priv) >= 7)
2617 /* IVB/HSW primary/sprite plane watermarks */
2618 return level == 0 ? 127 : 1023;
2619 else if (!is_sprite)
2620 /* ILK/SNB primary plane watermarks */
2621 return level == 0 ? 127 : 511;
2623 /* ILK/SNB sprite plane watermarks */
2624 return level == 0 ? 63 : 255;
2628 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2630 if (INTEL_GEN(dev_priv) >= 7)
2631 return level == 0 ? 63 : 255;
2633 return level == 0 ? 31 : 63;
2636 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2638 if (INTEL_GEN(dev_priv) >= 8)
2644 /* Calculate the maximum primary/sprite plane watermark */
2645 static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
2647 const struct intel_wm_config *config,
2648 enum intel_ddb_partitioning ddb_partitioning,
2651 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2653 /* if sprites aren't enabled, sprites get nothing */
2654 if (is_sprite && !config->sprites_enabled)
2657 /* HSW allows LP1+ watermarks even with multiple pipes */
2658 if (level == 0 || config->num_pipes_active > 1) {
2659 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
2662 * For some reason the non self refresh
2663 * FIFO size is only half of the self
2664 * refresh FIFO size on ILK/SNB.
2666 if (INTEL_GEN(dev_priv) <= 6)
2670 if (config->sprites_enabled) {
2671 /* level 0 is always calculated with 1:1 split */
2672 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2681 /* clamp to max that the registers can hold */
2682 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2685 /* Calculate the maximum cursor plane watermark */
2686 static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
2688 const struct intel_wm_config *config)
2690 /* HSW LP1+ watermarks w/ multiple pipes */
2691 if (level > 0 && config->num_pipes_active > 1)
2694 /* otherwise just report max that registers can hold */
2695 return ilk_cursor_wm_reg_max(dev_priv, level);
2698 static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
2700 const struct intel_wm_config *config,
2701 enum intel_ddb_partitioning ddb_partitioning,
2702 struct ilk_wm_maximums *max)
2704 max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
2705 max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true);
2706 max->cur = ilk_cursor_wm_max(dev_priv, level, config);
2707 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2710 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2712 struct ilk_wm_maximums *max)
2714 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2715 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2716 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2717 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2720 static bool ilk_validate_wm_level(int level,
2721 const struct ilk_wm_maximums *max,
2722 struct intel_wm_level *result)
2726 /* already determined to be invalid? */
2727 if (!result->enable)
2730 result->enable = result->pri_val <= max->pri &&
2731 result->spr_val <= max->spr &&
2732 result->cur_val <= max->cur;
2734 ret = result->enable;
2737 * HACK until we can pre-compute everything,
2738 * and thus fail gracefully if LP0 watermarks
2741 if (level == 0 && !result->enable) {
2742 if (result->pri_val > max->pri)
2743 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2744 level, result->pri_val, max->pri);
2745 if (result->spr_val > max->spr)
2746 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2747 level, result->spr_val, max->spr);
2748 if (result->cur_val > max->cur)
2749 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2750 level, result->cur_val, max->cur);
2752 result->pri_val = min_t(u32, result->pri_val, max->pri);
2753 result->spr_val = min_t(u32, result->spr_val, max->spr);
2754 result->cur_val = min_t(u32, result->cur_val, max->cur);
2755 result->enable = true;
2761 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2762 const struct intel_crtc *intel_crtc,
2764 struct intel_crtc_state *crtc_state,
2765 const struct intel_plane_state *pristate,
2766 const struct intel_plane_state *sprstate,
2767 const struct intel_plane_state *curstate,
2768 struct intel_wm_level *result)
2770 u16 pri_latency = dev_priv->wm.pri_latency[level];
2771 u16 spr_latency = dev_priv->wm.spr_latency[level];
2772 u16 cur_latency = dev_priv->wm.cur_latency[level];
2774 /* WM1+ latency values stored in 0.5us units */
2782 result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
2783 pri_latency, level);
2784 result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
2788 result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
2791 result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
2793 result->enable = true;
2797 hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
2799 const struct intel_atomic_state *intel_state =
2800 to_intel_atomic_state(crtc_state->base.state);
2801 const struct drm_display_mode *adjusted_mode =
2802 &crtc_state->base.adjusted_mode;
2803 u32 linetime, ips_linetime;
2805 if (!crtc_state->base.active)
2807 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2809 if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2812 /* The WM are computed with base on how long it takes to fill a single
2813 * row at the given clock rate, multiplied by 8.
2815 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2816 adjusted_mode->crtc_clock);
2817 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2818 intel_state->cdclk.logical.cdclk);
2820 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2821 PIPE_WM_LINETIME_TIME(linetime);
2824 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2827 struct intel_uncore *uncore = &dev_priv->uncore;
2829 if (INTEL_GEN(dev_priv) >= 9) {
2832 int level, max_level = ilk_wm_max_level(dev_priv);
2834 /* read the first set of memory latencies[0:3] */
2835 val = 0; /* data0 to be programmed to 0 for first set */
2836 ret = sandybridge_pcode_read(dev_priv,
2837 GEN9_PCODE_READ_MEM_LATENCY,
2841 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2845 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2846 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2847 GEN9_MEM_LATENCY_LEVEL_MASK;
2848 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2849 GEN9_MEM_LATENCY_LEVEL_MASK;
2850 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2851 GEN9_MEM_LATENCY_LEVEL_MASK;
2853 /* read the second set of memory latencies[4:7] */
2854 val = 1; /* data0 to be programmed to 1 for second set */
2855 ret = sandybridge_pcode_read(dev_priv,
2856 GEN9_PCODE_READ_MEM_LATENCY,
2859 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2863 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2864 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2865 GEN9_MEM_LATENCY_LEVEL_MASK;
2866 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2867 GEN9_MEM_LATENCY_LEVEL_MASK;
2868 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2869 GEN9_MEM_LATENCY_LEVEL_MASK;
2872 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2873 * need to be disabled. We make sure to sanitize the values out
2874 * of the punit to satisfy this requirement.
2876 for (level = 1; level <= max_level; level++) {
2877 if (wm[level] == 0) {
2878 for (i = level + 1; i <= max_level; i++)
2885 * WaWmMemoryReadLatency:skl+,glk
2887 * punit doesn't take into account the read latency so we need
2888 * to add 2us to the various latency levels we retrieve from the
2889 * punit when level 0 response data us 0us.
2893 for (level = 1; level <= max_level; level++) {
2901 * WA Level-0 adjustment for 16GB DIMMs: SKL+
2902 * If we could not get dimm info enable this WA to prevent from
2903 * any underrun. If not able to get Dimm info assume 16GB dimm
2904 * to avoid any underrun.
2906 if (dev_priv->dram_info.is_16gb_dimm)
2909 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2910 u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
2912 wm[0] = (sskpd >> 56) & 0xFF;
2914 wm[0] = sskpd & 0xF;
2915 wm[1] = (sskpd >> 4) & 0xFF;
2916 wm[2] = (sskpd >> 12) & 0xFF;
2917 wm[3] = (sskpd >> 20) & 0x1FF;
2918 wm[4] = (sskpd >> 32) & 0x1FF;
2919 } else if (INTEL_GEN(dev_priv) >= 6) {
2920 u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
2922 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2923 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2924 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2925 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2926 } else if (INTEL_GEN(dev_priv) >= 5) {
2927 u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
2929 /* ILK primary LP0 latency is 700 ns */
2931 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2932 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2934 MISSING_CASE(INTEL_DEVID(dev_priv));
2938 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2941 /* ILK sprite LP0 latency is 1300 ns */
2942 if (IS_GEN(dev_priv, 5))
2946 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2949 /* ILK cursor LP0 latency is 1300 ns */
2950 if (IS_GEN(dev_priv, 5))
2954 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2956 /* how many WM levels are we expecting */
2957 if (INTEL_GEN(dev_priv) >= 9)
2959 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2961 else if (INTEL_GEN(dev_priv) >= 6)
2967 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2971 int level, max_level = ilk_wm_max_level(dev_priv);
2973 for (level = 0; level <= max_level; level++) {
2974 unsigned int latency = wm[level];
2977 DRM_DEBUG_KMS("%s WM%d latency not provided\n",
2983 * - latencies are in us on gen9.
2984 * - before then, WM1+ latency values are in 0.5us units
2986 if (INTEL_GEN(dev_priv) >= 9)
2991 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2992 name, level, wm[level],
2993 latency / 10, latency % 10);
2997 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
3000 int level, max_level = ilk_wm_max_level(dev_priv);
3005 wm[0] = max(wm[0], min);
3006 for (level = 1; level <= max_level; level++)
3007 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
3012 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
3017 * The BIOS provided WM memory latency values are often
3018 * inadequate for high resolution displays. Adjust them.
3020 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
3021 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
3022 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
3027 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
3028 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3029 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3030 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3033 static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
3036 * On some SNB machines (Thinkpad X220 Tablet at least)
3037 * LP3 usage can cause vblank interrupts to be lost.
3038 * The DEIIR bit will go high but it looks like the CPU
3039 * never gets interrupted.
3041 * It's not clear whether other interrupt source could
3042 * be affected or if this is somehow limited to vblank
3043 * interrupts only. To play it safe we disable LP3
3044 * watermarks entirely.
3046 if (dev_priv->wm.pri_latency[3] == 0 &&
3047 dev_priv->wm.spr_latency[3] == 0 &&
3048 dev_priv->wm.cur_latency[3] == 0)
3051 dev_priv->wm.pri_latency[3] = 0;
3052 dev_priv->wm.spr_latency[3] = 0;
3053 dev_priv->wm.cur_latency[3] = 0;
3055 DRM_DEBUG_KMS("LP3 watermarks disabled due to potential for lost interrupts\n");
3056 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3057 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3058 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3061 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3063 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
3065 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
3066 sizeof(dev_priv->wm.pri_latency));
3067 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
3068 sizeof(dev_priv->wm.pri_latency));
3070 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
3071 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3073 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3074 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3075 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3077 if (IS_GEN(dev_priv, 6)) {
3078 snb_wm_latency_quirk(dev_priv);
3079 snb_wm_lp3_irq_quirk(dev_priv);
3083 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3085 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3086 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3089 static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
3090 struct intel_pipe_wm *pipe_wm)
3092 /* LP0 watermark maximums depend on this pipe alone */
3093 const struct intel_wm_config config = {
3094 .num_pipes_active = 1,
3095 .sprites_enabled = pipe_wm->sprites_enabled,
3096 .sprites_scaled = pipe_wm->sprites_scaled,
3098 struct ilk_wm_maximums max;
3100 /* LP0 watermarks always use 1/2 DDB partitioning */
3101 ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
3103 /* At least LP0 must be valid */
3104 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3105 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3112 /* Compute new watermarks for the pipe */
3113 static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
3115 struct drm_atomic_state *state = crtc_state->base.state;
3116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3117 struct intel_pipe_wm *pipe_wm;
3118 struct drm_device *dev = state->dev;
3119 const struct drm_i915_private *dev_priv = to_i915(dev);
3120 struct drm_plane *plane;
3121 const struct drm_plane_state *plane_state;
3122 const struct intel_plane_state *pristate = NULL;
3123 const struct intel_plane_state *sprstate = NULL;
3124 const struct intel_plane_state *curstate = NULL;
3125 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3126 struct ilk_wm_maximums max;
3128 pipe_wm = &crtc_state->wm.ilk.optimal;
3130 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) {
3131 const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
3133 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3135 else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
3137 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
3141 pipe_wm->pipe_enabled = crtc_state->base.active;
3143 pipe_wm->sprites_enabled = sprstate->base.visible;
3144 pipe_wm->sprites_scaled = sprstate->base.visible &&
3145 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
3146 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
3149 usable_level = max_level;
3151 /* ILK/SNB: LP2+ watermarks only w/o sprites */
3152 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3155 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3156 if (pipe_wm->sprites_scaled)
3159 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3160 ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
3161 pristate, sprstate, curstate, &pipe_wm->wm[0]);
3163 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3164 pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state);
3166 if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
3169 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3171 for (level = 1; level <= usable_level; level++) {
3172 struct intel_wm_level *wm = &pipe_wm->wm[level];
3174 ilk_compute_wm_level(dev_priv, intel_crtc, level, crtc_state,
3175 pristate, sprstate, curstate, wm);
3178 * Disable any watermark level that exceeds the
3179 * register maximums since such watermarks are
3182 if (!ilk_validate_wm_level(level, &max, wm)) {
3183 memset(wm, 0, sizeof(*wm));
3192 * Build a set of 'intermediate' watermark values that satisfy both the old
3193 * state and the new state. These can be programmed to the hardware
3196 static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
3198 struct intel_crtc *intel_crtc = to_intel_crtc(newstate->base.crtc);
3199 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3200 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3201 struct intel_atomic_state *intel_state =
3202 to_intel_atomic_state(newstate->base.state);
3203 const struct intel_crtc_state *oldstate =
3204 intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
3205 const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
3206 int level, max_level = ilk_wm_max_level(dev_priv);
3209 * Start with the final, target watermarks, then combine with the
3210 * currently active watermarks to get values that are safe both before
3211 * and after the vblank.
3213 *a = newstate->wm.ilk.optimal;
3214 if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
3215 intel_state->skip_intermediate_wm)
3218 a->pipe_enabled |= b->pipe_enabled;
3219 a->sprites_enabled |= b->sprites_enabled;
3220 a->sprites_scaled |= b->sprites_scaled;
3222 for (level = 0; level <= max_level; level++) {
3223 struct intel_wm_level *a_wm = &a->wm[level];
3224 const struct intel_wm_level *b_wm = &b->wm[level];
3226 a_wm->enable &= b_wm->enable;
3227 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3228 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3229 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3230 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3234 * We need to make sure that these merged watermark values are
3235 * actually a valid configuration themselves. If they're not,
3236 * there's no safe way to transition from the old state to
3237 * the new state, so we need to fail the atomic transaction.
3239 if (!ilk_validate_pipe_wm(dev_priv, a))
3243 * If our intermediate WM are identical to the final WM, then we can
3244 * omit the post-vblank programming; only update if it's different.
3246 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3247 newstate->wm.need_postvbl_update = true;
3253 * Merge the watermarks from all active pipes for a specific level.
3255 static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
3257 struct intel_wm_level *ret_wm)
3259 const struct intel_crtc *intel_crtc;
3261 ret_wm->enable = true;
3263 for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3264 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3265 const struct intel_wm_level *wm = &active->wm[level];
3267 if (!active->pipe_enabled)
3271 * The watermark values may have been used in the past,
3272 * so we must maintain them in the registers for some
3273 * time even if the level is now disabled.
3276 ret_wm->enable = false;
3278 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3279 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3280 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3281 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3286 * Merge all low power watermarks for all active pipes.
3288 static void ilk_wm_merge(struct drm_i915_private *dev_priv,
3289 const struct intel_wm_config *config,
3290 const struct ilk_wm_maximums *max,
3291 struct intel_pipe_wm *merged)
3293 int level, max_level = ilk_wm_max_level(dev_priv);
3294 int last_enabled_level = max_level;
3296 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3297 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3298 config->num_pipes_active > 1)
3299 last_enabled_level = 0;
3301 /* ILK: FBC WM must be disabled always */
3302 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3304 /* merge each WM1+ level */
3305 for (level = 1; level <= max_level; level++) {
3306 struct intel_wm_level *wm = &merged->wm[level];
3308 ilk_merge_wm_level(dev_priv, level, wm);
3310 if (level > last_enabled_level)
3312 else if (!ilk_validate_wm_level(level, max, wm))
3313 /* make sure all following levels get disabled */
3314 last_enabled_level = level - 1;
3317 * The spec says it is preferred to disable
3318 * FBC WMs instead of disabling a WM level.
3320 if (wm->fbc_val > max->fbc) {
3322 merged->fbc_wm_enabled = false;
3327 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3329 * FIXME this is racy. FBC might get enabled later.
3330 * What we should check here is whether FBC can be
3331 * enabled sometime later.
3333 if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
3334 intel_fbc_is_active(dev_priv)) {
3335 for (level = 2; level <= max_level; level++) {
3336 struct intel_wm_level *wm = &merged->wm[level];
3343 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3345 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3346 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3349 /* The value we need to program into the WM_LPx latency field */
3350 static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
3353 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3356 return dev_priv->wm.pri_latency[level];
3359 static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
3360 const struct intel_pipe_wm *merged,
3361 enum intel_ddb_partitioning partitioning,
3362 struct ilk_wm_values *results)
3364 struct intel_crtc *intel_crtc;
3367 results->enable_fbc_wm = merged->fbc_wm_enabled;
3368 results->partitioning = partitioning;
3370 /* LP1+ register values */
3371 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3372 const struct intel_wm_level *r;
3374 level = ilk_wm_lp_to_level(wm_lp, merged);
3376 r = &merged->wm[level];
3379 * Maintain the watermark values even if the level is
3380 * disabled. Doing otherwise could cause underruns.
3382 results->wm_lp[wm_lp - 1] =
3383 (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
3384 (r->pri_val << WM1_LP_SR_SHIFT) |
3388 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3390 if (INTEL_GEN(dev_priv) >= 8)
3391 results->wm_lp[wm_lp - 1] |=
3392 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3394 results->wm_lp[wm_lp - 1] |=
3395 r->fbc_val << WM1_LP_FBC_SHIFT;
3398 * Always set WM1S_LP_EN when spr_val != 0, even if the
3399 * level is disabled. Doing otherwise could cause underruns.
3401 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3402 WARN_ON(wm_lp != 1);
3403 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3405 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3408 /* LP0 register values */
3409 for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3410 enum pipe pipe = intel_crtc->pipe;
3411 const struct intel_wm_level *r =
3412 &intel_crtc->wm.active.ilk.wm[0];
3414 if (WARN_ON(!r->enable))
3417 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
3419 results->wm_pipe[pipe] =
3420 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3421 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3426 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3427 * case both are at the same level. Prefer r1 in case they're the same. */
3428 static struct intel_pipe_wm *
3429 ilk_find_best_result(struct drm_i915_private *dev_priv,
3430 struct intel_pipe_wm *r1,
3431 struct intel_pipe_wm *r2)
3433 int level, max_level = ilk_wm_max_level(dev_priv);
3434 int level1 = 0, level2 = 0;
3436 for (level = 1; level <= max_level; level++) {
3437 if (r1->wm[level].enable)
3439 if (r2->wm[level].enable)
3443 if (level1 == level2) {
3444 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3448 } else if (level1 > level2) {
3455 /* dirty bits used to track which watermarks need changes */
3456 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3457 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3458 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3459 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3460 #define WM_DIRTY_FBC (1 << 24)
3461 #define WM_DIRTY_DDB (1 << 25)
3463 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3464 const struct ilk_wm_values *old,
3465 const struct ilk_wm_values *new)
3467 unsigned int dirty = 0;
3471 for_each_pipe(dev_priv, pipe) {
3472 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
3473 dirty |= WM_DIRTY_LINETIME(pipe);
3474 /* Must disable LP1+ watermarks too */
3475 dirty |= WM_DIRTY_LP_ALL;
3478 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3479 dirty |= WM_DIRTY_PIPE(pipe);
3480 /* Must disable LP1+ watermarks too */
3481 dirty |= WM_DIRTY_LP_ALL;
3485 if (old->enable_fbc_wm != new->enable_fbc_wm) {
3486 dirty |= WM_DIRTY_FBC;
3487 /* Must disable LP1+ watermarks too */
3488 dirty |= WM_DIRTY_LP_ALL;
3491 if (old->partitioning != new->partitioning) {
3492 dirty |= WM_DIRTY_DDB;
3493 /* Must disable LP1+ watermarks too */
3494 dirty |= WM_DIRTY_LP_ALL;
3497 /* LP1+ watermarks already deemed dirty, no need to continue */
3498 if (dirty & WM_DIRTY_LP_ALL)
3501 /* Find the lowest numbered LP1+ watermark in need of an update... */
3502 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3503 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3504 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3508 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3509 for (; wm_lp <= 3; wm_lp++)
3510 dirty |= WM_DIRTY_LP(wm_lp);
3515 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3518 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3519 bool changed = false;
3521 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3522 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3523 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3526 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3527 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3528 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3531 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3532 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3533 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3538 * Don't touch WM1S_LP_EN here.
3539 * Doing so could cause underruns.
3546 * The spec says we shouldn't write when we don't need, because every write
3547 * causes WMs to be re-evaluated, expending some power.
3549 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3550 struct ilk_wm_values *results)
3552 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3556 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3560 _ilk_disable_lp_wm(dev_priv, dirty);
3562 if (dirty & WM_DIRTY_PIPE(PIPE_A))
3563 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
3564 if (dirty & WM_DIRTY_PIPE(PIPE_B))
3565 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
3566 if (dirty & WM_DIRTY_PIPE(PIPE_C))
3567 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3569 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
3570 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
3571 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
3572 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
3573 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
3574 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
3576 if (dirty & WM_DIRTY_DDB) {
3577 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3578 val = I915_READ(WM_MISC);
3579 if (results->partitioning == INTEL_DDB_PART_1_2)
3580 val &= ~WM_MISC_DATA_PARTITION_5_6;
3582 val |= WM_MISC_DATA_PARTITION_5_6;
3583 I915_WRITE(WM_MISC, val);
3585 val = I915_READ(DISP_ARB_CTL2);
3586 if (results->partitioning == INTEL_DDB_PART_1_2)
3587 val &= ~DISP_DATA_PARTITION_5_6;
3589 val |= DISP_DATA_PARTITION_5_6;
3590 I915_WRITE(DISP_ARB_CTL2, val);
3594 if (dirty & WM_DIRTY_FBC) {
3595 val = I915_READ(DISP_ARB_CTL);
3596 if (results->enable_fbc_wm)
3597 val &= ~DISP_FBC_WM_DIS;
3599 val |= DISP_FBC_WM_DIS;
3600 I915_WRITE(DISP_ARB_CTL, val);
3603 if (dirty & WM_DIRTY_LP(1) &&
3604 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3605 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3607 if (INTEL_GEN(dev_priv) >= 7) {
3608 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3609 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3610 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3611 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3614 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3615 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3616 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3617 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3618 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3619 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3621 dev_priv->wm.hw = *results;
3624 bool ilk_disable_lp_wm(struct drm_device *dev)
3626 struct drm_i915_private *dev_priv = to_i915(dev);
3628 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3631 static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
3635 /* Slice 1 will always be enabled */
3638 /* Gen prior to GEN11 have only one DBuf slice */
3639 if (INTEL_GEN(dev_priv) < 11)
3640 return enabled_slices;
3643 * FIXME: for now we'll only ever use 1 slice; pretend that we have
3644 * only that 1 slice enabled until we have a proper way for on-demand
3645 * toggling of the second slice.
3647 if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
3650 return enabled_slices;
3654 * FIXME: We still don't have the proper code detect if we need to apply the WA,
3655 * so assume we'll always need it in order to avoid underruns.
3657 static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
3659 return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
3663 intel_has_sagv(struct drm_i915_private *dev_priv)
3665 return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
3666 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
3670 * SAGV dynamically adjusts the system agent voltage and clock frequencies
3671 * depending on power and performance requirements. The display engine access
3672 * to system memory is blocked during the adjustment time. Because of the
3673 * blocking time, having this enabled can cause full system hangs and/or pipe
3674 * underruns if we don't meet all of the following requirements:
3676 * - <= 1 pipe enabled
3677 * - All planes can enable watermarks for latencies >= SAGV engine block time
3678 * - We're not using an interlaced display configuration
3681 intel_enable_sagv(struct drm_i915_private *dev_priv)
3685 if (!intel_has_sagv(dev_priv))
3688 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3691 DRM_DEBUG_KMS("Enabling SAGV\n");
3692 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3695 /* We don't need to wait for SAGV when enabling */
3698 * Some skl systems, pre-release machines in particular,
3699 * don't actually have SAGV.
3701 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3702 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3703 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3705 } else if (ret < 0) {
3706 DRM_ERROR("Failed to enable SAGV\n");
3710 dev_priv->sagv_status = I915_SAGV_ENABLED;
3715 intel_disable_sagv(struct drm_i915_private *dev_priv)
3719 if (!intel_has_sagv(dev_priv))
3722 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3725 DRM_DEBUG_KMS("Disabling SAGV\n");
3726 /* bspec says to keep retrying for at least 1 ms */
3727 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3729 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3732 * Some skl systems, pre-release machines in particular,
3733 * don't actually have SAGV.
3735 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3736 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3737 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3739 } else if (ret < 0) {
3740 DRM_ERROR("Failed to disable SAGV (%d)\n", ret);
3744 dev_priv->sagv_status = I915_SAGV_DISABLED;
3748 bool intel_can_enable_sagv(struct intel_atomic_state *state)
3750 struct drm_device *dev = state->base.dev;
3751 struct drm_i915_private *dev_priv = to_i915(dev);
3752 struct intel_crtc *crtc;
3753 struct intel_plane *plane;
3754 struct intel_crtc_state *crtc_state;
3757 int sagv_block_time_us;
3759 if (!intel_has_sagv(dev_priv))
3762 if (IS_GEN(dev_priv, 9))
3763 sagv_block_time_us = 30;
3764 else if (IS_GEN(dev_priv, 10))
3765 sagv_block_time_us = 20;
3767 sagv_block_time_us = 10;
3770 * If there are no active CRTCs, no additional checks need be performed
3772 if (hweight32(state->active_crtcs) == 0)
3776 * SKL+ workaround: bspec recommends we disable SAGV when we have
3777 * more then one pipe enabled
3779 if (hweight32(state->active_crtcs) > 1)
3782 /* Since we're now guaranteed to only have one active CRTC... */
3783 pipe = ffs(state->active_crtcs) - 1;
3784 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3785 crtc_state = to_intel_crtc_state(crtc->base.state);
3787 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3790 for_each_intel_plane_on_crtc(dev, crtc, plane) {
3791 struct skl_plane_wm *wm =
3792 &crtc_state->wm.skl.optimal.planes[plane->id];
3794 /* Skip this plane if it's not enabled */
3795 if (!wm->wm[0].plane_en)
3798 /* Find the highest enabled wm level for this plane */
3799 for (level = ilk_wm_max_level(dev_priv);
3800 !wm->wm[level].plane_en; --level)
3803 latency = dev_priv->wm.skl_latency[level];
3805 if (skl_needs_memory_bw_wa(dev_priv) &&
3806 plane->base.state->fb->modifier ==
3807 I915_FORMAT_MOD_X_TILED)
3811 * If any of the planes on this pipe don't enable wm levels that
3812 * incur memory latencies higher than sagv_block_time_us we
3813 * can't enable SAGV.
3815 if (latency < sagv_block_time_us)
3822 static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
3823 const struct intel_crtc_state *crtc_state,
3824 const u64 total_data_rate,
3825 const int num_active,
3826 struct skl_ddb_allocation *ddb)
3828 const struct drm_display_mode *adjusted_mode;
3830 u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3832 WARN_ON(ddb_size == 0);
3834 if (INTEL_GEN(dev_priv) < 11)
3835 return ddb_size - 4; /* 4 blocks for bypass path allocation */
3837 adjusted_mode = &crtc_state->base.adjusted_mode;
3838 total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
3841 * 12GB/s is maximum BW supported by single DBuf slice.
3843 * FIXME dbuf slice code is broken:
3844 * - must wait for planes to stop using the slice before powering it off
3845 * - plane straddling both slices is illegal in multi-pipe scenarios
3846 * - should validate we stay within the hw bandwidth limits
3848 if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
3849 ddb->enabled_slices = 2;
3851 ddb->enabled_slices = 1;
3859 skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
3860 const struct intel_crtc_state *crtc_state,
3861 const u64 total_data_rate,
3862 struct skl_ddb_allocation *ddb,
3863 struct skl_ddb_entry *alloc, /* out */
3864 int *num_active /* out */)
3866 struct drm_atomic_state *state = crtc_state->base.state;
3867 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3868 struct drm_crtc *for_crtc = crtc_state->base.crtc;
3869 const struct intel_crtc *crtc;
3870 u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
3871 enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
3875 if (WARN_ON(!state) || !crtc_state->base.active) {
3878 *num_active = hweight32(dev_priv->active_crtcs);
3882 if (intel_state->active_pipe_changes)
3883 *num_active = hweight32(intel_state->active_crtcs);
3885 *num_active = hweight32(dev_priv->active_crtcs);
3887 ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
3891 * If the state doesn't change the active CRTC's or there is no
3892 * modeset request, then there's no need to recalculate;
3893 * the existing pipe allocation limits should remain unchanged.
3894 * Note that we're safe from racing commits since any racing commit
3895 * that changes the active CRTC list or do modeset would need to
3896 * grab _all_ crtc locks, including the one we currently hold.
3898 if (!intel_state->active_pipe_changes && !intel_state->modeset) {
3900 * alloc may be cleared by clear_intel_crtc_state,
3901 * copy from old state to be sure
3903 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3908 * Watermark/ddb requirement highly depends upon width of the
3909 * framebuffer, So instead of allocating DDB equally among pipes
3910 * distribute DDB based on resolution/width of the display.
3912 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
3913 const struct drm_display_mode *adjusted_mode =
3914 &crtc_state->base.adjusted_mode;
3915 enum pipe pipe = crtc->pipe;
3916 int hdisplay, vdisplay;
3918 if (!crtc_state->base.enable)
3921 drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
3922 total_width += hdisplay;
3924 if (pipe < for_pipe)
3925 width_before_pipe += hdisplay;
3926 else if (pipe == for_pipe)
3927 pipe_width = hdisplay;
3930 alloc->start = ddb_size * width_before_pipe / total_width;
3931 alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
3934 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
3935 int width, const struct drm_format_info *format,
3936 u64 modifier, unsigned int rotation,
3937 u32 plane_pixel_rate, struct skl_wm_params *wp,
3939 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
3941 const struct skl_wm_params *wp,
3942 const struct skl_wm_level *result_prev,
3943 struct skl_wm_level *result /* out */);
3946 skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
3949 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3950 int level, max_level = ilk_wm_max_level(dev_priv);
3951 struct skl_wm_level wm = {};
3952 int ret, min_ddb_alloc = 0;
3953 struct skl_wm_params wp;
3955 ret = skl_compute_wm_params(crtc_state, 256,
3956 drm_format_info(DRM_FORMAT_ARGB8888),
3957 DRM_FORMAT_MOD_LINEAR,
3959 crtc_state->pixel_rate, &wp, 0);
3962 for (level = 0; level <= max_level; level++) {
3963 skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
3964 if (wm.min_ddb_alloc == U16_MAX)
3967 min_ddb_alloc = wm.min_ddb_alloc;
3970 return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
3973 static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
3974 struct skl_ddb_entry *entry, u32 reg)
3977 entry->start = reg & DDB_ENTRY_MASK;
3978 entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
3985 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
3986 const enum pipe pipe,
3987 const enum plane_id plane_id,
3988 struct skl_ddb_entry *ddb_y,
3989 struct skl_ddb_entry *ddb_uv)
3994 /* Cursor doesn't support NV12/planar, so no extra calculation needed */
3995 if (plane_id == PLANE_CURSOR) {
3996 val = I915_READ(CUR_BUF_CFG(pipe));
3997 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4001 val = I915_READ(PLANE_CTL(pipe, plane_id));
4003 /* No DDB allocated for disabled planes */
4004 if (val & PLANE_CTL_ENABLE)
4005 fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
4006 val & PLANE_CTL_ORDER_RGBX,
4007 val & PLANE_CTL_ALPHA_MASK);
4009 if (INTEL_GEN(dev_priv) >= 11) {
4010 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4011 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4013 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4014 val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
4016 if (is_planar_yuv_format(fourcc))
4019 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4020 skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
4024 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
4025 struct skl_ddb_entry *ddb_y,
4026 struct skl_ddb_entry *ddb_uv)
4028 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4029 enum intel_display_power_domain power_domain;
4030 enum pipe pipe = crtc->pipe;
4031 intel_wakeref_t wakeref;
4032 enum plane_id plane_id;
4034 power_domain = POWER_DOMAIN_PIPE(pipe);
4035 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4039 for_each_plane_id_on_crtc(crtc, plane_id)
4040 skl_ddb_get_hw_plane_state(dev_priv, pipe,
4045 intel_display_power_put(dev_priv, power_domain, wakeref);
4048 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
4049 struct skl_ddb_allocation *ddb /* out */)
4051 ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
4055 * Determines the downscale amount of a plane for the purposes of watermark calculations.
4056 * The bspec defines downscale amount as:
4059 * Horizontal down scale amount = maximum[1, Horizontal source size /
4060 * Horizontal destination size]
4061 * Vertical down scale amount = maximum[1, Vertical source size /
4062 * Vertical destination size]
4063 * Total down scale amount = Horizontal down scale amount *
4064 * Vertical down scale amount
4067 * Return value is provided in 16.16 fixed point form to retain fractional part.
4068 * Caller should take care of dividing & rounding off the value.
4070 static uint_fixed_16_16_t
4071 skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
4072 const struct intel_plane_state *plane_state)
4074 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
4075 u32 src_w, src_h, dst_w, dst_h;
4076 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4077 uint_fixed_16_16_t downscale_h, downscale_w;
4079 if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
4080 return u32_to_fixed16(0);
4082 /* n.b., src is 16.16 fixed point, dst is whole integer */
4083 if (plane->id == PLANE_CURSOR) {
4085 * Cursors only support 0/180 degree rotation,
4086 * hence no need to account for rotation here.
4088 src_w = plane_state->base.src_w >> 16;
4089 src_h = plane_state->base.src_h >> 16;
4090 dst_w = plane_state->base.crtc_w;
4091 dst_h = plane_state->base.crtc_h;
4094 * Src coordinates are already rotated by 270 degrees for
4095 * the 90/270 degree plane rotation cases (to match the
4096 * GTT mapping), hence no need to account for rotation here.
4098 src_w = drm_rect_width(&plane_state->base.src) >> 16;
4099 src_h = drm_rect_height(&plane_state->base.src) >> 16;
4100 dst_w = drm_rect_width(&plane_state->base.dst);
4101 dst_h = drm_rect_height(&plane_state->base.dst);
4104 fp_w_ratio = div_fixed16(src_w, dst_w);
4105 fp_h_ratio = div_fixed16(src_h, dst_h);
4106 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4107 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4109 return mul_fixed16(downscale_w, downscale_h);
4112 static uint_fixed_16_16_t
4113 skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
4115 uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
4117 if (!crtc_state->base.enable)
4118 return pipe_downscale;
4120 if (crtc_state->pch_pfit.enabled) {
4121 u32 src_w, src_h, dst_w, dst_h;
4122 u32 pfit_size = crtc_state->pch_pfit.size;
4123 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4124 uint_fixed_16_16_t downscale_h, downscale_w;
4126 src_w = crtc_state->pipe_src_w;
4127 src_h = crtc_state->pipe_src_h;
4128 dst_w = pfit_size >> 16;
4129 dst_h = pfit_size & 0xffff;
4131 if (!dst_w || !dst_h)
4132 return pipe_downscale;
4134 fp_w_ratio = div_fixed16(src_w, dst_w);
4135 fp_h_ratio = div_fixed16(src_h, dst_h);
4136 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4137 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4139 pipe_downscale = mul_fixed16(downscale_w, downscale_h);
4142 return pipe_downscale;
4145 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
4146 struct intel_crtc_state *crtc_state)
4148 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4149 struct drm_atomic_state *state = crtc_state->base.state;
4150 struct drm_plane *plane;
4151 const struct drm_plane_state *drm_plane_state;
4152 int crtc_clock, dotclk;
4153 u32 pipe_max_pixel_rate;
4154 uint_fixed_16_16_t pipe_downscale;
4155 uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
4157 if (!crtc_state->base.enable)
4160 drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
4161 uint_fixed_16_16_t plane_downscale;
4162 uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
4164 const struct intel_plane_state *plane_state =
4165 to_intel_plane_state(drm_plane_state);
4167 if (!intel_wm_plane_visible(crtc_state, plane_state))
4170 if (WARN_ON(!plane_state->base.fb))
4173 plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state);
4174 bpp = plane_state->base.fb->format->cpp[0] * 8;
4176 plane_downscale = mul_fixed16(plane_downscale,
4179 max_downscale = max_fixed16(plane_downscale, max_downscale);
4181 pipe_downscale = skl_pipe_downscale_amount(crtc_state);
4183 pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
4185 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
4186 dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
4188 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
4191 pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
4193 if (pipe_max_pixel_rate < crtc_clock) {
4194 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
4202 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
4203 const struct intel_plane_state *plane_state,
4206 struct intel_plane *intel_plane = to_intel_plane(plane_state->base.plane);
4208 u32 width = 0, height = 0;
4209 struct drm_framebuffer *fb;
4211 uint_fixed_16_16_t down_scale_amount;
4214 if (!plane_state->base.visible)
4217 fb = plane_state->base.fb;
4218 format = fb->format->format;
4220 if (intel_plane->id == PLANE_CURSOR)
4222 if (plane == 1 && !is_planar_yuv_format(format))
4226 * Src coordinates are already rotated by 270 degrees for
4227 * the 90/270 degree plane rotation cases (to match the
4228 * GTT mapping), hence no need to account for rotation here.
4230 width = drm_rect_width(&plane_state->base.src) >> 16;
4231 height = drm_rect_height(&plane_state->base.src) >> 16;
4233 /* UV plane does 1/2 pixel sub-sampling */
4234 if (plane == 1 && is_planar_yuv_format(format)) {
4239 data_rate = width * height;
4241 down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
4243 rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4245 rate *= fb->format->cpp[plane];
4250 skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
4251 u64 *plane_data_rate,
4252 u64 *uv_plane_data_rate)
4254 struct drm_atomic_state *state = crtc_state->base.state;
4255 struct drm_plane *plane;
4256 const struct drm_plane_state *drm_plane_state;
4257 u64 total_data_rate = 0;
4259 if (WARN_ON(!state))
4262 /* Calculate and cache data rate for each plane */
4263 drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
4264 enum plane_id plane_id = to_intel_plane(plane)->id;
4265 const struct intel_plane_state *plane_state =
4266 to_intel_plane_state(drm_plane_state);
4270 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4271 plane_data_rate[plane_id] = rate;
4272 total_data_rate += rate;
4275 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4276 uv_plane_data_rate[plane_id] = rate;
4277 total_data_rate += rate;
4280 return total_data_rate;
4284 icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
4285 u64 *plane_data_rate)
4287 struct drm_plane *plane;
4288 const struct drm_plane_state *drm_plane_state;
4289 u64 total_data_rate = 0;
4291 if (WARN_ON(!crtc_state->base.state))
4294 /* Calculate and cache data rate for each plane */
4295 drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
4296 const struct intel_plane_state *plane_state =
4297 to_intel_plane_state(drm_plane_state);
4298 enum plane_id plane_id = to_intel_plane(plane)->id;
4301 if (!plane_state->linked_plane) {
4302 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4303 plane_data_rate[plane_id] = rate;
4304 total_data_rate += rate;
4306 enum plane_id y_plane_id;
4309 * The slave plane might not iterate in
4310 * drm_atomic_crtc_state_for_each_plane_state(),
4311 * and needs the master plane state which may be
4312 * NULL if we try get_new_plane_state(), so we
4313 * always calculate from the master.
4315 if (plane_state->slave)
4318 /* Y plane rate is calculated on the slave */
4319 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4320 y_plane_id = plane_state->linked_plane->id;
4321 plane_data_rate[y_plane_id] = rate;
4322 total_data_rate += rate;
4324 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4325 plane_data_rate[plane_id] = rate;
4326 total_data_rate += rate;
4330 return total_data_rate;
4334 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
4335 struct skl_ddb_allocation *ddb /* out */)
4337 struct drm_atomic_state *state = crtc_state->base.state;
4338 struct drm_crtc *crtc = crtc_state->base.crtc;
4339 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4341 struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
4342 u16 alloc_size, start = 0;
4343 u16 total[I915_MAX_PLANES] = {};
4344 u16 uv_total[I915_MAX_PLANES] = {};
4345 u64 total_data_rate;
4346 enum plane_id plane_id;
4348 u64 plane_data_rate[I915_MAX_PLANES] = {};
4349 u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
4353 /* Clear the partitioning for disabled planes. */
4354 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
4355 memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
4357 if (WARN_ON(!state))
4360 if (!crtc_state->base.active) {
4361 alloc->start = alloc->end = 0;
4365 if (INTEL_GEN(dev_priv) >= 11)
4367 icl_get_total_relative_data_rate(crtc_state,
4371 skl_get_total_relative_data_rate(crtc_state,
4373 uv_plane_data_rate);
4376 skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
4377 ddb, alloc, &num_active);
4378 alloc_size = skl_ddb_entry_size(alloc);
4379 if (alloc_size == 0)
4382 /* Allocate fixed number of blocks for cursor. */
4383 total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
4384 alloc_size -= total[PLANE_CURSOR];
4385 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
4386 alloc->end - total[PLANE_CURSOR];
4387 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
4389 if (total_data_rate == 0)
4393 * Find the highest watermark level for which we can satisfy the block
4394 * requirement of active planes.
4396 for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
4398 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4399 const struct skl_plane_wm *wm =
4400 &crtc_state->wm.skl.optimal.planes[plane_id];
4402 if (plane_id == PLANE_CURSOR) {
4403 if (WARN_ON(wm->wm[level].min_ddb_alloc >
4404 total[PLANE_CURSOR])) {
4411 blocks += wm->wm[level].min_ddb_alloc;
4412 blocks += wm->uv_wm[level].min_ddb_alloc;
4415 if (blocks <= alloc_size) {
4416 alloc_size -= blocks;
4422 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4423 DRM_DEBUG_KMS("minimum required %d/%d\n", blocks,
4429 * Grant each plane the blocks it requires at the highest achievable
4430 * watermark level, plus an extra share of the leftover blocks
4431 * proportional to its relative data rate.
4433 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4434 const struct skl_plane_wm *wm =
4435 &crtc_state->wm.skl.optimal.planes[plane_id];
4439 if (plane_id == PLANE_CURSOR)
4443 * We've accounted for all active planes; remaining planes are
4446 if (total_data_rate == 0)
4449 rate = plane_data_rate[plane_id];
4450 extra = min_t(u16, alloc_size,
4451 DIV64_U64_ROUND_UP(alloc_size * rate,
4453 total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
4454 alloc_size -= extra;
4455 total_data_rate -= rate;
4457 if (total_data_rate == 0)
4460 rate = uv_plane_data_rate[plane_id];
4461 extra = min_t(u16, alloc_size,
4462 DIV64_U64_ROUND_UP(alloc_size * rate,
4464 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
4465 alloc_size -= extra;
4466 total_data_rate -= rate;
4468 WARN_ON(alloc_size != 0 || total_data_rate != 0);
4470 /* Set the actual DDB start/end points for each plane */
4471 start = alloc->start;
4472 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4473 struct skl_ddb_entry *plane_alloc =
4474 &crtc_state->wm.skl.plane_ddb_y[plane_id];
4475 struct skl_ddb_entry *uv_plane_alloc =
4476 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
4478 if (plane_id == PLANE_CURSOR)
4481 /* Gen11+ uses a separate plane for UV watermarks */
4482 WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
4484 /* Leave disabled planes at (0,0) */
4485 if (total[plane_id]) {
4486 plane_alloc->start = start;
4487 start += total[plane_id];
4488 plane_alloc->end = start;
4491 if (uv_total[plane_id]) {
4492 uv_plane_alloc->start = start;
4493 start += uv_total[plane_id];
4494 uv_plane_alloc->end = start;
4499 * When we calculated watermark values we didn't know how high
4500 * of a level we'd actually be able to hit, so we just marked
4501 * all levels as "enabled." Go back now and disable the ones
4502 * that aren't actually possible.
4504 for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
4505 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4506 struct skl_plane_wm *wm =
4507 &crtc_state->wm.skl.optimal.planes[plane_id];
4510 * We only disable the watermarks for each plane if
4511 * they exceed the ddb allocation of said plane. This
4512 * is done so that we don't end up touching cursor
4513 * watermarks needlessly when some other plane reduces
4514 * our max possible watermark level.
4516 * Bspec has this to say about the PLANE_WM enable bit:
4517 * "All the watermarks at this level for all enabled
4518 * planes must be enabled before the level will be used."
4519 * So this is actually safe to do.
4521 if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
4522 wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
4523 memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
4526 * Wa_1408961008:icl, ehl
4527 * Underruns with WM1+ disabled
4529 if (IS_GEN(dev_priv, 11) &&
4530 level == 1 && wm->wm[0].plane_en) {
4531 wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
4532 wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
4533 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
4539 * Go back and disable the transition watermark if it turns out we
4540 * don't have enough DDB blocks for it.
4542 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4543 struct skl_plane_wm *wm =
4544 &crtc_state->wm.skl.optimal.planes[plane_id];
4546 if (wm->trans_wm.plane_res_b >= total[plane_id])
4547 memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
4554 * The max latency should be 257 (max the punit can code is 255 and we add 2us
4555 * for the read latency) and cpp should always be <= 8, so that
4556 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4557 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4559 static uint_fixed_16_16_t
4560 skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
4561 u8 cpp, u32 latency, u32 dbuf_block_size)
4563 u32 wm_intermediate_val;
4564 uint_fixed_16_16_t ret;
4567 return FP_16_16_MAX;
4569 wm_intermediate_val = latency * pixel_rate * cpp;
4570 ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
4572 if (INTEL_GEN(dev_priv) >= 10)
4573 ret = add_fixed16_u32(ret, 1);
4578 static uint_fixed_16_16_t
4579 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
4580 uint_fixed_16_16_t plane_blocks_per_line)
4582 u32 wm_intermediate_val;
4583 uint_fixed_16_16_t ret;
4586 return FP_16_16_MAX;
4588 wm_intermediate_val = latency * pixel_rate;
4589 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
4590 pipe_htotal * 1000);
4591 ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
4595 static uint_fixed_16_16_t
4596 intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
4600 uint_fixed_16_16_t linetime_us;
4602 if (!crtc_state->base.active)
4603 return u32_to_fixed16(0);
4605 pixel_rate = crtc_state->pixel_rate;
4607 if (WARN_ON(pixel_rate == 0))
4608 return u32_to_fixed16(0);
4610 crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
4611 linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
4617 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
4618 const struct intel_plane_state *plane_state)
4620 u64 adjusted_pixel_rate;
4621 uint_fixed_16_16_t downscale_amount;
4623 /* Shouldn't reach here on disabled planes... */
4624 if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
4628 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4629 * with additional adjustments for plane-specific scaling.
4631 adjusted_pixel_rate = crtc_state->pixel_rate;
4632 downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
4634 return mul_round_up_u32_fixed16(adjusted_pixel_rate,
4639 skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
4640 int width, const struct drm_format_info *format,
4641 u64 modifier, unsigned int rotation,
4642 u32 plane_pixel_rate, struct skl_wm_params *wp,
4645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4646 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4649 /* only planar format has two planes */
4650 if (color_plane == 1 && !is_planar_yuv_format(format->format)) {
4651 DRM_DEBUG_KMS("Non planar format have single plane\n");
4655 wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
4656 modifier == I915_FORMAT_MOD_Yf_TILED ||
4657 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4658 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4659 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
4660 wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4661 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4662 wp->is_planar = is_planar_yuv_format(format->format);
4665 if (color_plane == 1 && wp->is_planar)
4668 wp->cpp = format->cpp[color_plane];
4669 wp->plane_pixel_rate = plane_pixel_rate;
4671 if (INTEL_GEN(dev_priv) >= 11 &&
4672 modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
4673 wp->dbuf_block_size = 256;
4675 wp->dbuf_block_size = 512;
4677 if (drm_rotation_90_or_270(rotation)) {
4680 wp->y_min_scanlines = 16;
4683 wp->y_min_scanlines = 8;
4686 wp->y_min_scanlines = 4;
4689 MISSING_CASE(wp->cpp);
4693 wp->y_min_scanlines = 4;
4696 if (skl_needs_memory_bw_wa(dev_priv))
4697 wp->y_min_scanlines *= 2;
4699 wp->plane_bytes_per_line = wp->width * wp->cpp;
4701 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
4702 wp->y_min_scanlines,
4703 wp->dbuf_block_size);
4705 if (INTEL_GEN(dev_priv) >= 10)
4708 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
4709 wp->y_min_scanlines);
4710 } else if (wp->x_tiled && IS_GEN(dev_priv, 9)) {
4711 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
4712 wp->dbuf_block_size);
4713 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4715 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
4716 wp->dbuf_block_size) + 1;
4717 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4720 wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
4721 wp->plane_blocks_per_line);
4723 wp->linetime_us = fixed16_to_u32_round_up(
4724 intel_get_linetime_us(crtc_state));
4730 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
4731 const struct intel_plane_state *plane_state,
4732 struct skl_wm_params *wp, int color_plane)
4734 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
4735 const struct drm_framebuffer *fb = plane_state->base.fb;
4738 if (plane->id == PLANE_CURSOR) {
4739 width = plane_state->base.crtc_w;
4742 * Src coordinates are already rotated by 270 degrees for
4743 * the 90/270 degree plane rotation cases (to match the
4744 * GTT mapping), hence no need to account for rotation here.
4746 width = drm_rect_width(&plane_state->base.src) >> 16;
4749 return skl_compute_wm_params(crtc_state, width,
4750 fb->format, fb->modifier,
4751 plane_state->base.rotation,
4752 skl_adjusted_plane_pixel_rate(crtc_state, plane_state),
4756 static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
4758 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4761 /* The number of lines are ignored for the level 0 watermark. */
4765 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
4767 const struct skl_wm_params *wp,
4768 const struct skl_wm_level *result_prev,
4769 struct skl_wm_level *result /* out */)
4771 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
4772 u32 latency = dev_priv->wm.skl_latency[level];
4773 uint_fixed_16_16_t method1, method2;
4774 uint_fixed_16_16_t selected_result;
4775 u32 res_blocks, res_lines, min_ddb_alloc = 0;
4779 result->min_ddb_alloc = U16_MAX;
4784 * WaIncreaseLatencyIPCEnabled: kbl,cfl
4785 * Display WA #1141: kbl,cfl
4787 if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
4788 dev_priv->ipc_enabled)
4791 if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
4794 method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
4795 wp->cpp, latency, wp->dbuf_block_size);
4796 method2 = skl_wm_method2(wp->plane_pixel_rate,
4797 crtc_state->base.adjusted_mode.crtc_htotal,
4799 wp->plane_blocks_per_line);
4802 selected_result = max_fixed16(method2, wp->y_tile_minimum);
4804 if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
4805 wp->dbuf_block_size < 1) &&
4806 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
4807 selected_result = method2;
4808 } else if (latency >= wp->linetime_us) {
4809 if (IS_GEN(dev_priv, 9) &&
4810 !IS_GEMINILAKE(dev_priv))
4811 selected_result = min_fixed16(method1, method2);
4813 selected_result = method2;
4815 selected_result = method1;
4819 res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
4820 res_lines = div_round_up_fixed16(selected_result,
4821 wp->plane_blocks_per_line);
4823 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
4824 /* Display WA #1125: skl,bxt,kbl */
4825 if (level == 0 && wp->rc_surface)
4827 fixed16_to_u32_round_up(wp->y_tile_minimum);
4829 /* Display WA #1126: skl,bxt,kbl */
4830 if (level >= 1 && level <= 7) {
4833 fixed16_to_u32_round_up(wp->y_tile_minimum);
4834 res_lines += wp->y_min_scanlines;
4840 * Make sure result blocks for higher latency levels are
4841 * atleast as high as level below the current level.
4842 * Assumption in DDB algorithm optimization for special
4843 * cases. Also covers Display WA #1125 for RC.
4845 if (result_prev->plane_res_b > res_blocks)
4846 res_blocks = result_prev->plane_res_b;
4850 if (INTEL_GEN(dev_priv) >= 11) {
4854 if (res_lines % wp->y_min_scanlines == 0)
4855 extra_lines = wp->y_min_scanlines;
4857 extra_lines = wp->y_min_scanlines * 2 -
4858 res_lines % wp->y_min_scanlines;
4860 min_ddb_alloc = mul_round_up_u32_fixed16(res_lines + extra_lines,
4861 wp->plane_blocks_per_line);
4863 min_ddb_alloc = res_blocks +
4864 DIV_ROUND_UP(res_blocks, 10);
4868 if (!skl_wm_has_lines(dev_priv, level))
4871 if (res_lines > 31) {
4873 result->min_ddb_alloc = U16_MAX;
4878 * If res_lines is valid, assume we can use this watermark level
4879 * for now. We'll come back and disable it after we calculate the
4880 * DDB allocation if it turns out we don't actually have enough
4881 * blocks to satisfy it.
4883 result->plane_res_b = res_blocks;
4884 result->plane_res_l = res_lines;
4885 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
4886 result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
4887 result->plane_en = true;
4891 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
4892 const struct skl_wm_params *wm_params,
4893 struct skl_wm_level *levels)
4895 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
4896 int level, max_level = ilk_wm_max_level(dev_priv);
4897 struct skl_wm_level *result_prev = &levels[0];
4899 for (level = 0; level <= max_level; level++) {
4900 struct skl_wm_level *result = &levels[level];
4902 skl_compute_plane_wm(crtc_state, level, wm_params,
4903 result_prev, result);
4905 result_prev = result;
4910 skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
4912 struct drm_atomic_state *state = crtc_state->base.state;
4913 struct drm_i915_private *dev_priv = to_i915(state->dev);
4914 uint_fixed_16_16_t linetime_us;
4917 linetime_us = intel_get_linetime_us(crtc_state);
4918 linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
4920 /* Display WA #1135: BXT:ALL GLK:ALL */
4921 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
4927 static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
4928 const struct skl_wm_params *wp,
4929 struct skl_plane_wm *wm)
4931 struct drm_device *dev = crtc_state->base.crtc->dev;
4932 const struct drm_i915_private *dev_priv = to_i915(dev);
4933 u16 trans_min, trans_y_tile_min;
4934 const u16 trans_amount = 10; /* This is configurable amount */
4935 u16 wm0_sel_res_b, trans_offset_b, res_blocks;
4937 /* Transition WM are not recommended by HW team for GEN9 */
4938 if (INTEL_GEN(dev_priv) <= 9)
4941 /* Transition WM don't make any sense if ipc is disabled */
4942 if (!dev_priv->ipc_enabled)
4946 if (INTEL_GEN(dev_priv) >= 11)
4949 trans_offset_b = trans_min + trans_amount;
4952 * The spec asks for Selected Result Blocks for wm0 (the real value),
4953 * not Result Blocks (the integer value). Pay attention to the capital
4954 * letters. The value wm_l0->plane_res_b is actually Result Blocks, but
4955 * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
4956 * and since we later will have to get the ceiling of the sum in the
4957 * transition watermarks calculation, we can just pretend Selected
4958 * Result Blocks is Result Blocks minus 1 and it should work for the
4959 * current platforms.
4961 wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
4965 (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
4966 res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
4969 res_blocks = wm0_sel_res_b + trans_offset_b;
4971 /* WA BUG:1938466 add one block for non y-tile planes */
4972 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
4978 * Just assume we can enable the transition watermark. After
4979 * computing the DDB we'll come back and disable it if that
4980 * assumption turns out to be false.
4982 wm->trans_wm.plane_res_b = res_blocks + 1;
4983 wm->trans_wm.plane_en = true;
4986 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
4987 const struct intel_plane_state *plane_state,
4988 enum plane_id plane_id, int color_plane)
4990 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
4991 struct skl_wm_params wm_params;
4994 ret = skl_compute_plane_wm_params(crtc_state, plane_state,
4995 &wm_params, color_plane);
4999 skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
5000 skl_compute_transition_wm(crtc_state, &wm_params, wm);
5005 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
5006 const struct intel_plane_state *plane_state,
5007 enum plane_id plane_id)
5009 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
5010 struct skl_wm_params wm_params;
5013 wm->is_planar = true;
5015 /* uv plane watermarks must also be validated for NV12/Planar */
5016 ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5021 skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
5026 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
5027 const struct intel_plane_state *plane_state)
5029 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
5030 const struct drm_framebuffer *fb = plane_state->base.fb;
5031 enum plane_id plane_id = plane->id;
5034 if (!intel_wm_plane_visible(crtc_state, plane_state))
5037 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5042 if (fb->format->is_yuv && fb->format->num_planes > 1) {
5043 ret = skl_build_plane_wm_uv(crtc_state, plane_state,
5052 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
5053 const struct intel_plane_state *plane_state)
5055 enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
5058 /* Watermarks calculated in master */
5059 if (plane_state->slave)
5062 if (plane_state->linked_plane) {
5063 const struct drm_framebuffer *fb = plane_state->base.fb;
5064 enum plane_id y_plane_id = plane_state->linked_plane->id;
5066 WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state));
5067 WARN_ON(!fb->format->is_yuv ||
5068 fb->format->num_planes == 1);
5070 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5075 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5079 } else if (intel_wm_plane_visible(crtc_state, plane_state)) {
5080 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5089 static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
5091 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
5092 struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5093 struct drm_plane *plane;
5094 const struct drm_plane_state *drm_plane_state;
5098 * We'll only calculate watermarks for planes that are actually
5099 * enabled, so make sure all other planes are set as disabled.
5101 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
5103 drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state,
5104 &crtc_state->base) {
5105 const struct intel_plane_state *plane_state =
5106 to_intel_plane_state(drm_plane_state);
5108 if (INTEL_GEN(dev_priv) >= 11)
5109 ret = icl_build_plane_wm(crtc_state, plane_state);
5111 ret = skl_build_plane_wm(crtc_state, plane_state);
5116 pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);
5121 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
5123 const struct skl_ddb_entry *entry)
5126 I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start);
5128 I915_WRITE_FW(reg, 0);
5131 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
5133 const struct skl_wm_level *level)
5137 if (level->plane_en)
5139 if (level->ignore_lines)
5140 val |= PLANE_WM_IGNORE_LINES;
5141 val |= level->plane_res_b;
5142 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
5144 I915_WRITE_FW(reg, val);
5147 void skl_write_plane_wm(struct intel_plane *plane,
5148 const struct intel_crtc_state *crtc_state)
5150 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5151 int level, max_level = ilk_wm_max_level(dev_priv);
5152 enum plane_id plane_id = plane->id;
5153 enum pipe pipe = plane->pipe;
5154 const struct skl_plane_wm *wm =
5155 &crtc_state->wm.skl.optimal.planes[plane_id];
5156 const struct skl_ddb_entry *ddb_y =
5157 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5158 const struct skl_ddb_entry *ddb_uv =
5159 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
5161 for (level = 0; level <= max_level; level++) {
5162 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
5165 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
5168 if (INTEL_GEN(dev_priv) >= 11) {
5169 skl_ddb_entry_write(dev_priv,
5170 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5175 swap(ddb_y, ddb_uv);
5177 skl_ddb_entry_write(dev_priv,
5178 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5179 skl_ddb_entry_write(dev_priv,
5180 PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
5183 void skl_write_cursor_wm(struct intel_plane *plane,
5184 const struct intel_crtc_state *crtc_state)
5186 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5187 int level, max_level = ilk_wm_max_level(dev_priv);
5188 enum plane_id plane_id = plane->id;
5189 enum pipe pipe = plane->pipe;
5190 const struct skl_plane_wm *wm =
5191 &crtc_state->wm.skl.optimal.planes[plane_id];
5192 const struct skl_ddb_entry *ddb =
5193 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5195 for (level = 0; level <= max_level; level++) {
5196 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
5199 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5201 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
5204 bool skl_wm_level_equals(const struct skl_wm_level *l1,
5205 const struct skl_wm_level *l2)
5207 return l1->plane_en == l2->plane_en &&
5208 l1->ignore_lines == l2->ignore_lines &&
5209 l1->plane_res_l == l2->plane_res_l &&
5210 l1->plane_res_b == l2->plane_res_b;
5213 static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
5214 const struct skl_plane_wm *wm1,
5215 const struct skl_plane_wm *wm2)
5217 int level, max_level = ilk_wm_max_level(dev_priv);
5219 for (level = 0; level <= max_level; level++) {
5220 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]) ||
5221 !skl_wm_level_equals(&wm1->uv_wm[level], &wm2->uv_wm[level]))
5225 return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm);
5228 static bool skl_pipe_wm_equals(struct intel_crtc *crtc,
5229 const struct skl_pipe_wm *wm1,
5230 const struct skl_pipe_wm *wm2)
5232 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5233 enum plane_id plane_id;
5235 for_each_plane_id_on_crtc(crtc, plane_id) {
5236 if (!skl_plane_wm_equals(dev_priv,
5237 &wm1->planes[plane_id],
5238 &wm2->planes[plane_id]))
5242 return wm1->linetime == wm2->linetime;
5245 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
5246 const struct skl_ddb_entry *b)
5248 return a->start < b->end && b->start < a->end;
5251 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
5252 const struct skl_ddb_entry *entries,
5253 int num_entries, int ignore_idx)
5257 for (i = 0; i < num_entries; i++) {
5258 if (i != ignore_idx &&
5259 skl_ddb_entries_overlap(ddb, &entries[i]))
5267 pipes_modified(struct intel_atomic_state *state)
5269 struct intel_crtc *crtc;
5270 struct intel_crtc_state *crtc_state;
5273 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
5274 ret |= drm_crtc_mask(&crtc->base);
5280 skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
5281 struct intel_crtc_state *new_crtc_state)
5283 struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
5284 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5285 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5286 struct intel_plane *plane;
5288 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5289 struct intel_plane_state *plane_state;
5290 enum plane_id plane_id = plane->id;
5292 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
5293 &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
5294 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
5295 &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
5298 plane_state = intel_atomic_get_plane_state(state, plane);
5299 if (IS_ERR(plane_state))
5300 return PTR_ERR(plane_state);
5302 new_crtc_state->update_planes |= BIT(plane_id);
5309 skl_compute_ddb(struct intel_atomic_state *state)
5311 const struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5312 struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
5313 struct intel_crtc_state *old_crtc_state;
5314 struct intel_crtc_state *new_crtc_state;
5315 struct intel_crtc *crtc;
5318 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
5320 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5321 new_crtc_state, i) {
5322 ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
5326 ret = skl_ddb_add_affected_planes(old_crtc_state,
5335 static char enast(bool enable)
5337 return enable ? '*' : ' ';
5341 skl_print_wm_changes(struct intel_atomic_state *state)
5343 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5344 const struct intel_crtc_state *old_crtc_state;
5345 const struct intel_crtc_state *new_crtc_state;
5346 struct intel_plane *plane;
5347 struct intel_crtc *crtc;
5350 if ((drm_debug & DRM_UT_KMS) == 0)
5353 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5354 new_crtc_state, i) {
5355 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm;
5357 old_pipe_wm = &old_crtc_state->wm.skl.optimal;
5358 new_pipe_wm = &new_crtc_state->wm.skl.optimal;
5360 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5361 enum plane_id plane_id = plane->id;
5362 const struct skl_ddb_entry *old, *new;
5364 old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
5365 new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
5367 if (skl_ddb_entry_equal(old, new))
5370 DRM_DEBUG_KMS("[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
5371 plane->base.base.id, plane->base.name,
5372 old->start, old->end, new->start, new->end,
5373 skl_ddb_entry_size(old), skl_ddb_entry_size(new));
5376 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5377 enum plane_id plane_id = plane->id;
5378 const struct skl_plane_wm *old_wm, *new_wm;
5380 old_wm = &old_pipe_wm->planes[plane_id];
5381 new_wm = &new_pipe_wm->planes[plane_id];
5383 if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
5386 DRM_DEBUG_KMS("[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm"
5387 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm\n",
5388 plane->base.base.id, plane->base.name,
5389 enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
5390 enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
5391 enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
5392 enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
5393 enast(old_wm->trans_wm.plane_en),
5394 enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
5395 enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
5396 enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
5397 enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
5398 enast(new_wm->trans_wm.plane_en));
5400 DRM_DEBUG_KMS("[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
5401 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
5402 plane->base.base.id, plane->base.name,
5403 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
5404 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
5405 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
5406 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
5407 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
5408 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
5409 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
5410 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
5411 enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
5413 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
5414 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
5415 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
5416 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
5417 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
5418 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
5419 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
5420 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
5421 enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
5423 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5424 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5425 plane->base.base.id, plane->base.name,
5426 old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
5427 old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
5428 old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
5429 old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
5430 old_wm->trans_wm.plane_res_b,
5431 new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
5432 new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
5433 new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
5434 new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
5435 new_wm->trans_wm.plane_res_b);
5437 DRM_DEBUG_KMS("[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5438 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5439 plane->base.base.id, plane->base.name,
5440 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
5441 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
5442 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
5443 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
5444 old_wm->trans_wm.min_ddb_alloc,
5445 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
5446 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
5447 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
5448 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
5449 new_wm->trans_wm.min_ddb_alloc);
5455 skl_ddb_add_affected_pipes(struct intel_atomic_state *state, bool *changed)
5457 struct drm_device *dev = state->base.dev;
5458 const struct drm_i915_private *dev_priv = to_i915(dev);
5459 struct intel_crtc *crtc;
5460 struct intel_crtc_state *crtc_state;
5461 u32 realloc_pipes = pipes_modified(state);
5465 * When we distrust bios wm we always need to recompute to set the
5466 * expected DDB allocations for each CRTC.
5468 if (dev_priv->wm.distrust_bios_wm)
5472 * If this transaction isn't actually touching any CRTC's, don't
5473 * bother with watermark calculation. Note that if we pass this
5474 * test, we're guaranteed to hold at least one CRTC state mutex,
5475 * which means we can safely use values like dev_priv->active_crtcs
5476 * since any racing commits that want to update them would need to
5477 * hold _all_ CRTC state mutexes.
5479 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
5486 * If this is our first atomic update following hardware readout,
5487 * we can't trust the DDB that the BIOS programmed for us. Let's
5488 * pretend that all pipes switched active status so that we'll
5489 * ensure a full DDB recompute.
5491 if (dev_priv->wm.distrust_bios_wm) {
5492 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
5493 state->base.acquire_ctx);
5497 state->active_pipe_changes = ~0;
5500 * We usually only initialize state->active_crtcs if we
5501 * we're doing a modeset; make sure this field is always
5502 * initialized during the sanitization process that happens
5503 * on the first commit too.
5505 if (!state->modeset)
5506 state->active_crtcs = dev_priv->active_crtcs;
5510 * If the modeset changes which CRTC's are active, we need to
5511 * recompute the DDB allocation for *all* active pipes, even
5512 * those that weren't otherwise being modified in any way by this
5513 * atomic commit. Due to the shrinking of the per-pipe allocations
5514 * when new active CRTC's are added, it's possible for a pipe that
5515 * we were already using and aren't changing at all here to suddenly
5516 * become invalid if its DDB needs exceeds its new allocation.
5518 * Note that if we wind up doing a full DDB recompute, we can't let
5519 * any other display updates race with this transaction, so we need
5520 * to grab the lock on *all* CRTC's.
5522 if (state->active_pipe_changes || state->modeset) {
5524 state->wm_results.dirty_pipes = ~0;
5528 * We're not recomputing for the pipes not included in the commit, so
5529 * make sure we start with the current state.
5531 for_each_intel_crtc_mask(dev, crtc, realloc_pipes) {
5532 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5533 if (IS_ERR(crtc_state))
5534 return PTR_ERR(crtc_state);
5541 * To make sure the cursor watermark registers are always consistent
5542 * with our computed state the following scenario needs special
5546 * 2. move cursor entirely offscreen
5549 * Step 2. does call .disable_plane() but does not zero the watermarks
5550 * (since we consider an offscreen cursor still active for the purposes
5551 * of watermarks). Step 3. would not normally call .disable_plane()
5552 * because the actual plane visibility isn't changing, and we don't
5553 * deallocate the cursor ddb until the pipe gets disabled. So we must
5554 * force step 3. to call .disable_plane() to update the watermark
5555 * registers properly.
5557 * Other planes do not suffer from this issues as their watermarks are
5558 * calculated based on the actual plane visibility. The only time this
5559 * can trigger for the other planes is during the initial readout as the
5560 * default value of the watermarks registers is not zero.
5562 static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
5563 struct intel_crtc *crtc)
5565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5566 const struct intel_crtc_state *old_crtc_state =
5567 intel_atomic_get_old_crtc_state(state, crtc);
5568 struct intel_crtc_state *new_crtc_state =
5569 intel_atomic_get_new_crtc_state(state, crtc);
5570 struct intel_plane *plane;
5572 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5573 struct intel_plane_state *plane_state;
5574 enum plane_id plane_id = plane->id;
5577 * Force a full wm update for every plane on modeset.
5578 * Required because the reset value of the wm registers
5579 * is non-zero, whereas we want all disabled planes to
5580 * have zero watermarks. So if we turn off the relevant
5581 * power well the hardware state will go out of sync
5582 * with the software state.
5584 if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) &&
5585 skl_plane_wm_equals(dev_priv,
5586 &old_crtc_state->wm.skl.optimal.planes[plane_id],
5587 &new_crtc_state->wm.skl.optimal.planes[plane_id]))
5590 plane_state = intel_atomic_get_plane_state(state, plane);
5591 if (IS_ERR(plane_state))
5592 return PTR_ERR(plane_state);
5594 new_crtc_state->update_planes |= BIT(plane_id);
5601 skl_compute_wm(struct intel_atomic_state *state)
5603 struct intel_crtc *crtc;
5604 struct intel_crtc_state *new_crtc_state;
5605 struct intel_crtc_state *old_crtc_state;
5606 struct skl_ddb_values *results = &state->wm_results;
5607 bool changed = false;
5610 /* Clear all dirty flags */
5611 results->dirty_pipes = 0;
5613 ret = skl_ddb_add_affected_pipes(state, &changed);
5614 if (ret || !changed)
5618 * Calculate WM's for all pipes that are part of this transaction.
5619 * Note that skl_ddb_add_affected_pipes may have added more CRTC's that
5620 * weren't otherwise being modified (and set bits in dirty_pipes) if
5621 * pipe allocations had to change.
5623 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5624 new_crtc_state, i) {
5625 ret = skl_build_pipe_wm(new_crtc_state);
5629 ret = skl_wm_add_affected_planes(state, crtc);
5633 if (!skl_pipe_wm_equals(crtc,
5634 &old_crtc_state->wm.skl.optimal,
5635 &new_crtc_state->wm.skl.optimal))
5636 results->dirty_pipes |= drm_crtc_mask(&crtc->base);
5639 ret = skl_compute_ddb(state);
5643 skl_print_wm_changes(state);
5648 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
5649 struct intel_crtc_state *crtc_state)
5651 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5652 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5653 struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5654 enum pipe pipe = crtc->pipe;
5656 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
5659 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
5662 static void skl_initial_wm(struct intel_atomic_state *state,
5663 struct intel_crtc_state *crtc_state)
5665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5666 struct drm_device *dev = intel_crtc->base.dev;
5667 struct drm_i915_private *dev_priv = to_i915(dev);
5668 struct skl_ddb_values *results = &state->wm_results;
5670 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
5673 mutex_lock(&dev_priv->wm.wm_mutex);
5675 if (crtc_state->base.active_changed)
5676 skl_atomic_update_crtc_wm(state, crtc_state);
5678 mutex_unlock(&dev_priv->wm.wm_mutex);
5681 static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
5682 struct intel_wm_config *config)
5684 struct intel_crtc *crtc;
5686 /* Compute the currently _active_ config */
5687 for_each_intel_crtc(&dev_priv->drm, crtc) {
5688 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
5690 if (!wm->pipe_enabled)
5693 config->sprites_enabled |= wm->sprites_enabled;
5694 config->sprites_scaled |= wm->sprites_scaled;
5695 config->num_pipes_active++;
5699 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
5701 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
5702 struct ilk_wm_maximums max;
5703 struct intel_wm_config config = {};
5704 struct ilk_wm_values results = {};
5705 enum intel_ddb_partitioning partitioning;
5707 ilk_compute_wm_config(dev_priv, &config);
5709 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
5710 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
5712 /* 5/6 split only in single pipe config on IVB+ */
5713 if (INTEL_GEN(dev_priv) >= 7 &&
5714 config.num_pipes_active == 1 && config.sprites_enabled) {
5715 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
5716 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
5718 best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
5720 best_lp_wm = &lp_wm_1_2;
5723 partitioning = (best_lp_wm == &lp_wm_1_2) ?
5724 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
5726 ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
5728 ilk_write_wm_values(dev_priv, &results);
5731 static void ilk_initial_watermarks(struct intel_atomic_state *state,
5732 struct intel_crtc_state *crtc_state)
5734 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
5735 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5737 mutex_lock(&dev_priv->wm.wm_mutex);
5738 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
5739 ilk_program_watermarks(dev_priv);
5740 mutex_unlock(&dev_priv->wm.wm_mutex);
5743 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
5744 struct intel_crtc_state *crtc_state)
5746 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
5747 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5749 if (!crtc_state->wm.need_postvbl_update)
5752 mutex_lock(&dev_priv->wm.wm_mutex);
5753 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
5754 ilk_program_watermarks(dev_priv);
5755 mutex_unlock(&dev_priv->wm.wm_mutex);
5758 static inline void skl_wm_level_from_reg_val(u32 val,
5759 struct skl_wm_level *level)
5761 level->plane_en = val & PLANE_WM_EN;
5762 level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
5763 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
5764 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
5765 PLANE_WM_LINES_MASK;
5768 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
5769 struct skl_pipe_wm *out)
5771 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5772 enum pipe pipe = crtc->pipe;
5773 int level, max_level;
5774 enum plane_id plane_id;
5777 max_level = ilk_wm_max_level(dev_priv);
5779 for_each_plane_id_on_crtc(crtc, plane_id) {
5780 struct skl_plane_wm *wm = &out->planes[plane_id];
5782 for (level = 0; level <= max_level; level++) {
5783 if (plane_id != PLANE_CURSOR)
5784 val = I915_READ(PLANE_WM(pipe, plane_id, level));
5786 val = I915_READ(CUR_WM(pipe, level));
5788 skl_wm_level_from_reg_val(val, &wm->wm[level]);
5791 if (plane_id != PLANE_CURSOR)
5792 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
5794 val = I915_READ(CUR_WM_TRANS(pipe));
5796 skl_wm_level_from_reg_val(val, &wm->trans_wm);
5802 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
5805 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
5807 struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
5808 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
5809 struct intel_crtc *crtc;
5810 struct intel_crtc_state *crtc_state;
5812 skl_ddb_get_hw_state(dev_priv, ddb);
5813 for_each_intel_crtc(&dev_priv->drm, crtc) {
5814 crtc_state = to_intel_crtc_state(crtc->base.state);
5816 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
5819 hw->dirty_pipes |= drm_crtc_mask(&crtc->base);
5822 if (dev_priv->active_crtcs) {
5823 /* Fully recompute DDB on first atomic commit */
5824 dev_priv->wm.distrust_bios_wm = true;
5828 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
5830 struct drm_device *dev = crtc->base.dev;
5831 struct drm_i915_private *dev_priv = to_i915(dev);
5832 struct ilk_wm_values *hw = &dev_priv->wm.hw;
5833 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
5834 struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
5835 enum pipe pipe = crtc->pipe;
5836 static const i915_reg_t wm0_pipe_reg[] = {
5837 [PIPE_A] = WM0_PIPEA_ILK,
5838 [PIPE_B] = WM0_PIPEB_ILK,
5839 [PIPE_C] = WM0_PIPEC_IVB,
5842 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
5843 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5844 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
5846 memset(active, 0, sizeof(*active));
5848 active->pipe_enabled = crtc->active;
5850 if (active->pipe_enabled) {
5851 u32 tmp = hw->wm_pipe[pipe];
5854 * For active pipes LP0 watermark is marked as
5855 * enabled, and LP1+ watermaks as disabled since
5856 * we can't really reverse compute them in case
5857 * multiple pipes are active.
5859 active->wm[0].enable = true;
5860 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
5861 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
5862 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
5863 active->linetime = hw->wm_linetime[pipe];
5865 int level, max_level = ilk_wm_max_level(dev_priv);
5868 * For inactive pipes, all watermark levels
5869 * should be marked as enabled but zeroed,
5870 * which is what we'd compute them to.
5872 for (level = 0; level <= max_level; level++)
5873 active->wm[level].enable = true;
5876 crtc->wm.active.ilk = *active;
5879 #define _FW_WM(value, plane) \
5880 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5881 #define _FW_WM_VLV(value, plane) \
5882 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5884 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
5885 struct g4x_wm_values *wm)
5889 tmp = I915_READ(DSPFW1);
5890 wm->sr.plane = _FW_WM(tmp, SR);
5891 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5892 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
5893 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
5895 tmp = I915_READ(DSPFW2);
5896 wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
5897 wm->sr.fbc = _FW_WM(tmp, FBC_SR);
5898 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5899 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
5900 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5901 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
5903 tmp = I915_READ(DSPFW3);
5904 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
5905 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5906 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
5907 wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
5910 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
5911 struct vlv_wm_values *wm)
5916 for_each_pipe(dev_priv, pipe) {
5917 tmp = I915_READ(VLV_DDL(pipe));
5919 wm->ddl[pipe].plane[PLANE_PRIMARY] =
5920 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5921 wm->ddl[pipe].plane[PLANE_CURSOR] =
5922 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5923 wm->ddl[pipe].plane[PLANE_SPRITE0] =
5924 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5925 wm->ddl[pipe].plane[PLANE_SPRITE1] =
5926 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5929 tmp = I915_READ(DSPFW1);
5930 wm->sr.plane = _FW_WM(tmp, SR);
5931 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5932 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
5933 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
5935 tmp = I915_READ(DSPFW2);
5936 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
5937 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5938 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
5940 tmp = I915_READ(DSPFW3);
5941 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5943 if (IS_CHERRYVIEW(dev_priv)) {
5944 tmp = I915_READ(DSPFW7_CHV);
5945 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5946 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5948 tmp = I915_READ(DSPFW8_CHV);
5949 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
5950 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
5952 tmp = I915_READ(DSPFW9_CHV);
5953 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
5954 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
5956 tmp = I915_READ(DSPHOWM);
5957 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5958 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
5959 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
5960 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
5961 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5962 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5963 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5964 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5965 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5966 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5968 tmp = I915_READ(DSPFW7);
5969 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5970 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5972 tmp = I915_READ(DSPHOWM);
5973 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5974 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5975 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5976 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5977 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5978 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5979 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5986 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
5988 struct g4x_wm_values *wm = &dev_priv->wm.g4x;
5989 struct intel_crtc *crtc;
5991 g4x_read_wm_values(dev_priv, wm);
5993 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5995 for_each_intel_crtc(&dev_priv->drm, crtc) {
5996 struct intel_crtc_state *crtc_state =
5997 to_intel_crtc_state(crtc->base.state);
5998 struct g4x_wm_state *active = &crtc->wm.active.g4x;
5999 struct g4x_pipe_wm *raw;
6000 enum pipe pipe = crtc->pipe;
6001 enum plane_id plane_id;
6002 int level, max_level;
6004 active->cxsr = wm->cxsr;
6005 active->hpll_en = wm->hpll_en;
6006 active->fbc_en = wm->fbc_en;
6008 active->sr = wm->sr;
6009 active->hpll = wm->hpll;
6011 for_each_plane_id_on_crtc(crtc, plane_id) {
6012 active->wm.plane[plane_id] =
6013 wm->pipe[pipe].plane[plane_id];
6016 if (wm->cxsr && wm->hpll_en)
6017 max_level = G4X_WM_LEVEL_HPLL;
6019 max_level = G4X_WM_LEVEL_SR;
6021 max_level = G4X_WM_LEVEL_NORMAL;
6023 level = G4X_WM_LEVEL_NORMAL;
6024 raw = &crtc_state->wm.g4x.raw[level];
6025 for_each_plane_id_on_crtc(crtc, plane_id)
6026 raw->plane[plane_id] = active->wm.plane[plane_id];
6028 if (++level > max_level)
6031 raw = &crtc_state->wm.g4x.raw[level];
6032 raw->plane[PLANE_PRIMARY] = active->sr.plane;
6033 raw->plane[PLANE_CURSOR] = active->sr.cursor;
6034 raw->plane[PLANE_SPRITE0] = 0;
6035 raw->fbc = active->sr.fbc;
6037 if (++level > max_level)
6040 raw = &crtc_state->wm.g4x.raw[level];
6041 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
6042 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
6043 raw->plane[PLANE_SPRITE0] = 0;
6044 raw->fbc = active->hpll.fbc;
6047 for_each_plane_id_on_crtc(crtc, plane_id)
6048 g4x_raw_plane_wm_set(crtc_state, level,
6049 plane_id, USHRT_MAX);
6050 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
6052 crtc_state->wm.g4x.optimal = *active;
6053 crtc_state->wm.g4x.intermediate = *active;
6055 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
6057 wm->pipe[pipe].plane[PLANE_PRIMARY],
6058 wm->pipe[pipe].plane[PLANE_CURSOR],
6059 wm->pipe[pipe].plane[PLANE_SPRITE0]);
6062 DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
6063 wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
6064 DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
6065 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
6066 DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
6067 yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
6070 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
6072 struct intel_plane *plane;
6073 struct intel_crtc *crtc;
6075 mutex_lock(&dev_priv->wm.wm_mutex);
6077 for_each_intel_plane(&dev_priv->drm, plane) {
6078 struct intel_crtc *crtc =
6079 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6080 struct intel_crtc_state *crtc_state =
6081 to_intel_crtc_state(crtc->base.state);
6082 struct intel_plane_state *plane_state =
6083 to_intel_plane_state(plane->base.state);
6084 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
6085 enum plane_id plane_id = plane->id;
6088 if (plane_state->base.visible)
6091 for (level = 0; level < 3; level++) {
6092 struct g4x_pipe_wm *raw =
6093 &crtc_state->wm.g4x.raw[level];
6095 raw->plane[plane_id] = 0;
6096 wm_state->wm.plane[plane_id] = 0;
6099 if (plane_id == PLANE_PRIMARY) {
6100 for (level = 0; level < 3; level++) {
6101 struct g4x_pipe_wm *raw =
6102 &crtc_state->wm.g4x.raw[level];
6106 wm_state->sr.fbc = 0;
6107 wm_state->hpll.fbc = 0;
6108 wm_state->fbc_en = false;
6112 for_each_intel_crtc(&dev_priv->drm, crtc) {
6113 struct intel_crtc_state *crtc_state =
6114 to_intel_crtc_state(crtc->base.state);
6116 crtc_state->wm.g4x.intermediate =
6117 crtc_state->wm.g4x.optimal;
6118 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
6121 g4x_program_watermarks(dev_priv);
6123 mutex_unlock(&dev_priv->wm.wm_mutex);
6126 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
6128 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
6129 struct intel_crtc *crtc;
6132 vlv_read_wm_values(dev_priv, wm);
6134 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
6135 wm->level = VLV_WM_LEVEL_PM2;
6137 if (IS_CHERRYVIEW(dev_priv)) {
6138 vlv_punit_get(dev_priv);
6140 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
6141 if (val & DSP_MAXFIFO_PM5_ENABLE)
6142 wm->level = VLV_WM_LEVEL_PM5;
6145 * If DDR DVFS is disabled in the BIOS, Punit
6146 * will never ack the request. So if that happens
6147 * assume we don't have to enable/disable DDR DVFS
6148 * dynamically. To test that just set the REQ_ACK
6149 * bit to poke the Punit, but don't change the
6150 * HIGH/LOW bits so that we don't actually change
6151 * the current state.
6153 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6154 val |= FORCE_DDR_FREQ_REQ_ACK;
6155 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
6157 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
6158 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
6159 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
6160 "assuming DDR DVFS is disabled\n");
6161 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
6163 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6164 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
6165 wm->level = VLV_WM_LEVEL_DDR_DVFS;
6168 vlv_punit_put(dev_priv);
6171 for_each_intel_crtc(&dev_priv->drm, crtc) {
6172 struct intel_crtc_state *crtc_state =
6173 to_intel_crtc_state(crtc->base.state);
6174 struct vlv_wm_state *active = &crtc->wm.active.vlv;
6175 const struct vlv_fifo_state *fifo_state =
6176 &crtc_state->wm.vlv.fifo_state;
6177 enum pipe pipe = crtc->pipe;
6178 enum plane_id plane_id;
6181 vlv_get_fifo_size(crtc_state);
6183 active->num_levels = wm->level + 1;
6184 active->cxsr = wm->cxsr;
6186 for (level = 0; level < active->num_levels; level++) {
6187 struct g4x_pipe_wm *raw =
6188 &crtc_state->wm.vlv.raw[level];
6190 active->sr[level].plane = wm->sr.plane;
6191 active->sr[level].cursor = wm->sr.cursor;
6193 for_each_plane_id_on_crtc(crtc, plane_id) {
6194 active->wm[level].plane[plane_id] =
6195 wm->pipe[pipe].plane[plane_id];
6197 raw->plane[plane_id] =
6198 vlv_invert_wm_value(active->wm[level].plane[plane_id],
6199 fifo_state->plane[plane_id]);
6203 for_each_plane_id_on_crtc(crtc, plane_id)
6204 vlv_raw_plane_wm_set(crtc_state, level,
6205 plane_id, USHRT_MAX);
6206 vlv_invalidate_wms(crtc, active, level);
6208 crtc_state->wm.vlv.optimal = *active;
6209 crtc_state->wm.vlv.intermediate = *active;
6211 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
6213 wm->pipe[pipe].plane[PLANE_PRIMARY],
6214 wm->pipe[pipe].plane[PLANE_CURSOR],
6215 wm->pipe[pipe].plane[PLANE_SPRITE0],
6216 wm->pipe[pipe].plane[PLANE_SPRITE1]);
6219 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
6220 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
6223 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
6225 struct intel_plane *plane;
6226 struct intel_crtc *crtc;
6228 mutex_lock(&dev_priv->wm.wm_mutex);
6230 for_each_intel_plane(&dev_priv->drm, plane) {
6231 struct intel_crtc *crtc =
6232 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6233 struct intel_crtc_state *crtc_state =
6234 to_intel_crtc_state(crtc->base.state);
6235 struct intel_plane_state *plane_state =
6236 to_intel_plane_state(plane->base.state);
6237 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
6238 const struct vlv_fifo_state *fifo_state =
6239 &crtc_state->wm.vlv.fifo_state;
6240 enum plane_id plane_id = plane->id;
6243 if (plane_state->base.visible)
6246 for (level = 0; level < wm_state->num_levels; level++) {
6247 struct g4x_pipe_wm *raw =
6248 &crtc_state->wm.vlv.raw[level];
6250 raw->plane[plane_id] = 0;
6252 wm_state->wm[level].plane[plane_id] =
6253 vlv_invert_wm_value(raw->plane[plane_id],
6254 fifo_state->plane[plane_id]);
6258 for_each_intel_crtc(&dev_priv->drm, crtc) {
6259 struct intel_crtc_state *crtc_state =
6260 to_intel_crtc_state(crtc->base.state);
6262 crtc_state->wm.vlv.intermediate =
6263 crtc_state->wm.vlv.optimal;
6264 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
6267 vlv_program_watermarks(dev_priv);
6269 mutex_unlock(&dev_priv->wm.wm_mutex);
6273 * FIXME should probably kill this and improve
6274 * the real watermark readout/sanitation instead
6276 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6278 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6279 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6280 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6283 * Don't touch WM1S_LP_EN here.
6284 * Doing so could cause underruns.
6288 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
6290 struct ilk_wm_values *hw = &dev_priv->wm.hw;
6291 struct intel_crtc *crtc;
6293 ilk_init_lp_watermarks(dev_priv);
6295 for_each_intel_crtc(&dev_priv->drm, crtc)
6296 ilk_pipe_wm_get_hw_state(crtc);
6298 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
6299 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
6300 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
6302 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
6303 if (INTEL_GEN(dev_priv) >= 7) {
6304 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
6305 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
6308 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6309 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
6310 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6311 else if (IS_IVYBRIDGE(dev_priv))
6312 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
6313 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6316 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
6320 * intel_update_watermarks - update FIFO watermark values based on current modes
6321 * @crtc: the #intel_crtc on which to compute the WM
6323 * Calculate watermark values for the various WM regs based on current mode
6324 * and plane configuration.
6326 * There are several cases to deal with here:
6327 * - normal (i.e. non-self-refresh)
6328 * - self-refresh (SR) mode
6329 * - lines are large relative to FIFO size (buffer can hold up to 2)
6330 * - lines are small relative to FIFO size (buffer can hold more than 2
6331 * lines), so need to account for TLB latency
6333 * The normal calculation is:
6334 * watermark = dotclock * bytes per pixel * latency
6335 * where latency is platform & configuration dependent (we assume pessimal
6338 * The SR calculation is:
6339 * watermark = (trunc(latency/line time)+1) * surface width *
6342 * line time = htotal / dotclock
6343 * surface width = hdisplay for normal plane and 64 for cursor
6344 * and latency is assumed to be high, as above.
6346 * The final value programmed to the register should always be rounded up,
6347 * and include an extra 2 entries to account for clock crossings.
6349 * We don't use the sprite, so we can ignore that. And on Crestline we have
6350 * to set the non-SR watermarks to 8.
6352 void intel_update_watermarks(struct intel_crtc *crtc)
6354 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6356 if (dev_priv->display.update_wm)
6357 dev_priv->display.update_wm(crtc);
6360 void intel_enable_ipc(struct drm_i915_private *dev_priv)
6364 if (!HAS_IPC(dev_priv))
6367 val = I915_READ(DISP_ARB_CTL2);
6369 if (dev_priv->ipc_enabled)
6370 val |= DISP_IPC_ENABLE;
6372 val &= ~DISP_IPC_ENABLE;
6374 I915_WRITE(DISP_ARB_CTL2, val);
6377 static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
6379 /* Display WA #0477 WaDisableIPC: skl */
6380 if (IS_SKYLAKE(dev_priv))
6383 /* Display WA #1141: SKL:all KBL:all CFL */
6384 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
6385 return dev_priv->dram_info.symmetric_memory;
6390 void intel_init_ipc(struct drm_i915_private *dev_priv)
6392 if (!HAS_IPC(dev_priv))
6395 dev_priv->ipc_enabled = intel_can_enable_ipc(dev_priv);
6397 intel_enable_ipc(dev_priv);
6401 * Lock protecting IPS related data structures
6403 DEFINE_SPINLOCK(mchdev_lock);
6405 bool ironlake_set_drps(struct drm_i915_private *i915, u8 val)
6407 struct intel_uncore *uncore = &i915->uncore;
6410 lockdep_assert_held(&mchdev_lock);
6412 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
6413 if (rgvswctl & MEMCTL_CMD_STS) {
6414 DRM_DEBUG("gpu busy, RCS change rejected\n");
6415 return false; /* still busy with another command */
6418 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6419 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6420 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
6421 intel_uncore_posting_read16(uncore, MEMSWCTL);
6423 rgvswctl |= MEMCTL_CMD_STS;
6424 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
6429 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
6431 struct intel_uncore *uncore = &dev_priv->uncore;
6433 u8 fmax, fmin, fstart, vstart;
6435 spin_lock_irq(&mchdev_lock);
6437 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
6439 /* Enable temp reporting */
6440 intel_uncore_write16(uncore, PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6441 intel_uncore_write16(uncore, TSC1, I915_READ(TSC1) | TSE);
6443 /* 100ms RC evaluation intervals */
6444 intel_uncore_write(uncore, RCUPEI, 100000);
6445 intel_uncore_write(uncore, RCDNEI, 100000);
6447 /* Set max/min thresholds to 90ms and 80ms respectively */
6448 intel_uncore_write(uncore, RCBMAXAVG, 90000);
6449 intel_uncore_write(uncore, RCBMINAVG, 80000);
6451 intel_uncore_write(uncore, MEMIHYST, 1);
6453 /* Set up min, max, and cur for interrupt handling */
6454 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6455 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6456 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6457 MEMMODE_FSTART_SHIFT;
6459 vstart = (intel_uncore_read(uncore, PXVFREQ(fstart)) &
6460 PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT;
6462 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
6463 dev_priv->ips.fstart = fstart;
6465 dev_priv->ips.max_delay = fstart;
6466 dev_priv->ips.min_delay = fmin;
6467 dev_priv->ips.cur_delay = fstart;
6469 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6470 fmax, fmin, fstart);
6472 intel_uncore_write(uncore,
6474 MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6477 * Interrupts will be enabled in ironlake_irq_postinstall
6480 intel_uncore_write(uncore, VIDSTART, vstart);
6481 intel_uncore_posting_read(uncore, VIDSTART);
6483 rgvmodectl |= MEMMODE_SWMODE_EN;
6484 intel_uncore_write(uncore, MEMMODECTL, rgvmodectl);
6486 if (wait_for_atomic((intel_uncore_read(uncore, MEMSWCTL) &
6487 MEMCTL_CMD_STS) == 0, 10))
6488 DRM_ERROR("stuck trying to change perf mode\n");
6491 ironlake_set_drps(dev_priv, fstart);
6493 dev_priv->ips.last_count1 =
6494 intel_uncore_read(uncore, DMIEC) +
6495 intel_uncore_read(uncore, DDREC) +
6496 intel_uncore_read(uncore, CSIEC);
6497 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
6498 dev_priv->ips.last_count2 = intel_uncore_read(uncore, GFXEC);
6499 dev_priv->ips.last_time2 = ktime_get_raw_ns();
6501 spin_unlock_irq(&mchdev_lock);
6504 static void ironlake_disable_drps(struct drm_i915_private *i915)
6506 struct intel_uncore *uncore = &i915->uncore;
6509 spin_lock_irq(&mchdev_lock);
6511 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
6513 /* Ack interrupts, disable EFC interrupt */
6514 intel_uncore_write(uncore,
6516 intel_uncore_read(uncore, MEMINTREN) &
6517 ~MEMINT_EVAL_CHG_EN);
6518 intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
6519 intel_uncore_write(uncore,
6521 intel_uncore_read(uncore, DEIER) & ~DE_PCU_EVENT);
6522 intel_uncore_write(uncore, DEIIR, DE_PCU_EVENT);
6523 intel_uncore_write(uncore,
6525 intel_uncore_read(uncore, DEIMR) | DE_PCU_EVENT);
6527 /* Go back to the starting frequency */
6528 ironlake_set_drps(i915, i915->ips.fstart);
6530 rgvswctl |= MEMCTL_CMD_STS;
6531 intel_uncore_write(uncore, MEMSWCTL, rgvswctl);
6534 spin_unlock_irq(&mchdev_lock);
6537 /* There's a funny hw issue where the hw returns all 0 when reading from
6538 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
6539 * ourselves, instead of doing a rmw cycle (which might result in us clearing
6540 * all limits and the gpu stuck at whatever frequency it is at atm).
6542 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
6544 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6547 /* Only set the down limit when we've reached the lowest level to avoid
6548 * getting more interrupts, otherwise leave this clear. This prevents a
6549 * race in the hw when coming out of rc6: There's a tiny window where
6550 * the hw runs at the minimal clock before selecting the desired
6551 * frequency, if the down threshold expires in that window we will not
6552 * receive a down interrupt. */
6553 if (INTEL_GEN(dev_priv) >= 9) {
6554 limits = (rps->max_freq_softlimit) << 23;
6555 if (val <= rps->min_freq_softlimit)
6556 limits |= (rps->min_freq_softlimit) << 14;
6558 limits = rps->max_freq_softlimit << 24;
6559 if (val <= rps->min_freq_softlimit)
6560 limits |= rps->min_freq_softlimit << 16;
6566 static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
6568 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6569 u32 threshold_up = 0, threshold_down = 0; /* in % */
6570 u32 ei_up = 0, ei_down = 0;
6572 lockdep_assert_held(&rps->power.mutex);
6574 if (new_power == rps->power.mode)
6577 /* Note the units here are not exactly 1us, but 1280ns. */
6578 switch (new_power) {
6580 /* Upclock if more than 95% busy over 16ms */
6584 /* Downclock if less than 85% busy over 32ms */
6586 threshold_down = 85;
6590 /* Upclock if more than 90% busy over 13ms */
6594 /* Downclock if less than 75% busy over 32ms */
6596 threshold_down = 75;
6600 /* Upclock if more than 85% busy over 10ms */
6604 /* Downclock if less than 60% busy over 32ms */
6606 threshold_down = 60;
6610 /* When byt can survive without system hang with dynamic
6611 * sw freq adjustments, this restriction can be lifted.
6613 if (IS_VALLEYVIEW(dev_priv))
6616 I915_WRITE(GEN6_RP_UP_EI,
6617 GT_INTERVAL_FROM_US(dev_priv, ei_up));
6618 I915_WRITE(GEN6_RP_UP_THRESHOLD,
6619 GT_INTERVAL_FROM_US(dev_priv,
6620 ei_up * threshold_up / 100));
6622 I915_WRITE(GEN6_RP_DOWN_EI,
6623 GT_INTERVAL_FROM_US(dev_priv, ei_down));
6624 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
6625 GT_INTERVAL_FROM_US(dev_priv,
6626 ei_down * threshold_down / 100));
6628 I915_WRITE(GEN6_RP_CONTROL,
6629 (INTEL_GEN(dev_priv) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
6630 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6631 GEN6_RP_MEDIA_IS_GFX |
6633 GEN6_RP_UP_BUSY_AVG |
6634 GEN6_RP_DOWN_IDLE_AVG);
6637 rps->power.mode = new_power;
6638 rps->power.up_threshold = threshold_up;
6639 rps->power.down_threshold = threshold_down;
6642 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
6644 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6647 new_power = rps->power.mode;
6648 switch (rps->power.mode) {
6650 if (val > rps->efficient_freq + 1 &&
6651 val > rps->cur_freq)
6652 new_power = BETWEEN;
6656 if (val <= rps->efficient_freq &&
6657 val < rps->cur_freq)
6658 new_power = LOW_POWER;
6659 else if (val >= rps->rp0_freq &&
6660 val > rps->cur_freq)
6661 new_power = HIGH_POWER;
6665 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
6666 val < rps->cur_freq)
6667 new_power = BETWEEN;
6670 /* Max/min bins are special */
6671 if (val <= rps->min_freq_softlimit)
6672 new_power = LOW_POWER;
6673 if (val >= rps->max_freq_softlimit)
6674 new_power = HIGH_POWER;
6676 mutex_lock(&rps->power.mutex);
6677 if (rps->power.interactive)
6678 new_power = HIGH_POWER;
6679 rps_set_power(dev_priv, new_power);
6680 mutex_unlock(&rps->power.mutex);
6683 void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive)
6685 struct intel_rps *rps = &i915->gt_pm.rps;
6687 if (INTEL_GEN(i915) < 6)
6690 mutex_lock(&rps->power.mutex);
6692 if (!rps->power.interactive++ && READ_ONCE(i915->gt.awake))
6693 rps_set_power(i915, HIGH_POWER);
6695 GEM_BUG_ON(!rps->power.interactive);
6696 rps->power.interactive--;
6698 mutex_unlock(&rps->power.mutex);
6701 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
6703 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6706 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
6707 if (val > rps->min_freq_softlimit)
6708 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
6709 if (val < rps->max_freq_softlimit)
6710 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
6712 mask &= dev_priv->pm_rps_events;
6714 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
6717 /* gen6_set_rps is called to update the frequency request, but should also be
6718 * called when the range (min_delay and max_delay) is modified so that we can
6719 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
6720 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
6722 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6724 /* min/max delay may still have been modified so be sure to
6725 * write the limits value.
6727 if (val != rps->cur_freq) {
6728 gen6_set_rps_thresholds(dev_priv, val);
6730 if (INTEL_GEN(dev_priv) >= 9)
6731 I915_WRITE(GEN6_RPNSWREQ,
6732 GEN9_FREQUENCY(val));
6733 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6734 I915_WRITE(GEN6_RPNSWREQ,
6735 HSW_FREQUENCY(val));
6737 I915_WRITE(GEN6_RPNSWREQ,
6738 GEN6_FREQUENCY(val) |
6740 GEN6_AGGRESSIVE_TURBO);
6743 /* Make sure we continue to get interrupts
6744 * until we hit the minimum or maximum frequencies.
6746 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
6747 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6749 rps->cur_freq = val;
6750 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6755 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
6759 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
6760 "Odd GPU freq value\n"))
6763 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6765 if (val != dev_priv->gt_pm.rps.cur_freq) {
6766 vlv_punit_get(dev_priv);
6767 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
6768 vlv_punit_put(dev_priv);
6772 gen6_set_rps_thresholds(dev_priv, val);
6775 dev_priv->gt_pm.rps.cur_freq = val;
6776 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6781 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6783 * * If Gfx is Idle, then
6784 * 1. Forcewake Media well.
6785 * 2. Request idle freq.
6786 * 3. Release Forcewake of Media well.
6788 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
6790 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6791 u32 val = rps->idle_freq;
6794 if (rps->cur_freq <= val)
6797 /* The punit delays the write of the frequency and voltage until it
6798 * determines the GPU is awake. During normal usage we don't want to
6799 * waste power changing the frequency if the GPU is sleeping (rc6).
6800 * However, the GPU and driver is now idle and we do not want to delay
6801 * switching to minimum voltage (reducing power whilst idle) as we do
6802 * not expect to be woken in the near future and so must flush the
6803 * change by waking the device.
6805 * We choose to take the media powerwell (either would do to trick the
6806 * punit into committing the voltage change) as that takes a lot less
6807 * power than the render powerwell.
6809 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_MEDIA);
6810 err = valleyview_set_rps(dev_priv, val);
6811 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_MEDIA);
6814 DRM_ERROR("Failed to set RPS for idle\n");
6817 void gen6_rps_busy(struct drm_i915_private *dev_priv)
6819 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6821 mutex_lock(&rps->lock);
6825 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
6826 gen6_rps_reset_ei(dev_priv);
6827 I915_WRITE(GEN6_PMINTRMSK,
6828 gen6_rps_pm_mask(dev_priv, rps->cur_freq));
6830 gen6_enable_rps_interrupts(dev_priv);
6832 /* Use the user's desired frequency as a guide, but for better
6833 * performance, jump directly to RPe as our starting frequency.
6835 freq = max(rps->cur_freq,
6836 rps->efficient_freq);
6838 if (intel_set_rps(dev_priv,
6840 rps->min_freq_softlimit,
6841 rps->max_freq_softlimit)))
6842 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6844 mutex_unlock(&rps->lock);
6847 void gen6_rps_idle(struct drm_i915_private *dev_priv)
6849 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6851 /* Flush our bottom-half so that it does not race with us
6852 * setting the idle frequency and so that it is bounded by
6853 * our rpm wakeref. And then disable the interrupts to stop any
6854 * futher RPS reclocking whilst we are asleep.
6856 gen6_disable_rps_interrupts(dev_priv);
6858 mutex_lock(&rps->lock);
6860 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6861 vlv_set_rps_idle(dev_priv);
6863 gen6_set_rps(dev_priv, rps->idle_freq);
6865 I915_WRITE(GEN6_PMINTRMSK,
6866 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
6868 mutex_unlock(&rps->lock);
6871 void gen6_rps_boost(struct i915_request *rq)
6873 struct intel_rps *rps = &rq->i915->gt_pm.rps;
6874 unsigned long flags;
6877 /* This is intentionally racy! We peek at the state here, then
6878 * validate inside the RPS worker.
6883 if (i915_request_signaled(rq))
6886 /* Serializes with i915_request_retire() */
6888 spin_lock_irqsave(&rq->lock, flags);
6889 if (!i915_request_has_waitboost(rq) &&
6890 !dma_fence_is_signaled_locked(&rq->fence)) {
6891 boost = !atomic_fetch_inc(&rps->num_waiters);
6892 rq->flags |= I915_REQUEST_WAITBOOST;
6894 spin_unlock_irqrestore(&rq->lock, flags);
6898 if (READ_ONCE(rps->cur_freq) < rps->boost_freq)
6899 schedule_work(&rps->work);
6901 atomic_inc(&rps->boosts);
6904 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
6906 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6909 lockdep_assert_held(&rps->lock);
6910 GEM_BUG_ON(val > rps->max_freq);
6911 GEM_BUG_ON(val < rps->min_freq);
6913 if (!rps->enabled) {
6914 rps->cur_freq = val;
6918 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6919 err = valleyview_set_rps(dev_priv, val);
6921 err = gen6_set_rps(dev_priv, val);
6926 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
6928 I915_WRITE(GEN6_RC_CONTROL, 0);
6929 I915_WRITE(GEN9_PG_ENABLE, 0);
6932 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
6934 I915_WRITE(GEN6_RP_CONTROL, 0);
6937 static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
6939 I915_WRITE(GEN6_RC_CONTROL, 0);
6942 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
6944 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6945 I915_WRITE(GEN6_RP_CONTROL, 0);
6948 static void cherryview_disable_rc6(struct drm_i915_private *dev_priv)
6950 I915_WRITE(GEN6_RC_CONTROL, 0);
6953 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
6955 I915_WRITE(GEN6_RP_CONTROL, 0);
6958 static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
6960 /* We're doing forcewake before Disabling RC6,
6961 * This what the BIOS expects when going into suspend */
6962 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
6964 I915_WRITE(GEN6_RC_CONTROL, 0);
6966 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
6969 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
6971 I915_WRITE(GEN6_RP_CONTROL, 0);
6974 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
6976 bool enable_rc6 = true;
6977 unsigned long rc6_ctx_base;
6981 rc_ctl = I915_READ(GEN6_RC_CONTROL);
6982 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
6983 RC_SW_TARGET_STATE_SHIFT;
6984 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6985 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6986 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
6987 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
6990 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
6991 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6996 * The exact context size is not known for BXT, so assume a page size
6999 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
7000 if (!((rc6_ctx_base >= dev_priv->dsm_reserved.start) &&
7001 (rc6_ctx_base + PAGE_SIZE < dev_priv->dsm_reserved.end))) {
7002 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
7006 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
7007 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
7008 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
7009 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
7010 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
7014 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
7015 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
7016 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
7017 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
7021 if (!I915_READ(GEN6_GFXPAUSE)) {
7022 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
7026 if (!I915_READ(GEN8_MISC_CTRL0)) {
7027 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
7034 static bool sanitize_rc6(struct drm_i915_private *i915)
7036 struct intel_device_info *info = mkwrite_device_info(i915);
7038 /* Powersaving is controlled by the host when inside a VM */
7039 if (intel_vgpu_active(i915)) {
7041 info->has_rps = false;
7044 if (info->has_rc6 &&
7045 IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
7046 DRM_INFO("RC6 disabled by BIOS\n");
7051 * We assume that we do not have any deep rc6 levels if we don't have
7052 * have the previous rc6 level supported, i.e. we use HAS_RC6()
7053 * as the initial coarse check for rc6 in general, moving on to
7054 * progressively finer/deeper levels.
7056 if (!info->has_rc6 && info->has_rc6p)
7059 return info->has_rc6;
7062 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
7064 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7066 /* All of these values are in units of 50MHz */
7068 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
7069 if (IS_GEN9_LP(dev_priv)) {
7070 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
7071 rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
7072 rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
7073 rps->min_freq = (rp_state_cap >> 0) & 0xff;
7075 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7076 rps->rp0_freq = (rp_state_cap >> 0) & 0xff;
7077 rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
7078 rps->min_freq = (rp_state_cap >> 16) & 0xff;
7080 /* hw_max = RP0 until we check for overclocking */
7081 rps->max_freq = rps->rp0_freq;
7083 rps->efficient_freq = rps->rp1_freq;
7084 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
7085 IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7086 u32 ddcc_status = 0;
7088 if (sandybridge_pcode_read(dev_priv,
7089 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
7090 &ddcc_status, NULL) == 0)
7091 rps->efficient_freq =
7093 ((ddcc_status >> 8) & 0xff),
7098 if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7099 /* Store the frequency values in 16.66 MHZ units, which is
7100 * the natural hardware unit for SKL
7102 rps->rp0_freq *= GEN9_FREQ_SCALER;
7103 rps->rp1_freq *= GEN9_FREQ_SCALER;
7104 rps->min_freq *= GEN9_FREQ_SCALER;
7105 rps->max_freq *= GEN9_FREQ_SCALER;
7106 rps->efficient_freq *= GEN9_FREQ_SCALER;
7110 static void reset_rps(struct drm_i915_private *dev_priv,
7111 int (*set)(struct drm_i915_private *, u8))
7113 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7114 u8 freq = rps->cur_freq;
7117 rps->power.mode = -1;
7120 if (set(dev_priv, freq))
7121 DRM_ERROR("Failed to reset RPS to initial values\n");
7124 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
7125 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
7127 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7129 /* Program defaults and thresholds for RPS */
7130 if (IS_GEN(dev_priv, 9))
7131 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7132 GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq));
7134 /* 1 second timeout*/
7135 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
7136 GT_INTERVAL_FROM_US(dev_priv, 1000000));
7138 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
7140 /* Leaning on the below call to gen6_set_rps to program/setup the
7141 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
7142 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
7143 reset_rps(dev_priv, gen6_set_rps);
7145 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7148 static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
7150 struct intel_engine_cs *engine;
7151 enum intel_engine_id id;
7153 /* 1a: Software RC state - RC0 */
7154 I915_WRITE(GEN6_RC_STATE, 0);
7157 * 1b: Get forcewake during program sequence. Although the driver
7158 * hasn't enabled a state yet where we need forcewake, BIOS may have.
7160 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7162 /* 2a: Disable RC states. */
7163 I915_WRITE(GEN6_RC_CONTROL, 0);
7165 /* 2b: Program RC6 thresholds.*/
7166 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
7167 I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
7169 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7170 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7171 for_each_engine(engine, dev_priv, id)
7172 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7174 if (HAS_GT_UC(dev_priv))
7175 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
7177 I915_WRITE(GEN6_RC_SLEEP, 0);
7179 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
7182 * 2c: Program Coarse Power Gating Policies.
7184 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
7185 * use instead is a more conservative estimate for the maximum time
7186 * it takes us to service a CS interrupt and submit a new ELSP - that
7187 * is the time which the GPU is idle waiting for the CPU to select the
7188 * next request to execute. If the idle hysteresis is less than that
7189 * interrupt service latency, the hardware will automatically gate
7190 * the power well and we will then incur the wake up cost on top of
7191 * the service latency. A similar guide from plane_state is that we
7192 * do not want the enable hysteresis to less than the wakeup latency.
7194 * igt/gem_exec_nop/sequential provides a rough estimate for the
7195 * service latency, and puts it around 10us for Broadwell (and other
7196 * big core) and around 40us for Broxton (and other low power cores).
7197 * [Note that for legacy ringbuffer submission, this is less than 1us!]
7198 * However, the wakeup latency on Broxton is closer to 100us. To be
7199 * conservative, we have to factor in a context switch on top (due
7202 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
7203 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
7205 /* 3a: Enable RC6 */
7206 I915_WRITE(GEN6_RC_CONTROL,
7207 GEN6_RC_CTL_HW_ENABLE |
7208 GEN6_RC_CTL_RC6_ENABLE |
7209 GEN6_RC_CTL_EI_MODE(1));
7211 /* 3b: Enable Coarse Power Gating only when RC6 is enabled. */
7212 I915_WRITE(GEN9_PG_ENABLE,
7213 GEN9_RENDER_PG_ENABLE |
7214 GEN9_MEDIA_PG_ENABLE |
7215 GEN11_MEDIA_SAMPLER_PG_ENABLE);
7217 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7220 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
7222 struct intel_engine_cs *engine;
7223 enum intel_engine_id id;
7226 /* 1a: Software RC state - RC0 */
7227 I915_WRITE(GEN6_RC_STATE, 0);
7229 /* 1b: Get forcewake during program sequence. Although the driver
7230 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7231 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7233 /* 2a: Disable RC states. */
7234 I915_WRITE(GEN6_RC_CONTROL, 0);
7236 /* 2b: Program RC6 thresholds.*/
7237 if (INTEL_GEN(dev_priv) >= 10) {
7238 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
7239 I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
7240 } else if (IS_SKYLAKE(dev_priv)) {
7242 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
7243 * when CPG is enabled
7245 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
7247 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
7250 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7251 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7252 for_each_engine(engine, dev_priv, id)
7253 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7255 if (HAS_GT_UC(dev_priv))
7256 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
7258 I915_WRITE(GEN6_RC_SLEEP, 0);
7261 * 2c: Program Coarse Power Gating Policies.
7263 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
7264 * use instead is a more conservative estimate for the maximum time
7265 * it takes us to service a CS interrupt and submit a new ELSP - that
7266 * is the time which the GPU is idle waiting for the CPU to select the
7267 * next request to execute. If the idle hysteresis is less than that
7268 * interrupt service latency, the hardware will automatically gate
7269 * the power well and we will then incur the wake up cost on top of
7270 * the service latency. A similar guide from plane_state is that we
7271 * do not want the enable hysteresis to less than the wakeup latency.
7273 * igt/gem_exec_nop/sequential provides a rough estimate for the
7274 * service latency, and puts it around 10us for Broadwell (and other
7275 * big core) and around 40us for Broxton (and other low power cores).
7276 * [Note that for legacy ringbuffer submission, this is less than 1us!]
7277 * However, the wakeup latency on Broxton is closer to 100us. To be
7278 * conservative, we have to factor in a context switch on top (due
7281 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
7282 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
7284 /* 3a: Enable RC6 */
7285 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
7287 /* WaRsUseTimeoutMode:cnl (pre-prod) */
7288 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0))
7289 rc6_mode = GEN7_RC_CTL_TO_MODE;
7291 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
7293 I915_WRITE(GEN6_RC_CONTROL,
7294 GEN6_RC_CTL_HW_ENABLE |
7295 GEN6_RC_CTL_RC6_ENABLE |
7299 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
7300 * WaRsDisableCoarsePowerGating:skl,cnl - Render/Media PG need to be disabled with RC6.
7302 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
7303 I915_WRITE(GEN9_PG_ENABLE, 0);
7305 I915_WRITE(GEN9_PG_ENABLE,
7306 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
7308 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7311 static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
7313 struct intel_engine_cs *engine;
7314 enum intel_engine_id id;
7316 /* 1a: Software RC state - RC0 */
7317 I915_WRITE(GEN6_RC_STATE, 0);
7319 /* 1b: Get forcewake during program sequence. Although the driver
7320 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7321 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7323 /* 2a: Disable RC states. */
7324 I915_WRITE(GEN6_RC_CONTROL, 0);
7326 /* 2b: Program RC6 thresholds.*/
7327 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7328 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7329 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7330 for_each_engine(engine, dev_priv, id)
7331 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7332 I915_WRITE(GEN6_RC_SLEEP, 0);
7333 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
7337 I915_WRITE(GEN6_RC_CONTROL,
7338 GEN6_RC_CTL_HW_ENABLE |
7339 GEN7_RC_CTL_TO_MODE |
7340 GEN6_RC_CTL_RC6_ENABLE);
7342 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7345 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
7347 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7349 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7351 /* 1 Program defaults and thresholds for RPS*/
7352 I915_WRITE(GEN6_RPNSWREQ,
7353 HSW_FREQUENCY(rps->rp1_freq));
7354 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7355 HSW_FREQUENCY(rps->rp1_freq));
7356 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
7357 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
7359 /* Docs recommend 900MHz, and 300 MHz respectively */
7360 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7361 rps->max_freq_softlimit << 24 |
7362 rps->min_freq_softlimit << 16);
7364 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
7365 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
7366 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
7367 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
7369 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7372 I915_WRITE(GEN6_RP_CONTROL,
7373 GEN6_RP_MEDIA_TURBO |
7374 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7375 GEN6_RP_MEDIA_IS_GFX |
7377 GEN6_RP_UP_BUSY_AVG |
7378 GEN6_RP_DOWN_IDLE_AVG);
7380 reset_rps(dev_priv, gen6_set_rps);
7382 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7385 static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
7387 struct intel_engine_cs *engine;
7388 enum intel_engine_id id;
7389 u32 rc6vids, rc6_mask;
7393 I915_WRITE(GEN6_RC_STATE, 0);
7395 /* Clear the DBG now so we don't confuse earlier errors */
7396 gtfifodbg = I915_READ(GTFIFODBG);
7398 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
7399 I915_WRITE(GTFIFODBG, gtfifodbg);
7402 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7404 /* disable the counters and set deterministic thresholds */
7405 I915_WRITE(GEN6_RC_CONTROL, 0);
7407 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7408 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7409 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7410 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7411 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7413 for_each_engine(engine, dev_priv, id)
7414 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7416 I915_WRITE(GEN6_RC_SLEEP, 0);
7417 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7418 if (IS_IVYBRIDGE(dev_priv))
7419 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
7421 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7422 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
7423 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7425 /* We don't use those on Haswell */
7426 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
7427 if (HAS_RC6p(dev_priv))
7428 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
7429 if (HAS_RC6pp(dev_priv))
7430 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
7431 I915_WRITE(GEN6_RC_CONTROL,
7433 GEN6_RC_CTL_EI_MODE(1) |
7434 GEN6_RC_CTL_HW_ENABLE);
7437 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
7439 if (IS_GEN(dev_priv, 6) && ret) {
7440 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
7441 } else if (IS_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
7442 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
7443 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
7444 rc6vids &= 0xffff00;
7445 rc6vids |= GEN6_ENCODE_RC6_VID(450);
7446 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
7448 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
7451 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7454 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
7456 /* Here begins a magic sequence of register writes to enable
7457 * auto-downclocking.
7459 * Perhaps there might be some value in exposing these to
7462 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7464 /* Power down if completely idle for over 50ms */
7465 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
7466 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7468 reset_rps(dev_priv, gen6_set_rps);
7470 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7473 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7475 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7476 const int min_freq = 15;
7477 const int scaling_factor = 180;
7478 unsigned int gpu_freq;
7479 unsigned int max_ia_freq, min_ring_freq;
7480 unsigned int max_gpu_freq, min_gpu_freq;
7481 struct cpufreq_policy *policy;
7483 lockdep_assert_held(&rps->lock);
7485 if (rps->max_freq <= rps->min_freq)
7488 policy = cpufreq_cpu_get(0);
7490 max_ia_freq = policy->cpuinfo.max_freq;
7491 cpufreq_cpu_put(policy);
7494 * Default to measured freq if none found, PCU will ensure we
7497 max_ia_freq = tsc_khz;
7500 /* Convert from kHz to MHz */
7501 max_ia_freq /= 1000;
7503 min_ring_freq = I915_READ(DCLK) & 0xf;
7504 /* convert DDR frequency from units of 266.6MHz to bandwidth */
7505 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
7507 min_gpu_freq = rps->min_freq;
7508 max_gpu_freq = rps->max_freq;
7509 if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7510 /* Convert GT frequency to 50 HZ units */
7511 min_gpu_freq /= GEN9_FREQ_SCALER;
7512 max_gpu_freq /= GEN9_FREQ_SCALER;
7516 * For each potential GPU frequency, load a ring frequency we'd like
7517 * to use for memory access. We do this by specifying the IA frequency
7518 * the PCU should use as a reference to determine the ring frequency.
7520 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
7521 const int diff = max_gpu_freq - gpu_freq;
7522 unsigned int ia_freq = 0, ring_freq = 0;
7524 if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7526 * ring_freq = 2 * GT. ring_freq is in 100MHz units
7527 * No floor required for ring frequency on SKL.
7529 ring_freq = gpu_freq;
7530 } else if (INTEL_GEN(dev_priv) >= 8) {
7531 /* max(2 * GT, DDR). NB: GT is 50MHz units */
7532 ring_freq = max(min_ring_freq, gpu_freq);
7533 } else if (IS_HASWELL(dev_priv)) {
7534 ring_freq = mult_frac(gpu_freq, 5, 4);
7535 ring_freq = max(min_ring_freq, ring_freq);
7536 /* leave ia_freq as the default, chosen by cpufreq */
7538 /* On older processors, there is no separate ring
7539 * clock domain, so in order to boost the bandwidth
7540 * of the ring, we need to upclock the CPU (ia_freq).
7542 * For GPU frequencies less than 750MHz,
7543 * just use the lowest ring freq.
7545 if (gpu_freq < min_freq)
7548 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7549 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7552 sandybridge_pcode_write(dev_priv,
7553 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
7554 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
7555 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
7560 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
7564 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
7566 switch (RUNTIME_INFO(dev_priv)->sseu.eu_total) {
7568 /* (2 * 4) config */
7569 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
7572 /* (2 * 6) config */
7573 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
7576 /* (2 * 8) config */
7578 /* Setting (2 * 8) Min RP0 for any other combination */
7579 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
7583 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
7588 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
7592 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
7593 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
7598 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
7602 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
7603 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
7608 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
7612 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
7613 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
7614 FB_GFX_FREQ_FUSE_MASK);
7619 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
7623 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
7625 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
7630 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
7634 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
7636 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
7638 rp0 = min_t(u32, rp0, 0xea);
7643 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
7647 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
7648 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
7649 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
7650 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
7655 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
7659 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
7661 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
7662 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
7663 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
7664 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
7665 * to make sure it matches what Punit accepts.
7667 return max_t(u32, val, 0xc0);
7670 /* Check that the pctx buffer wasn't move under us. */
7671 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
7673 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7675 WARN_ON(pctx_addr != dev_priv->dsm.start +
7676 dev_priv->vlv_pctx->stolen->start);
7680 /* Check that the pcbr address is not empty. */
7681 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
7683 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7685 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
7688 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
7690 resource_size_t pctx_paddr, paddr;
7691 resource_size_t pctx_size = 32*1024;
7694 pcbr = I915_READ(VLV_PCBR);
7695 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
7696 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7697 paddr = dev_priv->dsm.end + 1 - pctx_size;
7698 GEM_BUG_ON(paddr > U32_MAX);
7700 pctx_paddr = (paddr & (~4095));
7701 I915_WRITE(VLV_PCBR, pctx_paddr);
7704 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7707 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
7709 struct drm_i915_gem_object *pctx;
7710 resource_size_t pctx_paddr;
7711 resource_size_t pctx_size = 24*1024;
7714 pcbr = I915_READ(VLV_PCBR);
7716 /* BIOS set it up already, grab the pre-alloc'd space */
7717 resource_size_t pcbr_offset;
7719 pcbr_offset = (pcbr & (~4095)) - dev_priv->dsm.start;
7720 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
7722 I915_GTT_OFFSET_NONE,
7727 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7730 * From the Gunit register HAS:
7731 * The Gfx driver is expected to program this register and ensure
7732 * proper allocation within Gfx stolen memory. For example, this
7733 * register should be programmed such than the PCBR range does not
7734 * overlap with other ranges, such as the frame buffer, protected
7735 * memory, or any other relevant ranges.
7737 pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
7739 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
7743 GEM_BUG_ON(range_overflows_t(u64,
7744 dev_priv->dsm.start,
7745 pctx->stolen->start,
7747 pctx_paddr = dev_priv->dsm.start + pctx->stolen->start;
7748 I915_WRITE(VLV_PCBR, pctx_paddr);
7751 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7752 dev_priv->vlv_pctx = pctx;
7755 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
7757 struct drm_i915_gem_object *pctx;
7759 pctx = fetch_and_zero(&dev_priv->vlv_pctx);
7761 i915_gem_object_put(pctx);
7764 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
7766 dev_priv->gt_pm.rps.gpll_ref_freq =
7767 vlv_get_cck_clock(dev_priv, "GPLL ref",
7768 CCK_GPLL_CLOCK_CONTROL,
7769 dev_priv->czclk_freq);
7771 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
7772 dev_priv->gt_pm.rps.gpll_ref_freq);
7775 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
7777 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7780 valleyview_setup_pctx(dev_priv);
7782 vlv_iosf_sb_get(dev_priv,
7783 BIT(VLV_IOSF_SB_PUNIT) |
7784 BIT(VLV_IOSF_SB_NC) |
7785 BIT(VLV_IOSF_SB_CCK));
7787 vlv_init_gpll_ref_freq(dev_priv);
7789 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7790 switch ((val >> 6) & 3) {
7793 dev_priv->mem_freq = 800;
7796 dev_priv->mem_freq = 1066;
7799 dev_priv->mem_freq = 1333;
7802 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7804 rps->max_freq = valleyview_rps_max_freq(dev_priv);
7805 rps->rp0_freq = rps->max_freq;
7806 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7807 intel_gpu_freq(dev_priv, rps->max_freq),
7810 rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv);
7811 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7812 intel_gpu_freq(dev_priv, rps->efficient_freq),
7813 rps->efficient_freq);
7815 rps->rp1_freq = valleyview_rps_guar_freq(dev_priv);
7816 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7817 intel_gpu_freq(dev_priv, rps->rp1_freq),
7820 rps->min_freq = valleyview_rps_min_freq(dev_priv);
7821 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7822 intel_gpu_freq(dev_priv, rps->min_freq),
7825 vlv_iosf_sb_put(dev_priv,
7826 BIT(VLV_IOSF_SB_PUNIT) |
7827 BIT(VLV_IOSF_SB_NC) |
7828 BIT(VLV_IOSF_SB_CCK));
7831 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
7833 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7836 cherryview_setup_pctx(dev_priv);
7838 vlv_iosf_sb_get(dev_priv,
7839 BIT(VLV_IOSF_SB_PUNIT) |
7840 BIT(VLV_IOSF_SB_NC) |
7841 BIT(VLV_IOSF_SB_CCK));
7843 vlv_init_gpll_ref_freq(dev_priv);
7845 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
7847 switch ((val >> 2) & 0x7) {
7849 dev_priv->mem_freq = 2000;
7852 dev_priv->mem_freq = 1600;
7855 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7857 rps->max_freq = cherryview_rps_max_freq(dev_priv);
7858 rps->rp0_freq = rps->max_freq;
7859 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7860 intel_gpu_freq(dev_priv, rps->max_freq),
7863 rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv);
7864 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7865 intel_gpu_freq(dev_priv, rps->efficient_freq),
7866 rps->efficient_freq);
7868 rps->rp1_freq = cherryview_rps_guar_freq(dev_priv);
7869 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7870 intel_gpu_freq(dev_priv, rps->rp1_freq),
7873 rps->min_freq = cherryview_rps_min_freq(dev_priv);
7874 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7875 intel_gpu_freq(dev_priv, rps->min_freq),
7878 vlv_iosf_sb_put(dev_priv,
7879 BIT(VLV_IOSF_SB_PUNIT) |
7880 BIT(VLV_IOSF_SB_NC) |
7881 BIT(VLV_IOSF_SB_CCK));
7883 WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
7885 "Odd GPU freq values\n");
7888 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7890 valleyview_cleanup_pctx(dev_priv);
7893 static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
7895 struct intel_engine_cs *engine;
7896 enum intel_engine_id id;
7897 u32 gtfifodbg, rc6_mode, pcbr;
7899 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
7900 GT_FIFO_FREE_ENTRIES_CHV);
7902 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7904 I915_WRITE(GTFIFODBG, gtfifodbg);
7907 cherryview_check_pctx(dev_priv);
7909 /* 1a & 1b: Get forcewake during program sequence. Although the driver
7910 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7911 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7913 /* Disable RC states. */
7914 I915_WRITE(GEN6_RC_CONTROL, 0);
7916 /* 2a: Program RC6 thresholds.*/
7917 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7918 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7919 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7921 for_each_engine(engine, dev_priv, id)
7922 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7923 I915_WRITE(GEN6_RC_SLEEP, 0);
7925 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7926 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
7928 /* Allows RC6 residency counter to work */
7929 I915_WRITE(VLV_COUNTER_CONTROL,
7930 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7931 VLV_MEDIA_RC6_COUNT_EN |
7932 VLV_RENDER_RC6_COUNT_EN));
7934 /* For now we assume BIOS is allocating and populating the PCBR */
7935 pcbr = I915_READ(VLV_PCBR);
7939 if (pcbr >> VLV_PCBR_ADDR_SHIFT)
7940 rc6_mode = GEN7_RC_CTL_TO_MODE;
7941 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7943 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7946 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
7950 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7952 /* 1: Program defaults and thresholds for RPS*/
7953 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7954 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7955 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7956 I915_WRITE(GEN6_RP_UP_EI, 66000);
7957 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7959 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7962 I915_WRITE(GEN6_RP_CONTROL,
7963 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7964 GEN6_RP_MEDIA_IS_GFX |
7966 GEN6_RP_UP_BUSY_AVG |
7967 GEN6_RP_DOWN_IDLE_AVG);
7969 /* Setting Fixed Bias */
7970 vlv_punit_get(dev_priv);
7972 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50;
7973 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7975 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7977 vlv_punit_put(dev_priv);
7979 /* RPS code assumes GPLL is used */
7980 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7982 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7983 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7985 reset_rps(dev_priv, valleyview_set_rps);
7987 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7990 static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
7992 struct intel_engine_cs *engine;
7993 enum intel_engine_id id;
7996 valleyview_check_pctx(dev_priv);
7998 gtfifodbg = I915_READ(GTFIFODBG);
8000 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
8002 I915_WRITE(GTFIFODBG, gtfifodbg);
8005 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
8007 /* Disable RC states. */
8008 I915_WRITE(GEN6_RC_CONTROL, 0);
8010 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
8011 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8012 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8014 for_each_engine(engine, dev_priv, id)
8015 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
8017 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
8019 /* Allows RC6 residency counter to work */
8020 I915_WRITE(VLV_COUNTER_CONTROL,
8021 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
8022 VLV_MEDIA_RC0_COUNT_EN |
8023 VLV_RENDER_RC0_COUNT_EN |
8024 VLV_MEDIA_RC6_COUNT_EN |
8025 VLV_RENDER_RC6_COUNT_EN));
8027 I915_WRITE(GEN6_RC_CONTROL,
8028 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL);
8030 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
8033 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
8037 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
8039 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8040 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
8041 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
8042 I915_WRITE(GEN6_RP_UP_EI, 66000);
8043 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
8045 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8047 I915_WRITE(GEN6_RP_CONTROL,
8048 GEN6_RP_MEDIA_TURBO |
8049 GEN6_RP_MEDIA_HW_NORMAL_MODE |
8050 GEN6_RP_MEDIA_IS_GFX |
8052 GEN6_RP_UP_BUSY_AVG |
8053 GEN6_RP_DOWN_IDLE_CONT);
8055 vlv_punit_get(dev_priv);
8057 /* Setting Fixed Bias */
8058 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875;
8059 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
8061 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
8063 vlv_punit_put(dev_priv);
8065 /* RPS code assumes GPLL is used */
8066 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
8068 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
8069 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
8071 reset_rps(dev_priv, valleyview_set_rps);
8073 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
8076 static unsigned long intel_pxfreq(u32 vidfreq)
8079 int div = (vidfreq & 0x3f0000) >> 16;
8080 int post = (vidfreq & 0x3000) >> 12;
8081 int pre = (vidfreq & 0x7);
8086 freq = ((div * 133333) / ((1<<post) * pre));
8091 static const struct cparams {
8097 { 1, 1333, 301, 28664 },
8098 { 1, 1066, 294, 24460 },
8099 { 1, 800, 294, 25192 },
8100 { 0, 1333, 276, 27605 },
8101 { 0, 1066, 276, 27605 },
8102 { 0, 800, 231, 23784 },
8105 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
8107 u64 total_count, diff, ret;
8108 u32 count1, count2, count3, m = 0, c = 0;
8109 unsigned long now = jiffies_to_msecs(jiffies), diff1;
8112 lockdep_assert_held(&mchdev_lock);
8114 diff1 = now - dev_priv->ips.last_time1;
8116 /* Prevent division-by-zero if we are asking too fast.
8117 * Also, we don't get interesting results if we are polling
8118 * faster than once in 10ms, so just return the saved value
8122 return dev_priv->ips.chipset_power;
8124 count1 = I915_READ(DMIEC);
8125 count2 = I915_READ(DDREC);
8126 count3 = I915_READ(CSIEC);
8128 total_count = count1 + count2 + count3;
8130 /* FIXME: handle per-counter overflow */
8131 if (total_count < dev_priv->ips.last_count1) {
8132 diff = ~0UL - dev_priv->ips.last_count1;
8133 diff += total_count;
8135 diff = total_count - dev_priv->ips.last_count1;
8138 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
8139 if (cparams[i].i == dev_priv->ips.c_m &&
8140 cparams[i].t == dev_priv->ips.r_t) {
8147 diff = div_u64(diff, diff1);
8148 ret = ((m * diff) + c);
8149 ret = div_u64(ret, 10);
8151 dev_priv->ips.last_count1 = total_count;
8152 dev_priv->ips.last_time1 = now;
8154 dev_priv->ips.chipset_power = ret;
8159 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
8161 intel_wakeref_t wakeref;
8162 unsigned long val = 0;
8164 if (!IS_GEN(dev_priv, 5))
8167 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
8168 spin_lock_irq(&mchdev_lock);
8169 val = __i915_chipset_val(dev_priv);
8170 spin_unlock_irq(&mchdev_lock);
8176 unsigned long i915_mch_val(struct drm_i915_private *i915)
8178 unsigned long m, x, b;
8181 tsfs = intel_uncore_read(&i915->uncore, TSFS);
8183 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
8184 x = intel_uncore_read8(&i915->uncore, TR1);
8186 b = tsfs & TSFS_INTR_MASK;
8188 return ((m * x) / 127) - b;
8191 static int _pxvid_to_vd(u8 pxvid)
8196 if (pxvid >= 8 && pxvid < 31)
8199 return (pxvid + 2) * 125;
8202 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
8204 const int vd = _pxvid_to_vd(pxvid);
8205 const int vm = vd - 1125;
8207 if (INTEL_INFO(dev_priv)->is_mobile)
8208 return vm > 0 ? vm : 0;
8213 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
8215 u64 now, diff, diffms;
8218 lockdep_assert_held(&mchdev_lock);
8220 now = ktime_get_raw_ns();
8221 diffms = now - dev_priv->ips.last_time2;
8222 do_div(diffms, NSEC_PER_MSEC);
8224 /* Don't divide by 0 */
8228 count = I915_READ(GFXEC);
8230 if (count < dev_priv->ips.last_count2) {
8231 diff = ~0UL - dev_priv->ips.last_count2;
8234 diff = count - dev_priv->ips.last_count2;
8237 dev_priv->ips.last_count2 = count;
8238 dev_priv->ips.last_time2 = now;
8240 /* More magic constants... */
8242 diff = div_u64(diff, diffms * 10);
8243 dev_priv->ips.gfx_power = diff;
8246 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
8248 intel_wakeref_t wakeref;
8250 if (!IS_GEN(dev_priv, 5))
8253 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
8254 spin_lock_irq(&mchdev_lock);
8255 __i915_update_gfx_val(dev_priv);
8256 spin_unlock_irq(&mchdev_lock);
8260 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
8262 unsigned long t, corr, state1, corr2, state2;
8265 lockdep_assert_held(&mchdev_lock);
8267 pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));
8268 pxvid = (pxvid >> 24) & 0x7f;
8269 ext_v = pvid_to_extvid(dev_priv, pxvid);
8273 t = i915_mch_val(dev_priv);
8275 /* Revel in the empirically derived constants */
8277 /* Correction factor in 1/100000 units */
8279 corr = ((t * 2349) + 135940);
8281 corr = ((t * 964) + 29317);
8283 corr = ((t * 301) + 1004);
8285 corr = corr * ((150142 * state1) / 10000 - 78642);
8287 corr2 = (corr * dev_priv->ips.corr);
8289 state2 = (corr2 * state1) / 10000;
8290 state2 /= 100; /* convert to mW */
8292 __i915_update_gfx_val(dev_priv);
8294 return dev_priv->ips.gfx_power + state2;
8297 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
8299 intel_wakeref_t wakeref;
8300 unsigned long val = 0;
8302 if (!IS_GEN(dev_priv, 5))
8305 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
8306 spin_lock_irq(&mchdev_lock);
8307 val = __i915_gfx_val(dev_priv);
8308 spin_unlock_irq(&mchdev_lock);
8314 static struct drm_i915_private __rcu *i915_mch_dev;
8316 static struct drm_i915_private *mchdev_get(void)
8318 struct drm_i915_private *i915;
8321 i915 = rcu_dereference(i915_mch_dev);
8322 if (!kref_get_unless_zero(&i915->drm.ref))
8330 * i915_read_mch_val - return value for IPS use
8332 * Calculate and return a value for the IPS driver to use when deciding whether
8333 * we have thermal and power headroom to increase CPU or GPU power budget.
8335 unsigned long i915_read_mch_val(void)
8337 struct drm_i915_private *i915;
8338 unsigned long chipset_val = 0;
8339 unsigned long graphics_val = 0;
8340 intel_wakeref_t wakeref;
8342 i915 = mchdev_get();
8346 with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
8347 spin_lock_irq(&mchdev_lock);
8348 chipset_val = __i915_chipset_val(i915);
8349 graphics_val = __i915_gfx_val(i915);
8350 spin_unlock_irq(&mchdev_lock);
8353 drm_dev_put(&i915->drm);
8354 return chipset_val + graphics_val;
8356 EXPORT_SYMBOL_GPL(i915_read_mch_val);
8359 * i915_gpu_raise - raise GPU frequency limit
8361 * Raise the limit; IPS indicates we have thermal headroom.
8363 bool i915_gpu_raise(void)
8365 struct drm_i915_private *i915;
8367 i915 = mchdev_get();
8371 spin_lock_irq(&mchdev_lock);
8372 if (i915->ips.max_delay > i915->ips.fmax)
8373 i915->ips.max_delay--;
8374 spin_unlock_irq(&mchdev_lock);
8376 drm_dev_put(&i915->drm);
8379 EXPORT_SYMBOL_GPL(i915_gpu_raise);
8382 * i915_gpu_lower - lower GPU frequency limit
8384 * IPS indicates we're close to a thermal limit, so throttle back the GPU
8385 * frequency maximum.
8387 bool i915_gpu_lower(void)
8389 struct drm_i915_private *i915;
8391 i915 = mchdev_get();
8395 spin_lock_irq(&mchdev_lock);
8396 if (i915->ips.max_delay < i915->ips.min_delay)
8397 i915->ips.max_delay++;
8398 spin_unlock_irq(&mchdev_lock);
8400 drm_dev_put(&i915->drm);
8403 EXPORT_SYMBOL_GPL(i915_gpu_lower);
8406 * i915_gpu_busy - indicate GPU business to IPS
8408 * Tell the IPS driver whether or not the GPU is busy.
8410 bool i915_gpu_busy(void)
8412 struct drm_i915_private *i915;
8415 i915 = mchdev_get();
8419 ret = i915->gt.awake;
8421 drm_dev_put(&i915->drm);
8424 EXPORT_SYMBOL_GPL(i915_gpu_busy);
8427 * i915_gpu_turbo_disable - disable graphics turbo
8429 * Disable graphics turbo by resetting the max frequency and setting the
8430 * current frequency to the default.
8432 bool i915_gpu_turbo_disable(void)
8434 struct drm_i915_private *i915;
8437 i915 = mchdev_get();
8441 spin_lock_irq(&mchdev_lock);
8442 i915->ips.max_delay = i915->ips.fstart;
8443 ret = ironlake_set_drps(i915, i915->ips.fstart);
8444 spin_unlock_irq(&mchdev_lock);
8446 drm_dev_put(&i915->drm);
8449 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
8452 * Tells the intel_ips driver that the i915 driver is now loaded, if
8453 * IPS got loaded first.
8455 * This awkward dance is so that neither module has to depend on the
8456 * other in order for IPS to do the appropriate communication of
8457 * GPU turbo limits to i915.
8460 ips_ping_for_i915_load(void)
8464 link = symbol_get(ips_link_to_i915_driver);
8467 symbol_put(ips_link_to_i915_driver);
8471 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
8473 /* We only register the i915 ips part with intel-ips once everything is
8474 * set up, to avoid intel-ips sneaking in and reading bogus values. */
8475 rcu_assign_pointer(i915_mch_dev, dev_priv);
8477 ips_ping_for_i915_load();
8480 void intel_gpu_ips_teardown(void)
8482 rcu_assign_pointer(i915_mch_dev, NULL);
8485 static void intel_init_emon(struct drm_i915_private *dev_priv)
8491 /* Disable to program */
8495 /* Program energy weights for various events */
8496 I915_WRITE(SDEW, 0x15040d00);
8497 I915_WRITE(CSIEW0, 0x007f0000);
8498 I915_WRITE(CSIEW1, 0x1e220004);
8499 I915_WRITE(CSIEW2, 0x04000004);
8501 for (i = 0; i < 5; i++)
8502 I915_WRITE(PEW(i), 0);
8503 for (i = 0; i < 3; i++)
8504 I915_WRITE(DEW(i), 0);
8506 /* Program P-state weights to account for frequency power adjustment */
8507 for (i = 0; i < 16; i++) {
8508 u32 pxvidfreq = I915_READ(PXVFREQ(i));
8509 unsigned long freq = intel_pxfreq(pxvidfreq);
8510 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8515 val *= (freq / 1000);
8517 val /= (127*127*900);
8519 DRM_ERROR("bad pxval: %ld\n", val);
8522 /* Render standby states get 0 weight */
8526 for (i = 0; i < 4; i++) {
8527 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8528 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8529 I915_WRITE(PXW(i), val);
8532 /* Adjust magic regs to magic values (more experimental results) */
8533 I915_WRITE(OGW0, 0);
8534 I915_WRITE(OGW1, 0);
8535 I915_WRITE(EG0, 0x00007f00);
8536 I915_WRITE(EG1, 0x0000000e);
8537 I915_WRITE(EG2, 0x000e0000);
8538 I915_WRITE(EG3, 0x68000300);
8539 I915_WRITE(EG4, 0x42000000);
8540 I915_WRITE(EG5, 0x00140031);
8544 for (i = 0; i < 8; i++)
8545 I915_WRITE(PXWL(i), 0);
8547 /* Enable PMON + select events */
8548 I915_WRITE(ECR, 0x80000019);
8550 lcfuse = I915_READ(LCFUSE02);
8552 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
8555 static bool i915_rc6_ctx_corrupted(struct drm_i915_private *dev_priv)
8557 return !I915_READ(GEN8_RC6_CTX_INFO);
8560 static void i915_rc6_ctx_wa_init(struct drm_i915_private *i915)
8562 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915))
8565 if (i915_rc6_ctx_corrupted(i915)) {
8566 DRM_INFO("RC6 context corrupted, disabling runtime power management\n");
8567 i915->gt_pm.rc6.ctx_corrupted = true;
8568 i915->gt_pm.rc6.ctx_corrupted_wakeref =
8569 intel_runtime_pm_get(&i915->runtime_pm);
8573 static void i915_rc6_ctx_wa_cleanup(struct drm_i915_private *i915)
8575 if (i915->gt_pm.rc6.ctx_corrupted) {
8576 intel_runtime_pm_put(&i915->runtime_pm,
8577 i915->gt_pm.rc6.ctx_corrupted_wakeref);
8578 i915->gt_pm.rc6.ctx_corrupted = false;
8583 * i915_rc6_ctx_wa_suspend - system suspend sequence for the RC6 CTX WA
8584 * @i915: i915 device
8586 * Perform any steps needed to clean up the RC6 CTX WA before system suspend.
8588 void i915_rc6_ctx_wa_suspend(struct drm_i915_private *i915)
8590 if (i915->gt_pm.rc6.ctx_corrupted)
8591 intel_runtime_pm_put(&i915->runtime_pm,
8592 i915->gt_pm.rc6.ctx_corrupted_wakeref);
8596 * i915_rc6_ctx_wa_resume - system resume sequence for the RC6 CTX WA
8597 * @i915: i915 device
8599 * Perform any steps needed to re-init the RC6 CTX WA after system resume.
8601 void i915_rc6_ctx_wa_resume(struct drm_i915_private *i915)
8603 if (!i915->gt_pm.rc6.ctx_corrupted)
8606 if (i915_rc6_ctx_corrupted(i915)) {
8607 i915->gt_pm.rc6.ctx_corrupted_wakeref =
8608 intel_runtime_pm_get(&i915->runtime_pm);
8612 DRM_INFO("RC6 context restored, re-enabling runtime power management\n");
8613 i915->gt_pm.rc6.ctx_corrupted = false;
8616 static void intel_disable_rc6(struct drm_i915_private *dev_priv);
8619 * i915_rc6_ctx_wa_check - check for a new RC6 CTX corruption
8620 * @i915: i915 device
8622 * Check if an RC6 CTX corruption has happened since the last check and if so
8623 * disable RC6 and runtime power management.
8625 * Return false if no context corruption has happened since the last call of
8626 * this function, true otherwise.
8628 bool i915_rc6_ctx_wa_check(struct drm_i915_private *i915)
8630 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915))
8633 if (i915->gt_pm.rc6.ctx_corrupted)
8636 if (!i915_rc6_ctx_corrupted(i915))
8639 DRM_NOTE("RC6 context corruption, disabling runtime power management\n");
8641 intel_disable_rc6(i915);
8642 i915->gt_pm.rc6.ctx_corrupted = true;
8643 i915->gt_pm.rc6.ctx_corrupted_wakeref =
8644 intel_runtime_pm_get_noresume(&i915->runtime_pm);
8649 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
8651 struct intel_rps *rps = &dev_priv->gt_pm.rps;
8654 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
8657 if (!sanitize_rc6(dev_priv)) {
8658 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
8659 pm_runtime_get(&dev_priv->drm.pdev->dev);
8662 i915_rc6_ctx_wa_init(dev_priv);
8664 /* Initialize RPS limits (for userspace) */
8665 if (IS_CHERRYVIEW(dev_priv))
8666 cherryview_init_gt_powersave(dev_priv);
8667 else if (IS_VALLEYVIEW(dev_priv))
8668 valleyview_init_gt_powersave(dev_priv);
8669 else if (INTEL_GEN(dev_priv) >= 6)
8670 gen6_init_rps_frequencies(dev_priv);
8672 /* Derive initial user preferences/limits from the hardware limits */
8673 rps->max_freq_softlimit = rps->max_freq;
8674 rps->min_freq_softlimit = rps->min_freq;
8676 /* After setting max-softlimit, find the overclock max freq */
8677 if (IS_GEN(dev_priv, 6) ||
8678 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
8681 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS,
8683 if (params & BIT(31)) { /* OC supported */
8684 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
8685 (rps->max_freq & 0xff) * 50,
8686 (params & 0xff) * 50);
8687 rps->max_freq = params & 0xff;
8691 /* Finally allow us to boost to max by default */
8692 rps->boost_freq = rps->max_freq;
8693 rps->idle_freq = rps->min_freq;
8694 rps->cur_freq = rps->idle_freq;
8697 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
8699 if (IS_VALLEYVIEW(dev_priv))
8700 valleyview_cleanup_gt_powersave(dev_priv);
8702 i915_rc6_ctx_wa_cleanup(dev_priv);
8704 if (!HAS_RC6(dev_priv))
8705 pm_runtime_put(&dev_priv->drm.pdev->dev);
8708 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
8710 dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
8711 dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
8712 intel_disable_gt_powersave(dev_priv);
8714 if (INTEL_GEN(dev_priv) >= 11)
8715 gen11_reset_rps_interrupts(dev_priv);
8716 else if (INTEL_GEN(dev_priv) >= 6)
8717 gen6_reset_rps_interrupts(dev_priv);
8720 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
8722 lockdep_assert_held(&i915->gt_pm.rps.lock);
8724 if (!i915->gt_pm.llc_pstate.enabled)
8727 /* Currently there is no HW configuration to be done to disable. */
8729 i915->gt_pm.llc_pstate.enabled = false;
8732 static void __intel_disable_rc6(struct drm_i915_private *dev_priv)
8734 lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
8736 if (!dev_priv->gt_pm.rc6.enabled)
8739 if (INTEL_GEN(dev_priv) >= 9)
8740 gen9_disable_rc6(dev_priv);
8741 else if (IS_CHERRYVIEW(dev_priv))
8742 cherryview_disable_rc6(dev_priv);
8743 else if (IS_VALLEYVIEW(dev_priv))
8744 valleyview_disable_rc6(dev_priv);
8745 else if (INTEL_GEN(dev_priv) >= 6)
8746 gen6_disable_rc6(dev_priv);
8748 dev_priv->gt_pm.rc6.enabled = false;
8751 static void intel_disable_rc6(struct drm_i915_private *dev_priv)
8753 struct intel_rps *rps = &dev_priv->gt_pm.rps;
8755 mutex_lock(&rps->lock);
8756 __intel_disable_rc6(dev_priv);
8757 mutex_unlock(&rps->lock);
8760 static void intel_disable_rps(struct drm_i915_private *dev_priv)
8762 lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
8764 if (!dev_priv->gt_pm.rps.enabled)
8767 if (INTEL_GEN(dev_priv) >= 9)
8768 gen9_disable_rps(dev_priv);
8769 else if (IS_CHERRYVIEW(dev_priv))
8770 cherryview_disable_rps(dev_priv);
8771 else if (IS_VALLEYVIEW(dev_priv))
8772 valleyview_disable_rps(dev_priv);
8773 else if (INTEL_GEN(dev_priv) >= 6)
8774 gen6_disable_rps(dev_priv);
8775 else if (IS_IRONLAKE_M(dev_priv))
8776 ironlake_disable_drps(dev_priv);
8778 dev_priv->gt_pm.rps.enabled = false;
8781 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8783 mutex_lock(&dev_priv->gt_pm.rps.lock);
8785 __intel_disable_rc6(dev_priv);
8786 intel_disable_rps(dev_priv);
8787 if (HAS_LLC(dev_priv))
8788 intel_disable_llc_pstate(dev_priv);
8790 mutex_unlock(&dev_priv->gt_pm.rps.lock);
8793 static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
8795 lockdep_assert_held(&i915->gt_pm.rps.lock);
8797 if (i915->gt_pm.llc_pstate.enabled)
8800 gen6_update_ring_freq(i915);
8802 i915->gt_pm.llc_pstate.enabled = true;
8805 static void intel_enable_rc6(struct drm_i915_private *dev_priv)
8807 lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
8809 if (dev_priv->gt_pm.rc6.enabled)
8812 if (dev_priv->gt_pm.rc6.ctx_corrupted)
8815 if (IS_CHERRYVIEW(dev_priv))
8816 cherryview_enable_rc6(dev_priv);
8817 else if (IS_VALLEYVIEW(dev_priv))
8818 valleyview_enable_rc6(dev_priv);
8819 else if (INTEL_GEN(dev_priv) >= 11)
8820 gen11_enable_rc6(dev_priv);
8821 else if (INTEL_GEN(dev_priv) >= 9)
8822 gen9_enable_rc6(dev_priv);
8823 else if (IS_BROADWELL(dev_priv))
8824 gen8_enable_rc6(dev_priv);
8825 else if (INTEL_GEN(dev_priv) >= 6)
8826 gen6_enable_rc6(dev_priv);
8828 dev_priv->gt_pm.rc6.enabled = true;
8831 static void intel_enable_rps(struct drm_i915_private *dev_priv)
8833 struct intel_rps *rps = &dev_priv->gt_pm.rps;
8835 lockdep_assert_held(&rps->lock);
8840 if (IS_CHERRYVIEW(dev_priv)) {
8841 cherryview_enable_rps(dev_priv);
8842 } else if (IS_VALLEYVIEW(dev_priv)) {
8843 valleyview_enable_rps(dev_priv);
8844 } else if (INTEL_GEN(dev_priv) >= 9) {
8845 gen9_enable_rps(dev_priv);
8846 } else if (IS_BROADWELL(dev_priv)) {
8847 gen8_enable_rps(dev_priv);
8848 } else if (INTEL_GEN(dev_priv) >= 6) {
8849 gen6_enable_rps(dev_priv);
8850 } else if (IS_IRONLAKE_M(dev_priv)) {
8851 ironlake_enable_drps(dev_priv);
8852 intel_init_emon(dev_priv);
8855 WARN_ON(rps->max_freq < rps->min_freq);
8856 WARN_ON(rps->idle_freq > rps->max_freq);
8858 WARN_ON(rps->efficient_freq < rps->min_freq);
8859 WARN_ON(rps->efficient_freq > rps->max_freq);
8861 rps->enabled = true;
8864 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8866 /* Powersaving is controlled by the host when inside a VM */
8867 if (intel_vgpu_active(dev_priv))
8870 mutex_lock(&dev_priv->gt_pm.rps.lock);
8872 if (HAS_RC6(dev_priv))
8873 intel_enable_rc6(dev_priv);
8874 if (HAS_RPS(dev_priv))
8875 intel_enable_rps(dev_priv);
8876 if (HAS_LLC(dev_priv))
8877 intel_enable_llc_pstate(dev_priv);
8879 mutex_unlock(&dev_priv->gt_pm.rps.lock);
8882 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
8885 * On Ibex Peak and Cougar Point, we need to disable clock
8886 * gating for the panel power sequencer or it will fail to
8887 * start up when no ports are active.
8889 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8892 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
8896 for_each_pipe(dev_priv, pipe) {
8897 I915_WRITE(DSPCNTR(pipe),
8898 I915_READ(DSPCNTR(pipe)) |
8899 DISPPLANE_TRICKLE_FEED_DISABLE);
8901 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
8902 POSTING_READ(DSPSURF(pipe));
8906 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
8908 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8912 * WaFbcDisableDpfcClockGating:ilk
8914 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
8915 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
8916 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
8918 I915_WRITE(PCH_3DCGDIS0,
8919 MARIUNIT_CLOCK_GATE_DISABLE |
8920 SVSMUNIT_CLOCK_GATE_DISABLE);
8921 I915_WRITE(PCH_3DCGDIS1,
8922 VFMUNIT_CLOCK_GATE_DISABLE);
8925 * According to the spec the following bits should be set in
8926 * order to enable memory self-refresh
8927 * The bit 22/21 of 0x42004
8928 * The bit 5 of 0x42020
8929 * The bit 15 of 0x45000
8931 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8932 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8933 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8934 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
8935 I915_WRITE(DISP_ARB_CTL,
8936 (I915_READ(DISP_ARB_CTL) |
8940 * Based on the document from hardware guys the following bits
8941 * should be set unconditionally in order to enable FBC.
8942 * The bit 22 of 0x42000
8943 * The bit 22 of 0x42004
8944 * The bit 7,8,9 of 0x42020.
8946 if (IS_IRONLAKE_M(dev_priv)) {
8947 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
8948 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8949 I915_READ(ILK_DISPLAY_CHICKEN1) |
8951 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8952 I915_READ(ILK_DISPLAY_CHICKEN2) |
8956 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8958 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8959 I915_READ(ILK_DISPLAY_CHICKEN2) |
8960 ILK_ELPIN_409_SELECT);
8961 I915_WRITE(_3D_CHICKEN2,
8962 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8963 _3D_CHICKEN2_WM_READ_PIPELINED);
8965 /* WaDisableRenderCachePipelinedFlush:ilk */
8966 I915_WRITE(CACHE_MODE_0,
8967 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8969 /* WaDisable_RenderCache_OperationalFlush:ilk */
8970 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8972 g4x_disable_trickle_feed(dev_priv);
8974 ibx_init_clock_gating(dev_priv);
8977 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
8983 * On Ibex Peak and Cougar Point, we need to disable clock
8984 * gating for the panel power sequencer or it will fail to
8985 * start up when no ports are active.
8987 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
8988 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
8989 PCH_CPUNIT_CLOCK_GATE_DISABLE);
8990 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8991 DPLS_EDP_PPS_FIX_DIS);
8992 /* The below fixes the weird display corruption, a few pixels shifted
8993 * downward, on (only) LVDS of some HP laptops with IVY.
8995 for_each_pipe(dev_priv, pipe) {
8996 val = I915_READ(TRANS_CHICKEN2(pipe));
8997 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
8998 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8999 if (dev_priv->vbt.fdi_rx_polarity_inverted)
9000 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
9001 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
9002 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
9003 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
9004 I915_WRITE(TRANS_CHICKEN2(pipe), val);
9006 /* WADP0ClockGatingDisable */
9007 for_each_pipe(dev_priv, pipe) {
9008 I915_WRITE(TRANS_CHICKEN1(pipe),
9009 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
9013 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
9017 tmp = I915_READ(MCH_SSKPD);
9018 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
9019 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
9023 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
9025 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
9027 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
9029 I915_WRITE(ILK_DISPLAY_CHICKEN2,
9030 I915_READ(ILK_DISPLAY_CHICKEN2) |
9031 ILK_ELPIN_409_SELECT);
9033 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
9034 I915_WRITE(_3D_CHICKEN,
9035 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
9037 /* WaDisable_RenderCache_OperationalFlush:snb */
9038 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9041 * BSpec recoomends 8x4 when MSAA is used,
9042 * however in practice 16x4 seems fastest.
9044 * Note that PS/WM thread counts depend on the WIZ hashing
9045 * disable bit, which we don't touch here, but it's good
9046 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
9048 I915_WRITE(GEN6_GT_MODE,
9049 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
9051 I915_WRITE(CACHE_MODE_0,
9052 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
9054 I915_WRITE(GEN6_UCGCTL1,
9055 I915_READ(GEN6_UCGCTL1) |
9056 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
9057 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
9059 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
9060 * gating disable must be set. Failure to set it results in
9061 * flickering pixels due to Z write ordering failures after
9062 * some amount of runtime in the Mesa "fire" demo, and Unigine
9063 * Sanctuary and Tropics, and apparently anything else with
9064 * alpha test or pixel discard.
9066 * According to the spec, bit 11 (RCCUNIT) must also be set,
9067 * but we didn't debug actual testcases to find it out.
9069 * WaDisableRCCUnitClockGating:snb
9070 * WaDisableRCPBUnitClockGating:snb
9072 I915_WRITE(GEN6_UCGCTL2,
9073 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
9074 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
9076 /* WaStripsFansDisableFastClipPerformanceFix:snb */
9077 I915_WRITE(_3D_CHICKEN3,
9078 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
9082 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
9083 * 3DSTATE_SF number of SF output attributes is more than 16."
9085 I915_WRITE(_3D_CHICKEN3,
9086 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
9089 * According to the spec the following bits should be
9090 * set in order to enable memory self-refresh and fbc:
9091 * The bit21 and bit22 of 0x42000
9092 * The bit21 and bit22 of 0x42004
9093 * The bit5 and bit7 of 0x42020
9094 * The bit14 of 0x70180
9095 * The bit14 of 0x71180
9097 * WaFbcAsynchFlipDisableFbcQueue:snb
9099 I915_WRITE(ILK_DISPLAY_CHICKEN1,
9100 I915_READ(ILK_DISPLAY_CHICKEN1) |
9101 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
9102 I915_WRITE(ILK_DISPLAY_CHICKEN2,
9103 I915_READ(ILK_DISPLAY_CHICKEN2) |
9104 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
9105 I915_WRITE(ILK_DSPCLK_GATE_D,
9106 I915_READ(ILK_DSPCLK_GATE_D) |
9107 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
9108 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
9110 g4x_disable_trickle_feed(dev_priv);
9112 cpt_init_clock_gating(dev_priv);
9114 gen6_check_mch_setup(dev_priv);
9117 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
9119 u32 reg = I915_READ(GEN7_FF_THREAD_MODE);
9122 * WaVSThreadDispatchOverride:ivb,vlv
9124 * This actually overrides the dispatch
9125 * mode for all thread types.
9127 reg &= ~GEN7_FF_SCHED_MASK;
9128 reg |= GEN7_FF_TS_SCHED_HW;
9129 reg |= GEN7_FF_VS_SCHED_HW;
9130 reg |= GEN7_FF_DS_SCHED_HW;
9132 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
9135 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
9138 * TODO: this bit should only be enabled when really needed, then
9139 * disabled when not needed anymore in order to save power.
9141 if (HAS_PCH_LPT_LP(dev_priv))
9142 I915_WRITE(SOUTH_DSPCLK_GATE_D,
9143 I915_READ(SOUTH_DSPCLK_GATE_D) |
9144 PCH_LP_PARTITION_LEVEL_DISABLE);
9146 /* WADPOClockGatingDisable:hsw */
9147 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
9148 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
9149 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
9152 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
9154 if (HAS_PCH_LPT_LP(dev_priv)) {
9155 u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9157 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9158 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9162 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
9163 int general_prio_credits,
9164 int high_prio_credits)
9169 /* WaTempDisableDOPClkGating:bdw */
9170 misccpctl = I915_READ(GEN7_MISCCPCTL);
9171 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
9173 val = I915_READ(GEN8_L3SQCREG1);
9174 val &= ~L3_PRIO_CREDITS_MASK;
9175 val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
9176 val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
9177 I915_WRITE(GEN8_L3SQCREG1, val);
9180 * Wait at least 100 clocks before re-enabling clock gating.
9181 * See the definition of L3SQCREG1 in BSpec.
9183 POSTING_READ(GEN8_L3SQCREG1);
9185 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
9188 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
9190 /* This is not an Wa. Enable to reduce Sampler power */
9191 I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
9192 I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
9194 /* WaEnable32PlaneMode:icl */
9195 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
9196 _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
9199 * Wa_1408615072:icl,ehl (vsunit)
9200 * Wa_1407596294:icl,ehl (hsunit)
9202 intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE,
9203 0, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
9205 /* Wa_1407352427:icl,ehl */
9206 intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
9207 0, PSDUNIT_CLKGATE_DIS);
9210 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
9212 if (!HAS_PCH_CNP(dev_priv))
9215 /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
9216 I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
9217 CNP_PWM_CGE_GATING_DISABLE);
9220 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
9223 cnp_init_clock_gating(dev_priv);
9225 /* This is not an Wa. Enable for better image quality */
9226 I915_WRITE(_3D_CHICKEN3,
9227 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
9229 /* WaEnableChickenDCPR:cnl */
9230 I915_WRITE(GEN8_CHICKEN_DCPR_1,
9231 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
9233 /* WaFbcWakeMemOn:cnl */
9234 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
9235 DISP_FBC_MEMORY_WAKE);
9237 val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
9238 /* ReadHitWriteOnlyDisable:cnl */
9239 val |= RCCUNIT_CLKGATE_DIS;
9240 /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
9241 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
9242 val |= SARBUNIT_CLKGATE_DIS;
9243 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
9245 /* Wa_2201832410:cnl */
9246 val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
9247 val |= GWUNIT_CLKGATE_DIS;
9248 I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
9250 /* WaDisableVFclkgate:cnl */
9251 /* WaVFUnitClockGatingDisable:cnl */
9252 val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
9253 val |= VFUNIT_CLKGATE_DIS;
9254 I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
9257 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
9259 cnp_init_clock_gating(dev_priv);
9260 gen9_init_clock_gating(dev_priv);
9262 /* WaFbcNukeOnHostModify:cfl */
9263 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
9264 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9267 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
9269 gen9_init_clock_gating(dev_priv);
9271 /* WaDisableSDEUnitClockGating:kbl */
9272 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
9273 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9274 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
9276 /* WaDisableGamClockGating:kbl */
9277 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
9278 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
9279 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
9281 /* WaFbcNukeOnHostModify:kbl */
9282 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
9283 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9286 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
9288 gen9_init_clock_gating(dev_priv);
9290 /* WAC6entrylatency:skl */
9291 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
9292 FBC_LLC_FULLY_OPEN);
9294 /* WaFbcNukeOnHostModify:skl */
9295 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
9296 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9299 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
9303 /* WaSwitchSolVfFArbitrationPriority:bdw */
9304 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
9306 /* WaPsrDPAMaskVBlankInSRD:bdw */
9307 I915_WRITE(CHICKEN_PAR1_1,
9308 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
9310 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
9311 for_each_pipe(dev_priv, pipe) {
9312 I915_WRITE(CHICKEN_PIPESL_1(pipe),
9313 I915_READ(CHICKEN_PIPESL_1(pipe)) |
9314 BDW_DPRS_MASK_VBLANK_SRD);
9317 /* WaVSRefCountFullforceMissDisable:bdw */
9318 /* WaDSRefCountFullforceMissDisable:bdw */
9319 I915_WRITE(GEN7_FF_THREAD_MODE,
9320 I915_READ(GEN7_FF_THREAD_MODE) &
9321 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
9323 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
9324 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
9326 /* WaDisableSDEUnitClockGating:bdw */
9327 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9328 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
9330 /* WaProgramL3SqcReg1Default:bdw */
9331 gen8_set_l3sqc_credits(dev_priv, 30, 2);
9333 /* WaKVMNotificationOnConfigChange:bdw */
9334 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
9335 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
9337 lpt_init_clock_gating(dev_priv);
9339 /* WaDisableDopClockGating:bdw
9341 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
9344 I915_WRITE(GEN6_UCGCTL1,
9345 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
9348 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
9350 /* L3 caching of data atomics doesn't work -- disable it. */
9351 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
9352 I915_WRITE(HSW_ROW_CHICKEN3,
9353 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
9355 /* This is required by WaCatErrorRejectionIssue:hsw */
9356 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
9357 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
9358 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
9360 /* WaVSRefCountFullforceMissDisable:hsw */
9361 I915_WRITE(GEN7_FF_THREAD_MODE,
9362 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
9364 /* WaDisable_RenderCache_OperationalFlush:hsw */
9365 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9367 /* enable HiZ Raw Stall Optimization */
9368 I915_WRITE(CACHE_MODE_0_GEN7,
9369 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
9371 /* WaDisable4x2SubspanOptimization:hsw */
9372 I915_WRITE(CACHE_MODE_1,
9373 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
9376 * BSpec recommends 8x4 when MSAA is used,
9377 * however in practice 16x4 seems fastest.
9379 * Note that PS/WM thread counts depend on the WIZ hashing
9380 * disable bit, which we don't touch here, but it's good
9381 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
9383 I915_WRITE(GEN7_GT_MODE,
9384 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
9386 /* WaSampleCChickenBitEnable:hsw */
9387 I915_WRITE(HALF_SLICE_CHICKEN3,
9388 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
9390 /* WaSwitchSolVfFArbitrationPriority:hsw */
9391 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
9393 lpt_init_clock_gating(dev_priv);
9396 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
9400 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
9402 /* WaDisableEarlyCull:ivb */
9403 I915_WRITE(_3D_CHICKEN3,
9404 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
9406 /* WaDisableBackToBackFlipFix:ivb */
9407 I915_WRITE(IVB_CHICKEN3,
9408 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
9409 CHICKEN3_DGMG_DONE_FIX_DISABLE);
9411 /* WaDisablePSDDualDispatchEnable:ivb */
9412 if (IS_IVB_GT1(dev_priv))
9413 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
9414 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
9416 /* WaDisable_RenderCache_OperationalFlush:ivb */
9417 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9419 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
9420 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
9421 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
9423 /* WaApplyL3ControlAndL3ChickenMode:ivb */
9424 I915_WRITE(GEN7_L3CNTLREG1,
9425 GEN7_WA_FOR_GEN7_L3_CONTROL);
9426 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
9427 GEN7_WA_L3_CHICKEN_MODE);
9428 if (IS_IVB_GT1(dev_priv))
9429 I915_WRITE(GEN7_ROW_CHICKEN2,
9430 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
9432 /* must write both registers */
9433 I915_WRITE(GEN7_ROW_CHICKEN2,
9434 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
9435 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
9436 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
9439 /* WaForceL3Serialization:ivb */
9440 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
9441 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
9444 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
9445 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
9447 I915_WRITE(GEN6_UCGCTL2,
9448 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
9450 /* This is required by WaCatErrorRejectionIssue:ivb */
9451 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
9452 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
9453 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
9455 g4x_disable_trickle_feed(dev_priv);
9457 gen7_setup_fixed_func_scheduler(dev_priv);
9459 if (0) { /* causes HiZ corruption on ivb:gt1 */
9460 /* enable HiZ Raw Stall Optimization */
9461 I915_WRITE(CACHE_MODE_0_GEN7,
9462 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
9465 /* WaDisable4x2SubspanOptimization:ivb */
9466 I915_WRITE(CACHE_MODE_1,
9467 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
9470 * BSpec recommends 8x4 when MSAA is used,
9471 * however in practice 16x4 seems fastest.
9473 * Note that PS/WM thread counts depend on the WIZ hashing
9474 * disable bit, which we don't touch here, but it's good
9475 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
9477 I915_WRITE(GEN7_GT_MODE,
9478 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
9480 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
9481 snpcr &= ~GEN6_MBC_SNPCR_MASK;
9482 snpcr |= GEN6_MBC_SNPCR_MED;
9483 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
9485 if (!HAS_PCH_NOP(dev_priv))
9486 cpt_init_clock_gating(dev_priv);
9488 gen6_check_mch_setup(dev_priv);
9491 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
9493 /* WaDisableEarlyCull:vlv */
9494 I915_WRITE(_3D_CHICKEN3,
9495 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
9497 /* WaDisableBackToBackFlipFix:vlv */
9498 I915_WRITE(IVB_CHICKEN3,
9499 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
9500 CHICKEN3_DGMG_DONE_FIX_DISABLE);
9502 /* WaPsdDispatchEnable:vlv */
9503 /* WaDisablePSDDualDispatchEnable:vlv */
9504 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
9505 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
9506 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
9508 /* WaDisable_RenderCache_OperationalFlush:vlv */
9509 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9511 /* WaForceL3Serialization:vlv */
9512 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
9513 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
9515 /* WaDisableDopClockGating:vlv */
9516 I915_WRITE(GEN7_ROW_CHICKEN2,
9517 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
9519 /* This is required by WaCatErrorRejectionIssue:vlv */
9520 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
9521 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
9522 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
9524 gen7_setup_fixed_func_scheduler(dev_priv);
9527 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
9528 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
9530 I915_WRITE(GEN6_UCGCTL2,
9531 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
9533 /* WaDisableL3Bank2xClockGate:vlv
9534 * Disabling L3 clock gating- MMIO 940c[25] = 1
9535 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
9536 I915_WRITE(GEN7_UCGCTL4,
9537 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
9540 * BSpec says this must be set, even though
9541 * WaDisable4x2SubspanOptimization isn't listed for VLV.
9543 I915_WRITE(CACHE_MODE_1,
9544 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
9547 * BSpec recommends 8x4 when MSAA is used,
9548 * however in practice 16x4 seems fastest.
9550 * Note that PS/WM thread counts depend on the WIZ hashing
9551 * disable bit, which we don't touch here, but it's good
9552 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
9554 I915_WRITE(GEN7_GT_MODE,
9555 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
9558 * WaIncreaseL3CreditsForVLVB0:vlv
9559 * This is the hardware default actually.
9561 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
9564 * WaDisableVLVClockGating_VBIIssue:vlv
9565 * Disable clock gating on th GCFG unit to prevent a delay
9566 * in the reporting of vblank events.
9568 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
9571 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
9573 /* WaVSRefCountFullforceMissDisable:chv */
9574 /* WaDSRefCountFullforceMissDisable:chv */
9575 I915_WRITE(GEN7_FF_THREAD_MODE,
9576 I915_READ(GEN7_FF_THREAD_MODE) &
9577 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
9579 /* WaDisableSemaphoreAndSyncFlipWait:chv */
9580 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
9581 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
9583 /* WaDisableCSUnitClockGating:chv */
9584 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
9585 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
9587 /* WaDisableSDEUnitClockGating:chv */
9588 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9589 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
9592 * WaProgramL3SqcReg1Default:chv
9593 * See gfxspecs/Related Documents/Performance Guide/
9594 * LSQC Setting Recommendations.
9596 gen8_set_l3sqc_credits(dev_priv, 38, 2);
9599 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
9603 I915_WRITE(RENCLK_GATE_D1, 0);
9604 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
9605 GS_UNIT_CLOCK_GATE_DISABLE |
9606 CL_UNIT_CLOCK_GATE_DISABLE);
9607 I915_WRITE(RAMCLK_GATE_D, 0);
9608 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
9609 OVRUNIT_CLOCK_GATE_DISABLE |
9610 OVCUNIT_CLOCK_GATE_DISABLE;
9611 if (IS_GM45(dev_priv))
9612 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
9613 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
9615 /* WaDisableRenderCachePipelinedFlush */
9616 I915_WRITE(CACHE_MODE_0,
9617 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
9619 /* WaDisable_RenderCache_OperationalFlush:g4x */
9620 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9622 g4x_disable_trickle_feed(dev_priv);
9625 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
9627 struct intel_uncore *uncore = &dev_priv->uncore;
9629 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
9630 intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
9631 intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
9632 intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
9633 intel_uncore_write16(uncore, DEUC, 0);
9634 intel_uncore_write(uncore,
9636 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
9638 /* WaDisable_RenderCache_OperationalFlush:gen4 */
9639 intel_uncore_write(uncore,
9641 _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9644 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
9646 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
9647 I965_RCC_CLOCK_GATE_DISABLE |
9648 I965_RCPB_CLOCK_GATE_DISABLE |
9649 I965_ISC_CLOCK_GATE_DISABLE |
9650 I965_FBC_CLOCK_GATE_DISABLE);
9651 I915_WRITE(RENCLK_GATE_D2, 0);
9652 I915_WRITE(MI_ARB_STATE,
9653 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
9655 /* WaDisable_RenderCache_OperationalFlush:gen4 */
9656 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9659 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
9661 u32 dstate = I915_READ(D_STATE);
9663 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
9664 DSTATE_DOT_CLOCK_GATING;
9665 I915_WRITE(D_STATE, dstate);
9667 if (IS_PINEVIEW(dev_priv))
9668 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
9670 /* IIR "flip pending" means done if this bit is set */
9671 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
9673 /* interrupts should cause a wake up from C3 */
9674 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
9676 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
9677 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
9679 I915_WRITE(MI_ARB_STATE,
9680 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
9683 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
9685 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
9687 /* interrupts should cause a wake up from C3 */
9688 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
9689 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
9691 I915_WRITE(MEM_MODE,
9692 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
9695 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
9697 I915_WRITE(MEM_MODE,
9698 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
9699 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
9702 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
9704 dev_priv->display.init_clock_gating(dev_priv);
9707 void intel_suspend_hw(struct drm_i915_private *dev_priv)
9709 if (HAS_PCH_LPT(dev_priv))
9710 lpt_suspend_hw(dev_priv);
9713 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
9715 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
9719 * intel_init_clock_gating_hooks - setup the clock gating hooks
9720 * @dev_priv: device private
9722 * Setup the hooks that configure which clocks of a given platform can be
9723 * gated and also apply various GT and display specific workarounds for these
9724 * platforms. Note that some GT specific workarounds are applied separately
9725 * when GPU contexts or batchbuffers start their execution.
9727 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
9729 if (IS_GEN(dev_priv, 12))
9730 dev_priv->display.init_clock_gating = nop_init_clock_gating;
9731 else if (IS_GEN(dev_priv, 11))
9732 dev_priv->display.init_clock_gating = icl_init_clock_gating;
9733 else if (IS_CANNONLAKE(dev_priv))
9734 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
9735 else if (IS_COFFEELAKE(dev_priv))
9736 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
9737 else if (IS_SKYLAKE(dev_priv))
9738 dev_priv->display.init_clock_gating = skl_init_clock_gating;
9739 else if (IS_KABYLAKE(dev_priv))
9740 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
9741 else if (IS_BROXTON(dev_priv))
9742 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
9743 else if (IS_GEMINILAKE(dev_priv))
9744 dev_priv->display.init_clock_gating = glk_init_clock_gating;
9745 else if (IS_BROADWELL(dev_priv))
9746 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
9747 else if (IS_CHERRYVIEW(dev_priv))
9748 dev_priv->display.init_clock_gating = chv_init_clock_gating;
9749 else if (IS_HASWELL(dev_priv))
9750 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
9751 else if (IS_IVYBRIDGE(dev_priv))
9752 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
9753 else if (IS_VALLEYVIEW(dev_priv))
9754 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
9755 else if (IS_GEN(dev_priv, 6))
9756 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9757 else if (IS_GEN(dev_priv, 5))
9758 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
9759 else if (IS_G4X(dev_priv))
9760 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9761 else if (IS_I965GM(dev_priv))
9762 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
9763 else if (IS_I965G(dev_priv))
9764 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
9765 else if (IS_GEN(dev_priv, 3))
9766 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9767 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
9768 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9769 else if (IS_GEN(dev_priv, 2))
9770 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9772 MISSING_CASE(INTEL_DEVID(dev_priv));
9773 dev_priv->display.init_clock_gating = nop_init_clock_gating;
9777 /* Set up chip specific power management-related functions */
9778 void intel_init_pm(struct drm_i915_private *dev_priv)
9781 if (IS_PINEVIEW(dev_priv))
9782 i915_pineview_get_mem_freq(dev_priv);
9783 else if (IS_GEN(dev_priv, 5))
9784 i915_ironlake_get_mem_freq(dev_priv);
9786 /* For FIFO watermark updates */
9787 if (INTEL_GEN(dev_priv) >= 9) {
9788 skl_setup_wm_latency(dev_priv);
9789 dev_priv->display.initial_watermarks = skl_initial_wm;
9790 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
9791 dev_priv->display.compute_global_watermarks = skl_compute_wm;
9792 } else if (HAS_PCH_SPLIT(dev_priv)) {
9793 ilk_setup_wm_latency(dev_priv);
9795 if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
9796 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
9797 (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
9798 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
9799 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
9800 dev_priv->display.compute_intermediate_wm =
9801 ilk_compute_intermediate_wm;
9802 dev_priv->display.initial_watermarks =
9803 ilk_initial_watermarks;
9804 dev_priv->display.optimize_watermarks =
9805 ilk_optimize_watermarks;
9807 DRM_DEBUG_KMS("Failed to read display plane latency. "
9810 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9811 vlv_setup_wm_latency(dev_priv);
9812 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
9813 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
9814 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
9815 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
9816 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
9817 } else if (IS_G4X(dev_priv)) {
9818 g4x_setup_wm_latency(dev_priv);
9819 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
9820 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
9821 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
9822 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
9823 } else if (IS_PINEVIEW(dev_priv)) {
9824 if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
9827 dev_priv->mem_freq)) {
9828 DRM_INFO("failed to find known CxSR latency "
9829 "(found ddr%s fsb freq %d, mem freq %d), "
9831 (dev_priv->is_ddr3 == 1) ? "3" : "2",
9832 dev_priv->fsb_freq, dev_priv->mem_freq);
9833 /* Disable CxSR and never update its watermark again */
9834 intel_set_memory_cxsr(dev_priv, false);
9835 dev_priv->display.update_wm = NULL;
9837 dev_priv->display.update_wm = pineview_update_wm;
9838 } else if (IS_GEN(dev_priv, 4)) {
9839 dev_priv->display.update_wm = i965_update_wm;
9840 } else if (IS_GEN(dev_priv, 3)) {
9841 dev_priv->display.update_wm = i9xx_update_wm;
9842 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9843 } else if (IS_GEN(dev_priv, 2)) {
9844 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
9845 dev_priv->display.update_wm = i845_update_wm;
9846 dev_priv->display.get_fifo_size = i845_get_fifo_size;
9848 dev_priv->display.update_wm = i9xx_update_wm;
9849 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9852 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
9856 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
9858 struct intel_rps *rps = &dev_priv->gt_pm.rps;
9862 * Slow = Fast = GPLL ref * N
9864 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000);
9867 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
9869 struct intel_rps *rps = &dev_priv->gt_pm.rps;
9871 return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
9874 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
9876 struct intel_rps *rps = &dev_priv->gt_pm.rps;
9880 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9882 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000);
9885 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
9887 struct intel_rps *rps = &dev_priv->gt_pm.rps;
9889 /* CHV needs even values */
9890 return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
9893 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
9895 if (INTEL_GEN(dev_priv) >= 9)
9896 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
9898 else if (IS_CHERRYVIEW(dev_priv))
9899 return chv_gpu_freq(dev_priv, val);
9900 else if (IS_VALLEYVIEW(dev_priv))
9901 return byt_gpu_freq(dev_priv, val);
9903 return val * GT_FREQUENCY_MULTIPLIER;
9906 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
9908 if (INTEL_GEN(dev_priv) >= 9)
9909 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
9910 GT_FREQUENCY_MULTIPLIER);
9911 else if (IS_CHERRYVIEW(dev_priv))
9912 return chv_freq_opcode(dev_priv, val);
9913 else if (IS_VALLEYVIEW(dev_priv))
9914 return byt_freq_opcode(dev_priv, val);
9916 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
9919 void intel_pm_setup(struct drm_i915_private *dev_priv)
9921 mutex_init(&dev_priv->gt_pm.rps.lock);
9922 mutex_init(&dev_priv->gt_pm.rps.power.mutex);
9924 atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);
9926 dev_priv->runtime_pm.suspended = false;
9927 atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
9930 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
9931 const i915_reg_t reg)
9933 u32 lower, upper, tmp;
9937 * The register accessed do not need forcewake. We borrow
9938 * uncore lock to prevent concurrent access to range reg.
9940 lockdep_assert_held(&dev_priv->uncore.lock);
9943 * vlv and chv residency counters are 40 bits in width.
9944 * With a control bit, we can choose between upper or lower
9945 * 32bit window into this counter.
9947 * Although we always use the counter in high-range mode elsewhere,
9948 * userspace may attempt to read the value before rc6 is initialised,
9949 * before we have set the default VLV_COUNTER_CONTROL value. So always
9950 * set the high bit to be safe.
9952 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9953 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9954 upper = I915_READ_FW(reg);
9958 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9959 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
9960 lower = I915_READ_FW(reg);
9962 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9963 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9964 upper = I915_READ_FW(reg);
9965 } while (upper != tmp && --loop);
9968 * Everywhere else we always use VLV_COUNTER_CONTROL with the
9969 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9973 return lower | (u64)upper << 8;
9976 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
9977 const i915_reg_t reg)
9979 struct intel_uncore *uncore = &dev_priv->uncore;
9980 u64 time_hw, prev_hw, overflow_hw;
9981 unsigned int fw_domains;
9982 unsigned long flags;
9986 if (!HAS_RC6(dev_priv))
9990 * Store previous hw counter values for counter wrap-around handling.
9992 * There are only four interesting registers and they live next to each
9993 * other so we can use the relative address, compared to the smallest
9994 * one as the index into driver storage.
9996 i = (i915_mmio_reg_offset(reg) -
9997 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
9998 if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
10001 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
10003 spin_lock_irqsave(&uncore->lock, flags);
10004 intel_uncore_forcewake_get__locked(uncore, fw_domains);
10006 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
10007 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10009 div = dev_priv->czclk_freq;
10010 overflow_hw = BIT_ULL(40);
10011 time_hw = vlv_residency_raw(dev_priv, reg);
10013 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
10014 if (IS_GEN9_LP(dev_priv)) {
10022 overflow_hw = BIT_ULL(32);
10023 time_hw = intel_uncore_read_fw(uncore, reg);
10027 * Counter wrap handling.
10029 * But relying on a sufficient frequency of queries otherwise counters
10032 prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
10033 dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
10035 /* RC6 delta from last sample. */
10036 if (time_hw >= prev_hw)
10037 time_hw -= prev_hw;
10039 time_hw += overflow_hw - prev_hw;
10041 /* Add delta to RC6 extended raw driver copy. */
10042 time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
10043 dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
10045 intel_uncore_forcewake_put__locked(uncore, fw_domains);
10046 spin_unlock_irqrestore(&uncore->lock, flags);
10048 return mul_u64_u32_div(time_hw, mul, div);
10051 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
10054 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
10057 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
10061 if (INTEL_GEN(dev_priv) >= 9)
10062 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
10063 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
10064 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
10066 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;