drivers/gpu/drm/i915/intel_huc_fw.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2014-2018 Intel Corporation
   5  */
   6
   7 #include "intel_huc_fw.h"
   8 #include "i915_drv.h"
   9
  10 /**
  11  * DOC: HuC Firmware
  12  *
  13  * Motivation:
  14  * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
  15  * Efficiency Video Coding) operations. Userspace can use the firmware
  16  * capabilities by adding HuC specific commands to batch buffers.
  17  *
  18  * Implementation:
  19  * The same firmware loader is used as the GuC. However, the actual
  20  * loading to HW is deferred until GEM initialization is done.
  21  *
  22  * Note that HuC firmware loading must be done before GuC loading.
  23  */
  24
  25 #define BXT_HUC_FW_MAJOR 01
  26 #define BXT_HUC_FW_MINOR 8
  27 #define BXT_BLD_NUM 2893
  28
  29 #define SKL_HUC_FW_MAJOR 01
  30 #define SKL_HUC_FW_MINOR 07
  31 #define SKL_BLD_NUM 1398
  32
  33 #define KBL_HUC_FW_MAJOR 02
  34 #define KBL_HUC_FW_MINOR 00
  35 #define KBL_BLD_NUM 1810
  36
  37 #define GLK_HUC_FW_MAJOR 03
  38 #define GLK_HUC_FW_MINOR 01
  39 #define GLK_BLD_NUM 2893
  40
  41 #define ICL_HUC_FW_MAJOR 8
  42 #define ICL_HUC_FW_MINOR 4
  43 #define ICL_BLD_NUM 3238
  44
  45 #define HUC_FW_PATH(platform, major, minor, bld_num) \
  46         "/*(DEBLOBBED)*/"
  47
  48 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
  49         SKL_HUC_FW_MINOR, SKL_BLD_NUM)
  50 /*(DEBLOBBED)*/
  51
  52 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
  53         BXT_HUC_FW_MINOR, BXT_BLD_NUM)
  54 /*(DEBLOBBED)*/
  55
  56 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
  57         KBL_HUC_FW_MINOR, KBL_BLD_NUM)
  58 /*(DEBLOBBED)*/
  59
  60 #define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
  61         GLK_HUC_FW_MINOR, GLK_BLD_NUM)
  62 /*(DEBLOBBED)*/
  63
  64 #define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \
  65         ICL_HUC_FW_MINOR, ICL_BLD_NUM)
  66 /*(DEBLOBBED)*/
  67
  68 static void huc_fw_select(struct intel_uc_fw *huc_fw)
  69 {
  70         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
  71         struct drm_i915_private *dev_priv = huc_to_i915(huc);
  72
  73         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
  74
  75         if (!HAS_HUC(dev_priv))
  76                 return;
  77
  78         if (i915_modparams.huc_firmware_path) {
  79                 huc_fw->path = i915_modparams.huc_firmware_path;
  80                 huc_fw->major_ver_wanted = 0;
  81                 huc_fw->minor_ver_wanted = 0;
  82         } else if (IS_SKYLAKE(dev_priv)) {
  83                 huc_fw->path = I915_SKL_HUC_UCODE;
  84                 huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
  85                 huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
  86         } else if (IS_BROXTON(dev_priv)) {
  87                 huc_fw->path = I915_BXT_HUC_UCODE;
  88                 huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
  89                 huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
  90         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
  91                 huc_fw->path = I915_KBL_HUC_UCODE;
  92                 huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
  93                 huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
  94         } else if (IS_GEMINILAKE(dev_priv)) {
  95                 huc_fw->path = I915_GLK_HUC_UCODE;
  96                 huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
  97                 huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
  98         } else if (IS_ICELAKE(dev_priv)) {
  99                 huc_fw->path = I915_ICL_HUC_UCODE;
 100                 huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
 101                 huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
 102         }
 103 }
 104
 105 /**
 106  * intel_huc_fw_init_early() - initializes HuC firmware struct
 107  * @huc: intel_huc struct
 108  *
 109  * On platforms with HuC selects firmware for uploading
 110  */
 111 void intel_huc_fw_init_early(struct intel_huc *huc)
 112 {
 113         struct intel_uc_fw *huc_fw = &huc->fw;
 114
 115         intel_uc_fw_init_early(huc_fw, INTEL_UC_FW_TYPE_HUC);
 116         huc_fw_select(huc_fw);
 117 }
 118
 119 static void huc_xfer_rsa(struct intel_huc *huc)
 120 {
 121         struct intel_uc_fw *fw = &huc->fw;
 122         struct sg_table *pages = fw->obj->mm.pages;
 123
 124         /*
 125          * HuC firmware image is outside GuC accessible range.
 126          * Copy the RSA signature out of the image into
 127          * the perma-pinned region set aside for it
 128          */
 129         sg_pcopy_to_buffer(pages->sgl, pages->nents,
 130                            huc->rsa_data_vaddr, fw->rsa_size,
 131                            fw->rsa_offset);
 132 }
 133
 134 static int huc_xfer_ucode(struct intel_huc *huc)
 135 {
 136         struct intel_uc_fw *huc_fw = &huc->fw;
 137         struct drm_i915_private *dev_priv = huc_to_i915(huc);
 138         struct intel_uncore *uncore = &dev_priv->uncore;
 139         unsigned long offset = 0;
 140         u32 size;
 141         int ret;
 142
 143         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 144
 145         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 146
 147         /* Set the source address for the uCode */
 148         offset = intel_uc_fw_ggtt_offset(huc_fw) +
 149                  huc_fw->header_offset;
 150         intel_uncore_write(uncore, DMA_ADDR_0_LOW,
 151                            lower_32_bits(offset));
 152         intel_uncore_write(uncore, DMA_ADDR_0_HIGH,
 153                            upper_32_bits(offset) & 0xFFFF);
 154
 155         /*
 156          * Hardware doesn't look at destination address for HuC. Set it to 0,
 157          * but still program the correct address space.
 158          */
 159         intel_uncore_write(uncore, DMA_ADDR_1_LOW, 0);
 160         intel_uncore_write(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 161
 162         size = huc_fw->header_size + huc_fw->ucode_size;
 163         intel_uncore_write(uncore, DMA_COPY_SIZE, size);
 164
 165         /* Start the DMA */
 166         intel_uncore_write(uncore, DMA_CTRL,
 167                            _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
 168
 169         /* Wait for DMA to finish */
 170         ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
 171
 172         DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
 173
 174         /* Disable the bits once DMA is over */
 175         intel_uncore_write(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
 176
 177         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 178
 179         return ret;
 180 }
 181
 182 /**
 183  * huc_fw_xfer() - DMA's the firmware
 184  * @huc_fw: the firmware descriptor
 185  *
 186  * Transfer the firmware image to RAM for execution by the microcontroller.
 187  *
 188  * Return: 0 on success, non-zero on failure
 189  */
 190 static int huc_fw_xfer(struct intel_uc_fw *huc_fw)
 191 {
 192         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
 193
 194         huc_xfer_rsa(huc);
 195
 196         return huc_xfer_ucode(huc);
 197 }
 198
 199 /**
 200  * intel_huc_fw_upload() - load HuC uCode to device
 201  * @huc: intel_huc structure
 202  *
 203  * Called from intel_uc_init_hw() during driver load, resume from sleep and
 204  * after a GPU reset. Note that HuC must be loaded before GuC.
 205  *
 206  * The firmware image should have already been fetched into memory, so only
 207  * check that fetch succeeded, and then transfer the image to the h/w.
 208  *
 209  * Return:      non-zero code on error
 210  */
 211 int intel_huc_fw_upload(struct intel_huc *huc)
 212 {
 213         return intel_uc_fw_upload(&huc->fw, huc_fw_xfer);
 214 }