drivers/gpu/drm/i915/i915_suspend.c

   1 /*
   2  *
   3  * Copyright 2008 (c) Intel Corporation
   4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include <drm/i915_drm.h>
  28
  29 #include "display/intel_fbc.h"
  30 #include "display/intel_gmbus.h"
  31
  32 #include "i915_reg.h"
  33 #include "intel_drv.h"
  34
  35 static void i915_save_display(struct drm_i915_private *dev_priv)
  36 {
  37         /* Display arbitration control */
  38         if (INTEL_GEN(dev_priv) <= 4)
  39                 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
  40
  41         /* save FBC interval */
  42         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
  43                 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
  44 }
  45
  46 static void i915_restore_display(struct drm_i915_private *dev_priv)
  47 {
  48         /* Display arbitration */
  49         if (INTEL_GEN(dev_priv) <= 4)
  50                 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
  51
  52         /* only restore FBC info on the platform that supports FBC*/
  53         intel_fbc_global_disable(dev_priv);
  54
  55         /* restore FBC interval */
  56         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
  57                 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
  58
  59         i915_redisable_vga(dev_priv);
  60 }
  61
  62 int i915_save_state(struct drm_i915_private *dev_priv)
  63 {
  64         struct pci_dev *pdev = dev_priv->drm.pdev;
  65         int i;
  66
  67         mutex_lock(&dev_priv->drm.struct_mutex);
  68
  69         i915_save_display(dev_priv);
  70
  71         if (IS_GEN(dev_priv, 4))
  72                 pci_read_config_word(pdev, GCDGMBUS,
  73                                      &dev_priv->regfile.saveGCDGMBUS);
  74
  75         /* Cache mode state */
  76         if (INTEL_GEN(dev_priv) < 7)
  77                 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
  78
  79         /* Memory Arbitration state */
  80         dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
  81
  82         /* Scratch space */
  83         if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
  84                 for (i = 0; i < 7; i++) {
  85                         dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
  86                         dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
  87                 }
  88                 for (i = 0; i < 3; i++)
  89                         dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
  90         } else if (IS_GEN(dev_priv, 2)) {
  91                 for (i = 0; i < 7; i++)
  92                         dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
  93         } else if (HAS_GMCH(dev_priv)) {
  94                 for (i = 0; i < 16; i++) {
  95                         dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
  96                         dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
  97                 }
  98                 for (i = 0; i < 3; i++)
  99                         dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
 100         }
 101
 102         mutex_unlock(&dev_priv->drm.struct_mutex);
 103
 104         return 0;
 105 }
 106
 107 int i915_restore_state(struct drm_i915_private *dev_priv)
 108 {
 109         struct pci_dev *pdev = dev_priv->drm.pdev;
 110         int i;
 111
 112         mutex_lock(&dev_priv->drm.struct_mutex);
 113
 114         if (IS_GEN(dev_priv, 4))
 115                 pci_write_config_word(pdev, GCDGMBUS,
 116                                       dev_priv->regfile.saveGCDGMBUS);
 117         i915_restore_display(dev_priv);
 118
 119         /* Cache mode state */
 120         if (INTEL_GEN(dev_priv) < 7)
 121                 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
 122                            0xffff0000);
 123
 124         /* Memory arbitration state */
 125         I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
 126
 127         /* Scratch space */
 128         if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
 129                 for (i = 0; i < 7; i++) {
 130                         I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
 131                         I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
 132                 }
 133                 for (i = 0; i < 3; i++)
 134                         I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
 135         } else if (IS_GEN(dev_priv, 2)) {
 136                 for (i = 0; i < 7; i++)
 137                         I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
 138         } else if (HAS_GMCH(dev_priv)) {
 139                 for (i = 0; i < 16; i++) {
 140                         I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
 141                         I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
 142                 }
 143                 for (i = 0; i < 3; i++)
 144                         I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
 145         }
 146
 147         mutex_unlock(&dev_priv->drm.struct_mutex);
 148
 149         intel_gmbus_reset(dev_priv);
 150
 151         return 0;
 152 }