2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/debugfs.h>
30 #include <linux/sort.h>
31 #include <linux/sched/mm.h>
32 #include "intel_drv.h"
33 #include "i915_guc_submission.h"
35 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
37 return to_i915(node->minor->dev);
40 static __always_inline void seq_print_param(struct seq_file *m,
45 if (!__builtin_strcmp(type, "bool"))
46 seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
47 else if (!__builtin_strcmp(type, "int"))
48 seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
49 else if (!__builtin_strcmp(type, "unsigned int"))
50 seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
51 else if (!__builtin_strcmp(type, "char *"))
52 seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
57 static int i915_capabilities(struct seq_file *m, void *data)
59 struct drm_i915_private *dev_priv = node_to_i915(m->private);
60 const struct intel_device_info *info = INTEL_INFO(dev_priv);
62 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
63 seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
64 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
66 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
67 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
70 kernel_param_lock(THIS_MODULE);
71 #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
72 I915_PARAMS_FOR_EACH(PRINT_PARAM);
74 kernel_param_unlock(THIS_MODULE);
79 static char get_active_flag(struct drm_i915_gem_object *obj)
81 return i915_gem_object_is_active(obj) ? '*' : ' ';
84 static char get_pin_flag(struct drm_i915_gem_object *obj)
86 return obj->pin_global ? 'p' : ' ';
89 static char get_tiling_flag(struct drm_i915_gem_object *obj)
91 switch (i915_gem_object_get_tiling(obj)) {
93 case I915_TILING_NONE: return ' ';
94 case I915_TILING_X: return 'X';
95 case I915_TILING_Y: return 'Y';
99 static char get_global_flag(struct drm_i915_gem_object *obj)
101 return obj->userfault_count ? 'g' : ' ';
104 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
106 return obj->mm.mapping ? 'M' : ' ';
109 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
112 struct i915_vma *vma;
114 list_for_each_entry(vma, &obj->vma_list, obj_link) {
115 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
116 size += vma->node.size;
123 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
127 switch (page_sizes) {
130 case I915_GTT_PAGE_SIZE_4K:
132 case I915_GTT_PAGE_SIZE_64K:
134 case I915_GTT_PAGE_SIZE_2M:
140 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
141 x += snprintf(buf + x, len - x, "2M, ");
142 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
143 x += snprintf(buf + x, len - x, "64K, ");
144 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
145 x += snprintf(buf + x, len - x, "4K, ");
153 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
155 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
156 struct intel_engine_cs *engine;
157 struct i915_vma *vma;
158 unsigned int frontbuffer_bits;
161 lockdep_assert_held(&obj->base.dev->struct_mutex);
163 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
165 get_active_flag(obj),
167 get_tiling_flag(obj),
168 get_global_flag(obj),
169 get_pin_mapped_flag(obj),
170 obj->base.size / 1024,
171 obj->base.read_domains,
172 obj->base.write_domain,
173 i915_cache_level_str(dev_priv, obj->cache_level),
174 obj->mm.dirty ? " dirty" : "",
175 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
177 seq_printf(m, " (name: %d)", obj->base.name);
178 list_for_each_entry(vma, &obj->vma_list, obj_link) {
179 if (i915_vma_is_pinned(vma))
182 seq_printf(m, " (pinned x %d)", pin_count);
184 seq_printf(m, " (global)");
185 list_for_each_entry(vma, &obj->vma_list, obj_link) {
186 if (!drm_mm_node_allocated(&vma->node))
189 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
190 i915_vma_is_ggtt(vma) ? "g" : "pp",
191 vma->node.start, vma->node.size,
192 stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
193 if (i915_vma_is_ggtt(vma)) {
194 switch (vma->ggtt_view.type) {
195 case I915_GGTT_VIEW_NORMAL:
196 seq_puts(m, ", normal");
199 case I915_GGTT_VIEW_PARTIAL:
200 seq_printf(m, ", partial [%08llx+%x]",
201 vma->ggtt_view.partial.offset << PAGE_SHIFT,
202 vma->ggtt_view.partial.size << PAGE_SHIFT);
205 case I915_GGTT_VIEW_ROTATED:
206 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
207 vma->ggtt_view.rotated.plane[0].width,
208 vma->ggtt_view.rotated.plane[0].height,
209 vma->ggtt_view.rotated.plane[0].stride,
210 vma->ggtt_view.rotated.plane[0].offset,
211 vma->ggtt_view.rotated.plane[1].width,
212 vma->ggtt_view.rotated.plane[1].height,
213 vma->ggtt_view.rotated.plane[1].stride,
214 vma->ggtt_view.rotated.plane[1].offset);
218 MISSING_CASE(vma->ggtt_view.type);
223 seq_printf(m, " , fence: %d%s",
225 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
229 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
231 engine = i915_gem_object_last_write_engine(obj);
233 seq_printf(m, " (%s)", engine->name);
235 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
236 if (frontbuffer_bits)
237 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
240 static int obj_rank_by_stolen(const void *A, const void *B)
242 const struct drm_i915_gem_object *a =
243 *(const struct drm_i915_gem_object **)A;
244 const struct drm_i915_gem_object *b =
245 *(const struct drm_i915_gem_object **)B;
247 if (a->stolen->start < b->stolen->start)
249 if (a->stolen->start > b->stolen->start)
254 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
256 struct drm_i915_private *dev_priv = node_to_i915(m->private);
257 struct drm_device *dev = &dev_priv->drm;
258 struct drm_i915_gem_object **objects;
259 struct drm_i915_gem_object *obj;
260 u64 total_obj_size, total_gtt_size;
261 unsigned long total, count, n;
264 total = READ_ONCE(dev_priv->mm.object_count);
265 objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
269 ret = mutex_lock_interruptible(&dev->struct_mutex);
273 total_obj_size = total_gtt_size = count = 0;
275 spin_lock(&dev_priv->mm.obj_lock);
276 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
280 if (obj->stolen == NULL)
283 objects[count++] = obj;
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
292 if (obj->stolen == NULL)
295 objects[count++] = obj;
296 total_obj_size += obj->base.size;
298 spin_unlock(&dev_priv->mm.obj_lock);
300 sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
302 seq_puts(m, "Stolen:\n");
303 for (n = 0; n < count; n++) {
305 describe_obj(m, objects[n]);
308 seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
311 mutex_unlock(&dev->struct_mutex);
318 struct drm_i915_file_private *file_priv;
322 u64 active, inactive;
325 static int per_file_stats(int id, void *ptr, void *data)
327 struct drm_i915_gem_object *obj = ptr;
328 struct file_stats *stats = data;
329 struct i915_vma *vma;
331 lockdep_assert_held(&obj->base.dev->struct_mutex);
334 stats->total += obj->base.size;
335 if (!obj->bind_count)
336 stats->unbound += obj->base.size;
337 if (obj->base.name || obj->base.dma_buf)
338 stats->shared += obj->base.size;
340 list_for_each_entry(vma, &obj->vma_list, obj_link) {
341 if (!drm_mm_node_allocated(&vma->node))
344 if (i915_vma_is_ggtt(vma)) {
345 stats->global += vma->node.size;
347 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
349 if (ppgtt->base.file != stats->file_priv)
353 if (i915_vma_is_active(vma))
354 stats->active += vma->node.size;
356 stats->inactive += vma->node.size;
362 #define print_file_stats(m, name, stats) do { \
364 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
375 static void print_batch_pool_stats(struct seq_file *m,
376 struct drm_i915_private *dev_priv)
378 struct drm_i915_gem_object *obj;
379 struct file_stats stats;
380 struct intel_engine_cs *engine;
381 enum intel_engine_id id;
384 memset(&stats, 0, sizeof(stats));
386 for_each_engine(engine, dev_priv, id) {
387 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
388 list_for_each_entry(obj,
389 &engine->batch_pool.cache_list[j],
391 per_file_stats(0, obj, &stats);
395 print_file_stats(m, "[k]batch pool", stats);
398 static int per_file_ctx_stats(int id, void *ptr, void *data)
400 struct i915_gem_context *ctx = ptr;
403 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
404 if (ctx->engine[n].state)
405 per_file_stats(0, ctx->engine[n].state->obj, data);
406 if (ctx->engine[n].ring)
407 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
413 static void print_context_stats(struct seq_file *m,
414 struct drm_i915_private *dev_priv)
416 struct drm_device *dev = &dev_priv->drm;
417 struct file_stats stats;
418 struct drm_file *file;
420 memset(&stats, 0, sizeof(stats));
422 mutex_lock(&dev->struct_mutex);
423 if (dev_priv->kernel_context)
424 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
426 list_for_each_entry(file, &dev->filelist, lhead) {
427 struct drm_i915_file_private *fpriv = file->driver_priv;
428 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
430 mutex_unlock(&dev->struct_mutex);
432 print_file_stats(m, "[k]contexts", stats);
435 static int i915_gem_object_info(struct seq_file *m, void *data)
437 struct drm_i915_private *dev_priv = node_to_i915(m->private);
438 struct drm_device *dev = &dev_priv->drm;
439 struct i915_ggtt *ggtt = &dev_priv->ggtt;
440 u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
441 u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
442 struct drm_i915_gem_object *obj;
443 unsigned int page_sizes = 0;
444 struct drm_file *file;
448 ret = mutex_lock_interruptible(&dev->struct_mutex);
452 seq_printf(m, "%u objects, %llu bytes\n",
453 dev_priv->mm.object_count,
454 dev_priv->mm.object_memory);
457 mapped_size = mapped_count = 0;
458 purgeable_size = purgeable_count = 0;
459 huge_size = huge_count = 0;
461 spin_lock(&dev_priv->mm.obj_lock);
462 list_for_each_entry(obj, &dev_priv->mm.unbound_list, mm.link) {
463 size += obj->base.size;
466 if (obj->mm.madv == I915_MADV_DONTNEED) {
467 purgeable_size += obj->base.size;
471 if (obj->mm.mapping) {
473 mapped_size += obj->base.size;
476 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
478 huge_size += obj->base.size;
479 page_sizes |= obj->mm.page_sizes.sg;
482 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
484 size = count = dpy_size = dpy_count = 0;
485 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
486 size += obj->base.size;
489 if (obj->pin_global) {
490 dpy_size += obj->base.size;
494 if (obj->mm.madv == I915_MADV_DONTNEED) {
495 purgeable_size += obj->base.size;
499 if (obj->mm.mapping) {
501 mapped_size += obj->base.size;
504 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
506 huge_size += obj->base.size;
507 page_sizes |= obj->mm.page_sizes.sg;
510 spin_unlock(&dev_priv->mm.obj_lock);
512 seq_printf(m, "%u bound objects, %llu bytes\n",
514 seq_printf(m, "%u purgeable objects, %llu bytes\n",
515 purgeable_count, purgeable_size);
516 seq_printf(m, "%u mapped objects, %llu bytes\n",
517 mapped_count, mapped_size);
518 seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
520 stringify_page_sizes(page_sizes, buf, sizeof(buf)),
522 seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
523 dpy_count, dpy_size);
525 seq_printf(m, "%llu [%llu] gtt total\n",
526 ggtt->base.total, ggtt->mappable_end);
527 seq_printf(m, "Supported page sizes: %s\n",
528 stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
532 print_batch_pool_stats(m, dev_priv);
533 mutex_unlock(&dev->struct_mutex);
535 mutex_lock(&dev->filelist_mutex);
536 print_context_stats(m, dev_priv);
537 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
538 struct file_stats stats;
539 struct drm_i915_file_private *file_priv = file->driver_priv;
540 struct drm_i915_gem_request *request;
541 struct task_struct *task;
543 mutex_lock(&dev->struct_mutex);
545 memset(&stats, 0, sizeof(stats));
546 stats.file_priv = file->driver_priv;
547 spin_lock(&file->table_lock);
548 idr_for_each(&file->object_idr, per_file_stats, &stats);
549 spin_unlock(&file->table_lock);
551 * Although we have a valid reference on file->pid, that does
552 * not guarantee that the task_struct who called get_pid() is
553 * still alive (e.g. get_pid(current) => fork() => exit()).
554 * Therefore, we need to protect this ->comm access using RCU.
556 request = list_first_entry_or_null(&file_priv->mm.request_list,
557 struct drm_i915_gem_request,
560 task = pid_task(request && request->ctx->pid ?
561 request->ctx->pid : file->pid,
563 print_file_stats(m, task ? task->comm : "<unknown>", stats);
566 mutex_unlock(&dev->struct_mutex);
568 mutex_unlock(&dev->filelist_mutex);
573 static int i915_gem_gtt_info(struct seq_file *m, void *data)
575 struct drm_info_node *node = m->private;
576 struct drm_i915_private *dev_priv = node_to_i915(node);
577 struct drm_device *dev = &dev_priv->drm;
578 struct drm_i915_gem_object **objects;
579 struct drm_i915_gem_object *obj;
580 u64 total_obj_size, total_gtt_size;
581 unsigned long nobject, n;
584 nobject = READ_ONCE(dev_priv->mm.object_count);
585 objects = kvmalloc_array(nobject, sizeof(*objects), GFP_KERNEL);
589 ret = mutex_lock_interruptible(&dev->struct_mutex);
594 spin_lock(&dev_priv->mm.obj_lock);
595 list_for_each_entry(obj, &dev_priv->mm.bound_list, mm.link) {
596 objects[count++] = obj;
597 if (count == nobject)
600 spin_unlock(&dev_priv->mm.obj_lock);
602 total_obj_size = total_gtt_size = 0;
603 for (n = 0; n < count; n++) {
607 describe_obj(m, obj);
609 total_obj_size += obj->base.size;
610 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
613 mutex_unlock(&dev->struct_mutex);
615 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
616 count, total_obj_size, total_gtt_size);
622 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
624 struct drm_i915_private *dev_priv = node_to_i915(m->private);
625 struct drm_device *dev = &dev_priv->drm;
626 struct drm_i915_gem_object *obj;
627 struct intel_engine_cs *engine;
628 enum intel_engine_id id;
632 ret = mutex_lock_interruptible(&dev->struct_mutex);
636 for_each_engine(engine, dev_priv, id) {
637 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
641 list_for_each_entry(obj,
642 &engine->batch_pool.cache_list[j],
645 seq_printf(m, "%s cache[%d]: %d objects\n",
646 engine->name, j, count);
648 list_for_each_entry(obj,
649 &engine->batch_pool.cache_list[j],
652 describe_obj(m, obj);
660 seq_printf(m, "total: %d\n", total);
662 mutex_unlock(&dev->struct_mutex);
667 static void i915_ring_seqno_info(struct seq_file *m,
668 struct intel_engine_cs *engine)
670 struct intel_breadcrumbs *b = &engine->breadcrumbs;
673 seq_printf(m, "Current sequence (%s): %x\n",
674 engine->name, intel_engine_get_seqno(engine));
676 spin_lock_irq(&b->rb_lock);
677 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
678 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
680 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
681 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
683 spin_unlock_irq(&b->rb_lock);
686 static int i915_gem_seqno_info(struct seq_file *m, void *data)
688 struct drm_i915_private *dev_priv = node_to_i915(m->private);
689 struct intel_engine_cs *engine;
690 enum intel_engine_id id;
692 for_each_engine(engine, dev_priv, id)
693 i915_ring_seqno_info(m, engine);
699 static int i915_interrupt_info(struct seq_file *m, void *data)
701 struct drm_i915_private *dev_priv = node_to_i915(m->private);
702 struct intel_engine_cs *engine;
703 enum intel_engine_id id;
706 intel_runtime_pm_get(dev_priv);
708 if (IS_CHERRYVIEW(dev_priv)) {
709 seq_printf(m, "Master Interrupt Control:\t%08x\n",
710 I915_READ(GEN8_MASTER_IRQ));
712 seq_printf(m, "Display IER:\t%08x\n",
714 seq_printf(m, "Display IIR:\t%08x\n",
716 seq_printf(m, "Display IIR_RW:\t%08x\n",
717 I915_READ(VLV_IIR_RW));
718 seq_printf(m, "Display IMR:\t%08x\n",
720 for_each_pipe(dev_priv, pipe) {
721 enum intel_display_power_domain power_domain;
723 power_domain = POWER_DOMAIN_PIPE(pipe);
724 if (!intel_display_power_get_if_enabled(dev_priv,
726 seq_printf(m, "Pipe %c power disabled\n",
731 seq_printf(m, "Pipe %c stat:\t%08x\n",
733 I915_READ(PIPESTAT(pipe)));
735 intel_display_power_put(dev_priv, power_domain);
738 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
739 seq_printf(m, "Port hotplug:\t%08x\n",
740 I915_READ(PORT_HOTPLUG_EN));
741 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
742 I915_READ(VLV_DPFLIPSTAT));
743 seq_printf(m, "DPINVGTT:\t%08x\n",
744 I915_READ(DPINVGTT));
745 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
747 for (i = 0; i < 4; i++) {
748 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
749 i, I915_READ(GEN8_GT_IMR(i)));
750 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
751 i, I915_READ(GEN8_GT_IIR(i)));
752 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
753 i, I915_READ(GEN8_GT_IER(i)));
756 seq_printf(m, "PCU interrupt mask:\t%08x\n",
757 I915_READ(GEN8_PCU_IMR));
758 seq_printf(m, "PCU interrupt identity:\t%08x\n",
759 I915_READ(GEN8_PCU_IIR));
760 seq_printf(m, "PCU interrupt enable:\t%08x\n",
761 I915_READ(GEN8_PCU_IER));
762 } else if (INTEL_GEN(dev_priv) >= 8) {
763 seq_printf(m, "Master Interrupt Control:\t%08x\n",
764 I915_READ(GEN8_MASTER_IRQ));
766 for (i = 0; i < 4; i++) {
767 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
768 i, I915_READ(GEN8_GT_IMR(i)));
769 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
770 i, I915_READ(GEN8_GT_IIR(i)));
771 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
772 i, I915_READ(GEN8_GT_IER(i)));
775 for_each_pipe(dev_priv, pipe) {
776 enum intel_display_power_domain power_domain;
778 power_domain = POWER_DOMAIN_PIPE(pipe);
779 if (!intel_display_power_get_if_enabled(dev_priv,
781 seq_printf(m, "Pipe %c power disabled\n",
785 seq_printf(m, "Pipe %c IMR:\t%08x\n",
787 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
788 seq_printf(m, "Pipe %c IIR:\t%08x\n",
790 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
791 seq_printf(m, "Pipe %c IER:\t%08x\n",
793 I915_READ(GEN8_DE_PIPE_IER(pipe)));
795 intel_display_power_put(dev_priv, power_domain);
798 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
799 I915_READ(GEN8_DE_PORT_IMR));
800 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
801 I915_READ(GEN8_DE_PORT_IIR));
802 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
803 I915_READ(GEN8_DE_PORT_IER));
805 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
806 I915_READ(GEN8_DE_MISC_IMR));
807 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
808 I915_READ(GEN8_DE_MISC_IIR));
809 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
810 I915_READ(GEN8_DE_MISC_IER));
812 seq_printf(m, "PCU interrupt mask:\t%08x\n",
813 I915_READ(GEN8_PCU_IMR));
814 seq_printf(m, "PCU interrupt identity:\t%08x\n",
815 I915_READ(GEN8_PCU_IIR));
816 seq_printf(m, "PCU interrupt enable:\t%08x\n",
817 I915_READ(GEN8_PCU_IER));
818 } else if (IS_VALLEYVIEW(dev_priv)) {
819 seq_printf(m, "Display IER:\t%08x\n",
821 seq_printf(m, "Display IIR:\t%08x\n",
823 seq_printf(m, "Display IIR_RW:\t%08x\n",
824 I915_READ(VLV_IIR_RW));
825 seq_printf(m, "Display IMR:\t%08x\n",
827 for_each_pipe(dev_priv, pipe) {
828 enum intel_display_power_domain power_domain;
830 power_domain = POWER_DOMAIN_PIPE(pipe);
831 if (!intel_display_power_get_if_enabled(dev_priv,
833 seq_printf(m, "Pipe %c power disabled\n",
838 seq_printf(m, "Pipe %c stat:\t%08x\n",
840 I915_READ(PIPESTAT(pipe)));
841 intel_display_power_put(dev_priv, power_domain);
844 seq_printf(m, "Master IER:\t%08x\n",
845 I915_READ(VLV_MASTER_IER));
847 seq_printf(m, "Render IER:\t%08x\n",
849 seq_printf(m, "Render IIR:\t%08x\n",
851 seq_printf(m, "Render IMR:\t%08x\n",
854 seq_printf(m, "PM IER:\t\t%08x\n",
855 I915_READ(GEN6_PMIER));
856 seq_printf(m, "PM IIR:\t\t%08x\n",
857 I915_READ(GEN6_PMIIR));
858 seq_printf(m, "PM IMR:\t\t%08x\n",
859 I915_READ(GEN6_PMIMR));
861 seq_printf(m, "Port hotplug:\t%08x\n",
862 I915_READ(PORT_HOTPLUG_EN));
863 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
864 I915_READ(VLV_DPFLIPSTAT));
865 seq_printf(m, "DPINVGTT:\t%08x\n",
866 I915_READ(DPINVGTT));
868 } else if (!HAS_PCH_SPLIT(dev_priv)) {
869 seq_printf(m, "Interrupt enable: %08x\n",
871 seq_printf(m, "Interrupt identity: %08x\n",
873 seq_printf(m, "Interrupt mask: %08x\n",
875 for_each_pipe(dev_priv, pipe)
876 seq_printf(m, "Pipe %c stat: %08x\n",
878 I915_READ(PIPESTAT(pipe)));
880 seq_printf(m, "North Display Interrupt enable: %08x\n",
882 seq_printf(m, "North Display Interrupt identity: %08x\n",
884 seq_printf(m, "North Display Interrupt mask: %08x\n",
886 seq_printf(m, "South Display Interrupt enable: %08x\n",
888 seq_printf(m, "South Display Interrupt identity: %08x\n",
890 seq_printf(m, "South Display Interrupt mask: %08x\n",
892 seq_printf(m, "Graphics Interrupt enable: %08x\n",
894 seq_printf(m, "Graphics Interrupt identity: %08x\n",
896 seq_printf(m, "Graphics Interrupt mask: %08x\n",
899 for_each_engine(engine, dev_priv, id) {
900 if (INTEL_GEN(dev_priv) >= 6) {
902 "Graphics Interrupt mask (%s): %08x\n",
903 engine->name, I915_READ_IMR(engine));
905 i915_ring_seqno_info(m, engine);
907 intel_runtime_pm_put(dev_priv);
912 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
914 struct drm_i915_private *dev_priv = node_to_i915(m->private);
915 struct drm_device *dev = &dev_priv->drm;
918 ret = mutex_lock_interruptible(&dev->struct_mutex);
922 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
923 for (i = 0; i < dev_priv->num_fence_regs; i++) {
924 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
926 seq_printf(m, "Fence %d, pin count = %d, object = ",
927 i, dev_priv->fence_regs[i].pin_count);
929 seq_puts(m, "unused");
931 describe_obj(m, vma->obj);
935 mutex_unlock(&dev->struct_mutex);
939 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
940 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
941 size_t count, loff_t *pos)
943 struct i915_gpu_state *error = file->private_data;
944 struct drm_i915_error_state_buf str;
951 ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
955 ret = i915_error_state_to_str(&str, error);
960 ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
964 *pos = str.start + ret;
966 i915_error_state_buf_release(&str);
970 static int gpu_state_release(struct inode *inode, struct file *file)
972 i915_gpu_state_put(file->private_data);
976 static int i915_gpu_info_open(struct inode *inode, struct file *file)
978 struct drm_i915_private *i915 = inode->i_private;
979 struct i915_gpu_state *gpu;
981 intel_runtime_pm_get(i915);
982 gpu = i915_capture_gpu_state(i915);
983 intel_runtime_pm_put(i915);
987 file->private_data = gpu;
991 static const struct file_operations i915_gpu_info_fops = {
992 .owner = THIS_MODULE,
993 .open = i915_gpu_info_open,
994 .read = gpu_state_read,
995 .llseek = default_llseek,
996 .release = gpu_state_release,
1000 i915_error_state_write(struct file *filp,
1001 const char __user *ubuf,
1005 struct i915_gpu_state *error = filp->private_data;
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1011 i915_reset_error_state(error->i915);
1016 static int i915_error_state_open(struct inode *inode, struct file *file)
1018 file->private_data = i915_first_error_state(inode->i_private);
1022 static const struct file_operations i915_error_state_fops = {
1023 .owner = THIS_MODULE,
1024 .open = i915_error_state_open,
1025 .read = gpu_state_read,
1026 .write = i915_error_state_write,
1027 .llseek = default_llseek,
1028 .release = gpu_state_release,
1033 i915_next_seqno_set(void *data, u64 val)
1035 struct drm_i915_private *dev_priv = data;
1036 struct drm_device *dev = &dev_priv->drm;
1039 ret = mutex_lock_interruptible(&dev->struct_mutex);
1043 ret = i915_gem_set_global_seqno(dev, val);
1044 mutex_unlock(&dev->struct_mutex);
1049 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1050 NULL, i915_next_seqno_set,
1053 static int i915_frequency_info(struct seq_file *m, void *unused)
1055 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1056 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1059 intel_runtime_pm_get(dev_priv);
1061 if (IS_GEN5(dev_priv)) {
1062 u16 rgvswctl = I915_READ16(MEMSWCTL);
1063 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1065 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1066 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1067 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1069 seq_printf(m, "Current P-state: %d\n",
1070 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1071 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1072 u32 rpmodectl, freq_sts;
1074 mutex_lock(&dev_priv->pcu_lock);
1076 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1077 seq_printf(m, "Video Turbo Mode: %s\n",
1078 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1079 seq_printf(m, "HW control enabled: %s\n",
1080 yesno(rpmodectl & GEN6_RP_ENABLE));
1081 seq_printf(m, "SW control enabled: %s\n",
1082 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1083 GEN6_RP_MEDIA_SW_MODE));
1085 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1086 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1087 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1089 seq_printf(m, "actual GPU freq: %d MHz\n",
1090 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1092 seq_printf(m, "current GPU freq: %d MHz\n",
1093 intel_gpu_freq(dev_priv, rps->cur_freq));
1095 seq_printf(m, "max GPU freq: %d MHz\n",
1096 intel_gpu_freq(dev_priv, rps->max_freq));
1098 seq_printf(m, "min GPU freq: %d MHz\n",
1099 intel_gpu_freq(dev_priv, rps->min_freq));
1101 seq_printf(m, "idle GPU freq: %d MHz\n",
1102 intel_gpu_freq(dev_priv, rps->idle_freq));
1105 "efficient (RPe) frequency: %d MHz\n",
1106 intel_gpu_freq(dev_priv, rps->efficient_freq));
1107 mutex_unlock(&dev_priv->pcu_lock);
1108 } else if (INTEL_GEN(dev_priv) >= 6) {
1109 u32 rp_state_limits;
1112 u32 rpmodectl, rpinclimit, rpdeclimit;
1113 u32 rpstat, cagf, reqf;
1114 u32 rpupei, rpcurup, rpprevup;
1115 u32 rpdownei, rpcurdown, rpprevdown;
1116 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1119 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1120 if (IS_GEN9_LP(dev_priv)) {
1121 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1122 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1124 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1125 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1128 /* RPSTAT1 is in the GT power well */
1129 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1131 reqf = I915_READ(GEN6_RPNSWREQ);
1132 if (INTEL_GEN(dev_priv) >= 9)
1135 reqf &= ~GEN6_TURBO_DISABLE;
1136 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1141 reqf = intel_gpu_freq(dev_priv, reqf);
1143 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1144 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1145 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1147 rpstat = I915_READ(GEN6_RPSTAT1);
1148 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1149 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1150 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1151 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1152 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1153 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1154 if (INTEL_GEN(dev_priv) >= 9)
1155 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1156 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1157 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1159 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1160 cagf = intel_gpu_freq(dev_priv, cagf);
1162 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1164 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1165 pm_ier = I915_READ(GEN6_PMIER);
1166 pm_imr = I915_READ(GEN6_PMIMR);
1167 pm_isr = I915_READ(GEN6_PMISR);
1168 pm_iir = I915_READ(GEN6_PMIIR);
1169 pm_mask = I915_READ(GEN6_PMINTRMSK);
1171 pm_ier = I915_READ(GEN8_GT_IER(2));
1172 pm_imr = I915_READ(GEN8_GT_IMR(2));
1173 pm_isr = I915_READ(GEN8_GT_ISR(2));
1174 pm_iir = I915_READ(GEN8_GT_IIR(2));
1175 pm_mask = I915_READ(GEN6_PMINTRMSK);
1177 seq_printf(m, "Video Turbo Mode: %s\n",
1178 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1179 seq_printf(m, "HW control enabled: %s\n",
1180 yesno(rpmodectl & GEN6_RP_ENABLE));
1181 seq_printf(m, "SW control enabled: %s\n",
1182 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1183 GEN6_RP_MEDIA_SW_MODE));
1184 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1185 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1186 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1187 rps->pm_intrmsk_mbz);
1188 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1189 seq_printf(m, "Render p-state ratio: %d\n",
1190 (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1191 seq_printf(m, "Render p-state VID: %d\n",
1192 gt_perf_status & 0xff);
1193 seq_printf(m, "Render p-state limit: %d\n",
1194 rp_state_limits & 0xff);
1195 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1196 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1197 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1198 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1199 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1200 seq_printf(m, "CAGF: %dMHz\n", cagf);
1201 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1202 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1203 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1204 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1205 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1206 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1207 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
1209 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1210 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1211 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1212 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1213 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1214 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1215 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
1217 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1218 rp_state_cap >> 16) & 0xff;
1219 max_freq *= (IS_GEN9_BC(dev_priv) ||
1220 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1221 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1222 intel_gpu_freq(dev_priv, max_freq));
1224 max_freq = (rp_state_cap & 0xff00) >> 8;
1225 max_freq *= (IS_GEN9_BC(dev_priv) ||
1226 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1227 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1228 intel_gpu_freq(dev_priv, max_freq));
1230 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1231 rp_state_cap >> 0) & 0xff;
1232 max_freq *= (IS_GEN9_BC(dev_priv) ||
1233 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1234 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1235 intel_gpu_freq(dev_priv, max_freq));
1236 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1237 intel_gpu_freq(dev_priv, rps->max_freq));
1239 seq_printf(m, "Current freq: %d MHz\n",
1240 intel_gpu_freq(dev_priv, rps->cur_freq));
1241 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1242 seq_printf(m, "Idle freq: %d MHz\n",
1243 intel_gpu_freq(dev_priv, rps->idle_freq));
1244 seq_printf(m, "Min freq: %d MHz\n",
1245 intel_gpu_freq(dev_priv, rps->min_freq));
1246 seq_printf(m, "Boost freq: %d MHz\n",
1247 intel_gpu_freq(dev_priv, rps->boost_freq));
1248 seq_printf(m, "Max freq: %d MHz\n",
1249 intel_gpu_freq(dev_priv, rps->max_freq));
1251 "efficient (RPe) frequency: %d MHz\n",
1252 intel_gpu_freq(dev_priv, rps->efficient_freq));
1254 seq_puts(m, "no P-state info available\n");
1257 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1258 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1259 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1261 intel_runtime_pm_put(dev_priv);
1265 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1267 struct intel_instdone *instdone)
1272 seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1273 instdone->instdone);
1275 if (INTEL_GEN(dev_priv) <= 3)
1278 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1279 instdone->slice_common);
1281 if (INTEL_GEN(dev_priv) <= 6)
1284 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1285 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1286 slice, subslice, instdone->sampler[slice][subslice]);
1288 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1289 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1290 slice, subslice, instdone->row[slice][subslice]);
1293 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1295 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1296 struct intel_engine_cs *engine;
1297 u64 acthd[I915_NUM_ENGINES];
1298 u32 seqno[I915_NUM_ENGINES];
1299 struct intel_instdone instdone;
1300 enum intel_engine_id id;
1302 if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1303 seq_puts(m, "Wedged\n");
1304 if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1305 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1306 if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1307 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1308 if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1309 seq_puts(m, "Waiter holding struct mutex\n");
1310 if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1311 seq_puts(m, "struct_mutex blocked for reset\n");
1313 if (!i915_modparams.enable_hangcheck) {
1314 seq_puts(m, "Hangcheck disabled\n");
1318 intel_runtime_pm_get(dev_priv);
1320 for_each_engine(engine, dev_priv, id) {
1321 acthd[id] = intel_engine_get_active_head(engine);
1322 seqno[id] = intel_engine_get_seqno(engine);
1325 intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1327 intel_runtime_pm_put(dev_priv);
1329 if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1330 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1331 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1333 else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1334 seq_puts(m, "Hangcheck active, work pending\n");
1336 seq_puts(m, "Hangcheck inactive\n");
1338 seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1340 for_each_engine(engine, dev_priv, id) {
1341 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1344 seq_printf(m, "%s:\n", engine->name);
1345 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1346 engine->hangcheck.seqno, seqno[id],
1347 intel_engine_last_submit(engine),
1348 engine->timeline->inflight_seqnos);
1349 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1350 yesno(intel_engine_has_waiter(engine)),
1351 yesno(test_bit(engine->id,
1352 &dev_priv->gpu_error.missed_irq_rings)),
1353 yesno(engine->hangcheck.stalled));
1355 spin_lock_irq(&b->rb_lock);
1356 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1357 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1359 seq_printf(m, "\t%s [%d] waiting for %x\n",
1360 w->tsk->comm, w->tsk->pid, w->seqno);
1362 spin_unlock_irq(&b->rb_lock);
1364 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1365 (long long)engine->hangcheck.acthd,
1366 (long long)acthd[id]);
1367 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1368 hangcheck_action_to_str(engine->hangcheck.action),
1369 engine->hangcheck.action,
1370 jiffies_to_msecs(jiffies -
1371 engine->hangcheck.action_timestamp));
1373 if (engine->id == RCS) {
1374 seq_puts(m, "\tinstdone read =\n");
1376 i915_instdone_info(dev_priv, m, &instdone);
1378 seq_puts(m, "\tinstdone accu =\n");
1380 i915_instdone_info(dev_priv, m,
1381 &engine->hangcheck.instdone);
1388 static int i915_reset_info(struct seq_file *m, void *unused)
1390 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1391 struct i915_gpu_error *error = &dev_priv->gpu_error;
1392 struct intel_engine_cs *engine;
1393 enum intel_engine_id id;
1395 seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1397 for_each_engine(engine, dev_priv, id) {
1398 seq_printf(m, "%s = %u\n", engine->name,
1399 i915_reset_engine_count(error, engine));
1405 static int ironlake_drpc_info(struct seq_file *m)
1407 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1408 u32 rgvmodectl, rstdbyctl;
1411 rgvmodectl = I915_READ(MEMMODECTL);
1412 rstdbyctl = I915_READ(RSTDBYCTL);
1413 crstandvid = I915_READ16(CRSTANDVID);
1415 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1416 seq_printf(m, "Boost freq: %d\n",
1417 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1418 MEMMODE_BOOST_FREQ_SHIFT);
1419 seq_printf(m, "HW control enabled: %s\n",
1420 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1421 seq_printf(m, "SW control enabled: %s\n",
1422 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1423 seq_printf(m, "Gated voltage change: %s\n",
1424 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1425 seq_printf(m, "Starting frequency: P%d\n",
1426 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1427 seq_printf(m, "Max P-state: P%d\n",
1428 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1429 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1430 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1431 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1432 seq_printf(m, "Render standby enabled: %s\n",
1433 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1434 seq_puts(m, "Current RS state: ");
1435 switch (rstdbyctl & RSX_STATUS_MASK) {
1437 seq_puts(m, "on\n");
1439 case RSX_STATUS_RC1:
1440 seq_puts(m, "RC1\n");
1442 case RSX_STATUS_RC1E:
1443 seq_puts(m, "RC1E\n");
1445 case RSX_STATUS_RS1:
1446 seq_puts(m, "RS1\n");
1448 case RSX_STATUS_RS2:
1449 seq_puts(m, "RS2 (RC6)\n");
1451 case RSX_STATUS_RS3:
1452 seq_puts(m, "RC3 (RC6+)\n");
1455 seq_puts(m, "unknown\n");
1462 static int i915_forcewake_domains(struct seq_file *m, void *data)
1464 struct drm_i915_private *i915 = node_to_i915(m->private);
1465 struct intel_uncore_forcewake_domain *fw_domain;
1468 seq_printf(m, "user.bypass_count = %u\n",
1469 i915->uncore.user_forcewake.count);
1471 for_each_fw_domain(fw_domain, i915, tmp)
1472 seq_printf(m, "%s.wake_count = %u\n",
1473 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1474 READ_ONCE(fw_domain->wake_count));
1479 static void print_rc6_res(struct seq_file *m,
1481 const i915_reg_t reg)
1483 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1485 seq_printf(m, "%s %u (%llu us)\n",
1486 title, I915_READ(reg),
1487 intel_rc6_residency_us(dev_priv, reg));
1490 static int vlv_drpc_info(struct seq_file *m)
1492 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1493 u32 rcctl1, pw_status;
1495 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1496 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1498 seq_printf(m, "RC6 Enabled: %s\n",
1499 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1500 GEN6_RC_CTL_EI_MODE(1))));
1501 seq_printf(m, "Render Power Well: %s\n",
1502 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1503 seq_printf(m, "Media Power Well: %s\n",
1504 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1506 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1507 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1509 return i915_forcewake_domains(m, NULL);
1512 static int gen6_drpc_info(struct seq_file *m)
1514 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1515 u32 gt_core_status, rcctl1, rc6vids = 0;
1516 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1517 unsigned forcewake_count;
1520 forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
1521 if (forcewake_count) {
1522 seq_puts(m, "RC information inaccurate because somebody "
1523 "holds a forcewake reference \n");
1525 /* NB: we cannot use forcewake, else we read the wrong values */
1526 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1528 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1531 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1532 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1534 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1535 if (INTEL_GEN(dev_priv) >= 9) {
1536 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1537 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1540 mutex_lock(&dev_priv->pcu_lock);
1541 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1542 mutex_unlock(&dev_priv->pcu_lock);
1544 seq_printf(m, "RC1e Enabled: %s\n",
1545 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546 seq_printf(m, "RC6 Enabled: %s\n",
1547 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548 if (INTEL_GEN(dev_priv) >= 9) {
1549 seq_printf(m, "Render Well Gating Enabled: %s\n",
1550 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1551 seq_printf(m, "Media Well Gating Enabled: %s\n",
1552 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1554 seq_printf(m, "Deep RC6 Enabled: %s\n",
1555 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1556 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1557 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1558 seq_puts(m, "Current RC state: ");
1559 switch (gt_core_status & GEN6_RCn_MASK) {
1561 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1562 seq_puts(m, "Core Power Down\n");
1564 seq_puts(m, "on\n");
1567 seq_puts(m, "RC3\n");
1570 seq_puts(m, "RC6\n");
1573 seq_puts(m, "RC7\n");
1576 seq_puts(m, "Unknown\n");
1580 seq_printf(m, "Core Power Down: %s\n",
1581 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1582 if (INTEL_GEN(dev_priv) >= 9) {
1583 seq_printf(m, "Render Power Well: %s\n",
1584 (gen9_powergate_status &
1585 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1586 seq_printf(m, "Media Power Well: %s\n",
1587 (gen9_powergate_status &
1588 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1591 /* Not exactly sure what this is */
1592 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1593 GEN6_GT_GFX_RC6_LOCKED);
1594 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1595 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1596 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1598 seq_printf(m, "RC6 voltage: %dmV\n",
1599 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1600 seq_printf(m, "RC6+ voltage: %dmV\n",
1601 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1602 seq_printf(m, "RC6++ voltage: %dmV\n",
1603 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1604 return i915_forcewake_domains(m, NULL);
1607 static int i915_drpc_info(struct seq_file *m, void *unused)
1609 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1612 intel_runtime_pm_get(dev_priv);
1614 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1615 err = vlv_drpc_info(m);
1616 else if (INTEL_GEN(dev_priv) >= 6)
1617 err = gen6_drpc_info(m);
1619 err = ironlake_drpc_info(m);
1621 intel_runtime_pm_put(dev_priv);
1626 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1628 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1630 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1631 dev_priv->fb_tracking.busy_bits);
1633 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1634 dev_priv->fb_tracking.flip_bits);
1639 static int i915_fbc_status(struct seq_file *m, void *unused)
1641 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1643 if (!HAS_FBC(dev_priv)) {
1644 seq_puts(m, "FBC unsupported on this chipset\n");
1648 intel_runtime_pm_get(dev_priv);
1649 mutex_lock(&dev_priv->fbc.lock);
1651 if (intel_fbc_is_active(dev_priv))
1652 seq_puts(m, "FBC enabled\n");
1654 seq_printf(m, "FBC disabled: %s\n",
1655 dev_priv->fbc.no_fbc_reason);
1657 if (intel_fbc_is_active(dev_priv)) {
1660 if (INTEL_GEN(dev_priv) >= 8)
1661 mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1662 else if (INTEL_GEN(dev_priv) >= 7)
1663 mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1664 else if (INTEL_GEN(dev_priv) >= 5)
1665 mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1666 else if (IS_G4X(dev_priv))
1667 mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1669 mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1670 FBC_STAT_COMPRESSED);
1672 seq_printf(m, "Compressing: %s\n", yesno(mask));
1675 mutex_unlock(&dev_priv->fbc.lock);
1676 intel_runtime_pm_put(dev_priv);
1681 static int i915_fbc_false_color_get(void *data, u64 *val)
1683 struct drm_i915_private *dev_priv = data;
1685 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1688 *val = dev_priv->fbc.false_color;
1693 static int i915_fbc_false_color_set(void *data, u64 val)
1695 struct drm_i915_private *dev_priv = data;
1698 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1701 mutex_lock(&dev_priv->fbc.lock);
1703 reg = I915_READ(ILK_DPFC_CONTROL);
1704 dev_priv->fbc.false_color = val;
1706 I915_WRITE(ILK_DPFC_CONTROL, val ?
1707 (reg | FBC_CTL_FALSE_COLOR) :
1708 (reg & ~FBC_CTL_FALSE_COLOR));
1710 mutex_unlock(&dev_priv->fbc.lock);
1714 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1715 i915_fbc_false_color_get, i915_fbc_false_color_set,
1718 static int i915_ips_status(struct seq_file *m, void *unused)
1720 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1722 if (!HAS_IPS(dev_priv)) {
1723 seq_puts(m, "not supported\n");
1727 intel_runtime_pm_get(dev_priv);
1729 seq_printf(m, "Enabled by kernel parameter: %s\n",
1730 yesno(i915_modparams.enable_ips));
1732 if (INTEL_GEN(dev_priv) >= 8) {
1733 seq_puts(m, "Currently: unknown\n");
1735 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1736 seq_puts(m, "Currently: enabled\n");
1738 seq_puts(m, "Currently: disabled\n");
1741 intel_runtime_pm_put(dev_priv);
1746 static int i915_sr_status(struct seq_file *m, void *unused)
1748 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1749 bool sr_enabled = false;
1751 intel_runtime_pm_get(dev_priv);
1752 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1754 if (INTEL_GEN(dev_priv) >= 9)
1755 /* no global SR status; inspect per-plane WM */;
1756 else if (HAS_PCH_SPLIT(dev_priv))
1757 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1758 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1759 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1760 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1761 else if (IS_I915GM(dev_priv))
1762 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1763 else if (IS_PINEVIEW(dev_priv))
1764 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1765 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1766 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1768 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1769 intel_runtime_pm_put(dev_priv);
1771 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1776 static int i915_emon_status(struct seq_file *m, void *unused)
1778 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1779 struct drm_device *dev = &dev_priv->drm;
1780 unsigned long temp, chipset, gfx;
1783 if (!IS_GEN5(dev_priv))
1786 ret = mutex_lock_interruptible(&dev->struct_mutex);
1790 temp = i915_mch_val(dev_priv);
1791 chipset = i915_chipset_val(dev_priv);
1792 gfx = i915_gfx_val(dev_priv);
1793 mutex_unlock(&dev->struct_mutex);
1795 seq_printf(m, "GMCH temp: %ld\n", temp);
1796 seq_printf(m, "Chipset power: %ld\n", chipset);
1797 seq_printf(m, "GFX power: %ld\n", gfx);
1798 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1803 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1805 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1806 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1808 int gpu_freq, ia_freq;
1809 unsigned int max_gpu_freq, min_gpu_freq;
1811 if (!HAS_LLC(dev_priv)) {
1812 seq_puts(m, "unsupported on this chipset\n");
1816 intel_runtime_pm_get(dev_priv);
1818 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1822 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1823 /* Convert GT frequency to 50 HZ units */
1824 min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
1825 max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
1827 min_gpu_freq = rps->min_freq_softlimit;
1828 max_gpu_freq = rps->max_freq_softlimit;
1831 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1833 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1835 sandybridge_pcode_read(dev_priv,
1836 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1838 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1839 intel_gpu_freq(dev_priv, (gpu_freq *
1840 (IS_GEN9_BC(dev_priv) ||
1841 IS_CANNONLAKE(dev_priv) ?
1842 GEN9_FREQ_SCALER : 1))),
1843 ((ia_freq >> 0) & 0xff) * 100,
1844 ((ia_freq >> 8) & 0xff) * 100);
1847 mutex_unlock(&dev_priv->pcu_lock);
1850 intel_runtime_pm_put(dev_priv);
1854 static int i915_opregion(struct seq_file *m, void *unused)
1856 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1857 struct drm_device *dev = &dev_priv->drm;
1858 struct intel_opregion *opregion = &dev_priv->opregion;
1861 ret = mutex_lock_interruptible(&dev->struct_mutex);
1865 if (opregion->header)
1866 seq_write(m, opregion->header, OPREGION_SIZE);
1868 mutex_unlock(&dev->struct_mutex);
1874 static int i915_vbt(struct seq_file *m, void *unused)
1876 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1879 seq_write(m, opregion->vbt, opregion->vbt_size);
1884 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1886 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1887 struct drm_device *dev = &dev_priv->drm;
1888 struct intel_framebuffer *fbdev_fb = NULL;
1889 struct drm_framebuffer *drm_fb;
1892 ret = mutex_lock_interruptible(&dev->struct_mutex);
1896 #ifdef CONFIG_DRM_FBDEV_EMULATION
1897 if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1898 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1900 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1901 fbdev_fb->base.width,
1902 fbdev_fb->base.height,
1903 fbdev_fb->base.format->depth,
1904 fbdev_fb->base.format->cpp[0] * 8,
1905 fbdev_fb->base.modifier,
1906 drm_framebuffer_read_refcount(&fbdev_fb->base));
1907 describe_obj(m, fbdev_fb->obj);
1912 mutex_lock(&dev->mode_config.fb_lock);
1913 drm_for_each_fb(drm_fb, dev) {
1914 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1918 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1921 fb->base.format->depth,
1922 fb->base.format->cpp[0] * 8,
1924 drm_framebuffer_read_refcount(&fb->base));
1925 describe_obj(m, fb->obj);
1928 mutex_unlock(&dev->mode_config.fb_lock);
1929 mutex_unlock(&dev->struct_mutex);
1934 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1936 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1937 ring->space, ring->head, ring->tail);
1940 static int i915_context_status(struct seq_file *m, void *unused)
1942 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1943 struct drm_device *dev = &dev_priv->drm;
1944 struct intel_engine_cs *engine;
1945 struct i915_gem_context *ctx;
1946 enum intel_engine_id id;
1949 ret = mutex_lock_interruptible(&dev->struct_mutex);
1953 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1954 seq_printf(m, "HW context %u ", ctx->hw_id);
1956 struct task_struct *task;
1958 task = get_pid_task(ctx->pid, PIDTYPE_PID);
1960 seq_printf(m, "(%s [%d]) ",
1961 task->comm, task->pid);
1962 put_task_struct(task);
1964 } else if (IS_ERR(ctx->file_priv)) {
1965 seq_puts(m, "(deleted) ");
1967 seq_puts(m, "(kernel) ");
1970 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1973 for_each_engine(engine, dev_priv, id) {
1974 struct intel_context *ce = &ctx->engine[engine->id];
1976 seq_printf(m, "%s: ", engine->name);
1977 seq_putc(m, ce->initialised ? 'I' : 'i');
1979 describe_obj(m, ce->state->obj);
1981 describe_ctx_ring(m, ce->ring);
1988 mutex_unlock(&dev->struct_mutex);
1993 static void i915_dump_lrc_obj(struct seq_file *m,
1994 struct i915_gem_context *ctx,
1995 struct intel_engine_cs *engine)
1997 struct i915_vma *vma = ctx->engine[engine->id].state;
2001 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2004 seq_puts(m, "\tFake context\n");
2008 if (vma->flags & I915_VMA_GLOBAL_BIND)
2009 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2010 i915_ggtt_offset(vma));
2012 if (i915_gem_object_pin_pages(vma->obj)) {
2013 seq_puts(m, "\tFailed to get pages for context object\n\n");
2017 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2019 u32 *reg_state = kmap_atomic(page);
2021 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2023 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2025 reg_state[j], reg_state[j + 1],
2026 reg_state[j + 2], reg_state[j + 3]);
2028 kunmap_atomic(reg_state);
2031 i915_gem_object_unpin_pages(vma->obj);
2035 static int i915_dump_lrc(struct seq_file *m, void *unused)
2037 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2038 struct drm_device *dev = &dev_priv->drm;
2039 struct intel_engine_cs *engine;
2040 struct i915_gem_context *ctx;
2041 enum intel_engine_id id;
2044 if (!i915_modparams.enable_execlists) {
2045 seq_printf(m, "Logical Ring Contexts are disabled\n");
2049 ret = mutex_lock_interruptible(&dev->struct_mutex);
2053 list_for_each_entry(ctx, &dev_priv->contexts.list, link)
2054 for_each_engine(engine, dev_priv, id)
2055 i915_dump_lrc_obj(m, ctx, engine);
2057 mutex_unlock(&dev->struct_mutex);
2062 static const char *swizzle_string(unsigned swizzle)
2065 case I915_BIT_6_SWIZZLE_NONE:
2067 case I915_BIT_6_SWIZZLE_9:
2069 case I915_BIT_6_SWIZZLE_9_10:
2070 return "bit9/bit10";
2071 case I915_BIT_6_SWIZZLE_9_11:
2072 return "bit9/bit11";
2073 case I915_BIT_6_SWIZZLE_9_10_11:
2074 return "bit9/bit10/bit11";
2075 case I915_BIT_6_SWIZZLE_9_17:
2076 return "bit9/bit17";
2077 case I915_BIT_6_SWIZZLE_9_10_17:
2078 return "bit9/bit10/bit17";
2079 case I915_BIT_6_SWIZZLE_UNKNOWN:
2086 static int i915_swizzle_info(struct seq_file *m, void *data)
2088 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2090 intel_runtime_pm_get(dev_priv);
2092 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2093 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2094 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2095 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2097 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2098 seq_printf(m, "DDC = 0x%08x\n",
2100 seq_printf(m, "DDC2 = 0x%08x\n",
2102 seq_printf(m, "C0DRB3 = 0x%04x\n",
2103 I915_READ16(C0DRB3));
2104 seq_printf(m, "C1DRB3 = 0x%04x\n",
2105 I915_READ16(C1DRB3));
2106 } else if (INTEL_GEN(dev_priv) >= 6) {
2107 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2108 I915_READ(MAD_DIMM_C0));
2109 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2110 I915_READ(MAD_DIMM_C1));
2111 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2112 I915_READ(MAD_DIMM_C2));
2113 seq_printf(m, "TILECTL = 0x%08x\n",
2114 I915_READ(TILECTL));
2115 if (INTEL_GEN(dev_priv) >= 8)
2116 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2117 I915_READ(GAMTARBMODE));
2119 seq_printf(m, "ARB_MODE = 0x%08x\n",
2120 I915_READ(ARB_MODE));
2121 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2122 I915_READ(DISP_ARB_CTL));
2125 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2126 seq_puts(m, "L-shaped memory detected\n");
2128 intel_runtime_pm_put(dev_priv);
2133 static int per_file_ctx(int id, void *ptr, void *data)
2135 struct i915_gem_context *ctx = ptr;
2136 struct seq_file *m = data;
2137 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2140 seq_printf(m, " no ppgtt for context %d\n",
2145 if (i915_gem_context_is_default(ctx))
2146 seq_puts(m, " default context:\n");
2148 seq_printf(m, " context %d:\n", ctx->user_handle);
2149 ppgtt->debug_dump(ppgtt, m);
2154 static void gen8_ppgtt_info(struct seq_file *m,
2155 struct drm_i915_private *dev_priv)
2157 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2158 struct intel_engine_cs *engine;
2159 enum intel_engine_id id;
2165 for_each_engine(engine, dev_priv, id) {
2166 seq_printf(m, "%s\n", engine->name);
2167 for (i = 0; i < 4; i++) {
2168 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2170 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2171 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2176 static void gen6_ppgtt_info(struct seq_file *m,
2177 struct drm_i915_private *dev_priv)
2179 struct intel_engine_cs *engine;
2180 enum intel_engine_id id;
2182 if (IS_GEN6(dev_priv))
2183 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2185 for_each_engine(engine, dev_priv, id) {
2186 seq_printf(m, "%s\n", engine->name);
2187 if (IS_GEN7(dev_priv))
2188 seq_printf(m, "GFX_MODE: 0x%08x\n",
2189 I915_READ(RING_MODE_GEN7(engine)));
2190 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2191 I915_READ(RING_PP_DIR_BASE(engine)));
2192 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2193 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2194 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2195 I915_READ(RING_PP_DIR_DCLV(engine)));
2197 if (dev_priv->mm.aliasing_ppgtt) {
2198 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2200 seq_puts(m, "aliasing PPGTT:\n");
2201 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2203 ppgtt->debug_dump(ppgtt, m);
2206 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2209 static int i915_ppgtt_info(struct seq_file *m, void *data)
2211 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2212 struct drm_device *dev = &dev_priv->drm;
2213 struct drm_file *file;
2216 mutex_lock(&dev->filelist_mutex);
2217 ret = mutex_lock_interruptible(&dev->struct_mutex);
2221 intel_runtime_pm_get(dev_priv);
2223 if (INTEL_GEN(dev_priv) >= 8)
2224 gen8_ppgtt_info(m, dev_priv);
2225 else if (INTEL_GEN(dev_priv) >= 6)
2226 gen6_ppgtt_info(m, dev_priv);
2228 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2229 struct drm_i915_file_private *file_priv = file->driver_priv;
2230 struct task_struct *task;
2232 task = get_pid_task(file->pid, PIDTYPE_PID);
2237 seq_printf(m, "\nproc: %s\n", task->comm);
2238 put_task_struct(task);
2239 idr_for_each(&file_priv->context_idr, per_file_ctx,
2240 (void *)(unsigned long)m);
2244 intel_runtime_pm_put(dev_priv);
2245 mutex_unlock(&dev->struct_mutex);
2247 mutex_unlock(&dev->filelist_mutex);
2251 static int count_irq_waiters(struct drm_i915_private *i915)
2253 struct intel_engine_cs *engine;
2254 enum intel_engine_id id;
2257 for_each_engine(engine, i915, id)
2258 count += intel_engine_has_waiter(engine);
2263 static const char *rps_power_to_str(unsigned int power)
2265 static const char * const strings[] = {
2266 [LOW_POWER] = "low power",
2267 [BETWEEN] = "mixed",
2268 [HIGH_POWER] = "high power",
2271 if (power >= ARRAY_SIZE(strings) || !strings[power])
2274 return strings[power];
2277 static int i915_rps_boost_info(struct seq_file *m, void *data)
2279 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2280 struct drm_device *dev = &dev_priv->drm;
2281 struct intel_rps *rps = &dev_priv->gt_pm.rps;
2282 struct drm_file *file;
2284 seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2285 seq_printf(m, "GPU busy? %s [%d requests]\n",
2286 yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2287 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2288 seq_printf(m, "Boosts outstanding? %d\n",
2289 atomic_read(&rps->num_waiters));
2290 seq_printf(m, "Frequency requested %d\n",
2291 intel_gpu_freq(dev_priv, rps->cur_freq));
2292 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2293 intel_gpu_freq(dev_priv, rps->min_freq),
2294 intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2295 intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2296 intel_gpu_freq(dev_priv, rps->max_freq));
2297 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
2298 intel_gpu_freq(dev_priv, rps->idle_freq),
2299 intel_gpu_freq(dev_priv, rps->efficient_freq),
2300 intel_gpu_freq(dev_priv, rps->boost_freq));
2302 mutex_lock(&dev->filelist_mutex);
2303 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2304 struct drm_i915_file_private *file_priv = file->driver_priv;
2305 struct task_struct *task;
2308 task = pid_task(file->pid, PIDTYPE_PID);
2309 seq_printf(m, "%s [%d]: %d boosts\n",
2310 task ? task->comm : "<unknown>",
2311 task ? task->pid : -1,
2312 atomic_read(&file_priv->rps_client.boosts));
2315 seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2316 atomic_read(&rps->boosts));
2317 mutex_unlock(&dev->filelist_mutex);
2319 if (INTEL_GEN(dev_priv) >= 6 &&
2321 dev_priv->gt.active_requests) {
2323 u32 rpdown, rpdownei;
2325 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2326 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2327 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2328 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2329 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2330 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2332 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2333 rps_power_to_str(rps->power));
2334 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
2335 rpup && rpupei ? 100 * rpup / rpupei : 0,
2337 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
2338 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2339 rps->down_threshold);
2341 seq_puts(m, "\nRPS Autotuning inactive\n");
2347 static int i915_llc(struct seq_file *m, void *data)
2349 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2350 const bool edram = INTEL_GEN(dev_priv) > 8;
2352 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2353 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2354 intel_uncore_edram_size(dev_priv)/1024/1024);
2359 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2361 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2362 struct drm_printer p;
2364 if (!HAS_HUC_UCODE(dev_priv))
2367 p = drm_seq_file_printer(m);
2368 intel_uc_fw_dump(&dev_priv->huc.fw, &p);
2370 intel_runtime_pm_get(dev_priv);
2371 seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2372 intel_runtime_pm_put(dev_priv);
2377 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2379 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2380 struct drm_printer p;
2383 if (!HAS_GUC_UCODE(dev_priv))
2386 p = drm_seq_file_printer(m);
2387 intel_uc_fw_dump(&dev_priv->guc.fw, &p);
2389 intel_runtime_pm_get(dev_priv);
2391 tmp = I915_READ(GUC_STATUS);
2393 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2394 seq_printf(m, "\tBootrom status = 0x%x\n",
2395 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2396 seq_printf(m, "\tuKernel status = 0x%x\n",
2397 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2398 seq_printf(m, "\tMIA Core status = 0x%x\n",
2399 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2400 seq_puts(m, "\nScratch registers:\n");
2401 for (i = 0; i < 16; i++)
2402 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2404 intel_runtime_pm_put(dev_priv);
2409 static void i915_guc_log_info(struct seq_file *m,
2410 struct drm_i915_private *dev_priv)
2412 struct intel_guc *guc = &dev_priv->guc;
2414 seq_puts(m, "\nGuC logging stats:\n");
2416 seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n",
2417 guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2418 guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2420 seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n",
2421 guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2422 guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2424 seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2425 guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2426 guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2428 seq_printf(m, "\tTotal flush interrupt count: %u\n",
2429 guc->log.flush_interrupt_count);
2431 seq_printf(m, "\tCapture miss count: %u\n",
2432 guc->log.capture_miss_count);
2435 static void i915_guc_client_info(struct seq_file *m,
2436 struct drm_i915_private *dev_priv,
2437 struct i915_guc_client *client)
2439 struct intel_engine_cs *engine;
2440 enum intel_engine_id id;
2443 seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2444 client->priority, client->stage_id, client->proc_desc_offset);
2445 seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2446 client->doorbell_id, client->doorbell_offset);
2448 for_each_engine(engine, dev_priv, id) {
2449 u64 submissions = client->submissions[id];
2451 seq_printf(m, "\tSubmissions: %llu %s\n",
2452 submissions, engine->name);
2454 seq_printf(m, "\tTotal: %llu\n", tot);
2457 static bool check_guc_submission(struct seq_file *m)
2459 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2460 const struct intel_guc *guc = &dev_priv->guc;
2462 if (!guc->execbuf_client) {
2463 seq_printf(m, "GuC submission %s\n",
2464 HAS_GUC_SCHED(dev_priv) ?
2473 static int i915_guc_info(struct seq_file *m, void *data)
2475 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2476 const struct intel_guc *guc = &dev_priv->guc;
2478 if (!check_guc_submission(m))
2481 seq_printf(m, "Doorbell map:\n");
2482 seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2483 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2485 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2486 i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2488 i915_guc_log_info(m, dev_priv);
2490 /* Add more as required ... */
2495 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2497 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2498 const struct intel_guc *guc = &dev_priv->guc;
2499 struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2500 struct i915_guc_client *client = guc->execbuf_client;
2504 if (!check_guc_submission(m))
2507 for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2508 struct intel_engine_cs *engine;
2510 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2513 seq_printf(m, "GuC stage descriptor %u:\n", index);
2514 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2515 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2516 seq_printf(m, "\tPriority: %d\n", desc->priority);
2517 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2518 seq_printf(m, "\tEngines used: 0x%x\n",
2519 desc->engines_used);
2520 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2521 desc->db_trigger_phy,
2522 desc->db_trigger_cpu,
2523 desc->db_trigger_uk);
2524 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2525 desc->process_desc);
2526 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2527 desc->wq_addr, desc->wq_size);
2530 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2531 u32 guc_engine_id = engine->guc_id;
2532 struct guc_execlist_context *lrc =
2533 &desc->lrc[guc_engine_id];
2535 seq_printf(m, "\t%s LRC:\n", engine->name);
2536 seq_printf(m, "\t\tContext desc: 0x%x\n",
2538 seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2539 seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2540 seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2541 seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2549 static int i915_guc_log_dump(struct seq_file *m, void *data)
2551 struct drm_info_node *node = m->private;
2552 struct drm_i915_private *dev_priv = node_to_i915(node);
2553 bool dump_load_err = !!node->info_ent->data;
2554 struct drm_i915_gem_object *obj = NULL;
2559 obj = dev_priv->guc.load_err_log;
2560 else if (dev_priv->guc.log.vma)
2561 obj = dev_priv->guc.log.vma->obj;
2566 log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2568 DRM_DEBUG("Failed to pin object\n");
2569 seq_puts(m, "(log data unaccessible)\n");
2570 return PTR_ERR(log);
2573 for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2574 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2575 *(log + i), *(log + i + 1),
2576 *(log + i + 2), *(log + i + 3));
2580 i915_gem_object_unpin_map(obj);
2585 static int i915_guc_log_control_get(void *data, u64 *val)
2587 struct drm_i915_private *dev_priv = data;
2589 if (!dev_priv->guc.log.vma)
2592 *val = i915_modparams.guc_log_level;
2597 static int i915_guc_log_control_set(void *data, u64 val)
2599 struct drm_i915_private *dev_priv = data;
2602 if (!dev_priv->guc.log.vma)
2605 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
2609 intel_runtime_pm_get(dev_priv);
2610 ret = i915_guc_log_control(dev_priv, val);
2611 intel_runtime_pm_put(dev_priv);
2613 mutex_unlock(&dev_priv->drm.struct_mutex);
2617 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2618 i915_guc_log_control_get, i915_guc_log_control_set,
2621 static const char *psr2_live_status(u32 val)
2623 static const char * const live_status[] = {
2637 val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2638 if (val < ARRAY_SIZE(live_status))
2639 return live_status[val];
2644 static int i915_edp_psr_status(struct seq_file *m, void *data)
2646 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2650 bool enabled = false;
2652 if (!HAS_PSR(dev_priv)) {
2653 seq_puts(m, "PSR not supported\n");
2657 intel_runtime_pm_get(dev_priv);
2659 mutex_lock(&dev_priv->psr.lock);
2660 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2661 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2662 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2663 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2664 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2665 dev_priv->psr.busy_frontbuffer_bits);
2666 seq_printf(m, "Re-enable work scheduled: %s\n",
2667 yesno(work_busy(&dev_priv->psr.work.work)));
2669 if (HAS_DDI(dev_priv)) {
2670 if (dev_priv->psr.psr2_support)
2671 enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2673 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2675 for_each_pipe(dev_priv, pipe) {
2676 enum transcoder cpu_transcoder =
2677 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2678 enum intel_display_power_domain power_domain;
2680 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2681 if (!intel_display_power_get_if_enabled(dev_priv,
2685 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2686 VLV_EDP_PSR_CURR_STATE_MASK;
2687 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2688 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2691 intel_display_power_put(dev_priv, power_domain);
2695 seq_printf(m, "Main link in standby mode: %s\n",
2696 yesno(dev_priv->psr.link_standby));
2698 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2700 if (!HAS_DDI(dev_priv))
2701 for_each_pipe(dev_priv, pipe) {
2702 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2703 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2704 seq_printf(m, " pipe %c", pipe_name(pipe));
2709 * VLV/CHV PSR has no kind of performance counter
2710 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2712 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2713 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2714 EDP_PSR_PERF_CNT_MASK;
2716 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2718 if (dev_priv->psr.psr2_support) {
2719 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2721 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2722 psr2, psr2_live_status(psr2));
2724 mutex_unlock(&dev_priv->psr.lock);
2726 intel_runtime_pm_put(dev_priv);
2730 static int i915_sink_crc(struct seq_file *m, void *data)
2732 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2733 struct drm_device *dev = &dev_priv->drm;
2734 struct intel_connector *connector;
2735 struct drm_connector_list_iter conn_iter;
2736 struct intel_dp *intel_dp = NULL;
2740 drm_modeset_lock_all(dev);
2741 drm_connector_list_iter_begin(dev, &conn_iter);
2742 for_each_intel_connector_iter(connector, &conn_iter) {
2743 struct drm_crtc *crtc;
2745 if (!connector->base.state->best_encoder)
2748 crtc = connector->base.state->crtc;
2749 if (!crtc->state->active)
2752 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2755 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2757 ret = intel_dp_sink_crc(intel_dp, crc);
2761 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2762 crc[0], crc[1], crc[2],
2763 crc[3], crc[4], crc[5]);
2768 drm_connector_list_iter_end(&conn_iter);
2769 drm_modeset_unlock_all(dev);
2773 static int i915_energy_uJ(struct seq_file *m, void *data)
2775 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2776 unsigned long long power;
2779 if (INTEL_GEN(dev_priv) < 6)
2782 intel_runtime_pm_get(dev_priv);
2784 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2785 intel_runtime_pm_put(dev_priv);
2789 units = (power & 0x1f00) >> 8;
2790 power = I915_READ(MCH_SECP_NRG_STTS);
2791 power = (1000000 * power) >> units; /* convert to uJ */
2793 intel_runtime_pm_put(dev_priv);
2795 seq_printf(m, "%llu", power);
2800 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2802 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2803 struct pci_dev *pdev = dev_priv->drm.pdev;
2805 if (!HAS_RUNTIME_PM(dev_priv))
2806 seq_puts(m, "Runtime power management not supported\n");
2808 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2809 seq_printf(m, "IRQs disabled: %s\n",
2810 yesno(!intel_irqs_enabled(dev_priv)));
2812 seq_printf(m, "Usage count: %d\n",
2813 atomic_read(&dev_priv->drm.dev->power.usage_count));
2815 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2817 seq_printf(m, "PCI device power state: %s [%d]\n",
2818 pci_power_name(pdev->current_state),
2819 pdev->current_state);
2824 static int i915_power_domain_info(struct seq_file *m, void *unused)
2826 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2827 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2830 mutex_lock(&power_domains->lock);
2832 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2833 for (i = 0; i < power_domains->power_well_count; i++) {
2834 struct i915_power_well *power_well;
2835 enum intel_display_power_domain power_domain;
2837 power_well = &power_domains->power_wells[i];
2838 seq_printf(m, "%-25s %d\n", power_well->name,
2841 for_each_power_domain(power_domain, power_well->domains)
2842 seq_printf(m, " %-23s %d\n",
2843 intel_display_power_domain_str(power_domain),
2844 power_domains->domain_use_count[power_domain]);
2847 mutex_unlock(&power_domains->lock);
2852 static int i915_dmc_info(struct seq_file *m, void *unused)
2854 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2855 struct intel_csr *csr;
2857 if (!HAS_CSR(dev_priv)) {
2858 seq_puts(m, "not supported\n");
2862 csr = &dev_priv->csr;
2864 intel_runtime_pm_get(dev_priv);
2866 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2867 seq_printf(m, "path: %s\n", csr->fw_path);
2869 if (!csr->dmc_payload)
2872 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2873 CSR_VERSION_MINOR(csr->version));
2875 if (IS_KABYLAKE(dev_priv) ||
2876 (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2877 seq_printf(m, "DC3 -> DC5 count: %d\n",
2878 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2879 seq_printf(m, "DC5 -> DC6 count: %d\n",
2880 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2881 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2882 seq_printf(m, "DC3 -> DC5 count: %d\n",
2883 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2887 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2888 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2889 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2891 intel_runtime_pm_put(dev_priv);
2896 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2897 struct drm_display_mode *mode)
2901 for (i = 0; i < tabs; i++)
2904 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2905 mode->base.id, mode->name,
2906 mode->vrefresh, mode->clock,
2907 mode->hdisplay, mode->hsync_start,
2908 mode->hsync_end, mode->htotal,
2909 mode->vdisplay, mode->vsync_start,
2910 mode->vsync_end, mode->vtotal,
2911 mode->type, mode->flags);
2914 static void intel_encoder_info(struct seq_file *m,
2915 struct intel_crtc *intel_crtc,
2916 struct intel_encoder *intel_encoder)
2918 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2919 struct drm_device *dev = &dev_priv->drm;
2920 struct drm_crtc *crtc = &intel_crtc->base;
2921 struct intel_connector *intel_connector;
2922 struct drm_encoder *encoder;
2924 encoder = &intel_encoder->base;
2925 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2926 encoder->base.id, encoder->name);
2927 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2928 struct drm_connector *connector = &intel_connector->base;
2929 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2932 drm_get_connector_status_name(connector->status));
2933 if (connector->status == connector_status_connected) {
2934 struct drm_display_mode *mode = &crtc->mode;
2935 seq_printf(m, ", mode:\n");
2936 intel_seq_print_mode(m, 2, mode);
2943 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2945 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2946 struct drm_device *dev = &dev_priv->drm;
2947 struct drm_crtc *crtc = &intel_crtc->base;
2948 struct intel_encoder *intel_encoder;
2949 struct drm_plane_state *plane_state = crtc->primary->state;
2950 struct drm_framebuffer *fb = plane_state->fb;
2953 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2954 fb->base.id, plane_state->src_x >> 16,
2955 plane_state->src_y >> 16, fb->width, fb->height);
2957 seq_puts(m, "\tprimary plane disabled\n");
2958 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2959 intel_encoder_info(m, intel_crtc, intel_encoder);
2962 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2964 struct drm_display_mode *mode = panel->fixed_mode;
2966 seq_printf(m, "\tfixed mode:\n");
2967 intel_seq_print_mode(m, 2, mode);
2970 static void intel_dp_info(struct seq_file *m,
2971 struct intel_connector *intel_connector)
2973 struct intel_encoder *intel_encoder = intel_connector->encoder;
2974 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2976 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2977 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2978 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2979 intel_panel_info(m, &intel_connector->panel);
2981 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2985 static void intel_dp_mst_info(struct seq_file *m,
2986 struct intel_connector *intel_connector)
2988 struct intel_encoder *intel_encoder = intel_connector->encoder;
2989 struct intel_dp_mst_encoder *intel_mst =
2990 enc_to_mst(&intel_encoder->base);
2991 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2992 struct intel_dp *intel_dp = &intel_dig_port->dp;
2993 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2994 intel_connector->port);
2996 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2999 static void intel_hdmi_info(struct seq_file *m,
3000 struct intel_connector *intel_connector)
3002 struct intel_encoder *intel_encoder = intel_connector->encoder;
3003 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
3005 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
3008 static void intel_lvds_info(struct seq_file *m,
3009 struct intel_connector *intel_connector)
3011 intel_panel_info(m, &intel_connector->panel);
3014 static void intel_connector_info(struct seq_file *m,
3015 struct drm_connector *connector)
3017 struct intel_connector *intel_connector = to_intel_connector(connector);
3018 struct intel_encoder *intel_encoder = intel_connector->encoder;
3019 struct drm_display_mode *mode;
3021 seq_printf(m, "connector %d: type %s, status: %s\n",
3022 connector->base.id, connector->name,
3023 drm_get_connector_status_name(connector->status));
3024 if (connector->status == connector_status_connected) {
3025 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3026 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3027 connector->display_info.width_mm,
3028 connector->display_info.height_mm);
3029 seq_printf(m, "\tsubpixel order: %s\n",
3030 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3031 seq_printf(m, "\tCEA rev: %d\n",
3032 connector->display_info.cea_rev);
3038 switch (connector->connector_type) {
3039 case DRM_MODE_CONNECTOR_DisplayPort:
3040 case DRM_MODE_CONNECTOR_eDP:
3041 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3042 intel_dp_mst_info(m, intel_connector);
3044 intel_dp_info(m, intel_connector);
3046 case DRM_MODE_CONNECTOR_LVDS:
3047 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3048 intel_lvds_info(m, intel_connector);
3050 case DRM_MODE_CONNECTOR_HDMIA:
3051 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3052 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3053 intel_hdmi_info(m, intel_connector);
3059 seq_printf(m, "\tmodes:\n");
3060 list_for_each_entry(mode, &connector->modes, head)
3061 intel_seq_print_mode(m, 2, mode);
3064 static const char *plane_type(enum drm_plane_type type)
3067 case DRM_PLANE_TYPE_OVERLAY:
3069 case DRM_PLANE_TYPE_PRIMARY:
3071 case DRM_PLANE_TYPE_CURSOR:
3074 * Deliberately omitting default: to generate compiler warnings
3075 * when a new drm_plane_type gets added.
3082 static const char *plane_rotation(unsigned int rotation)
3084 static char buf[48];
3086 * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3087 * will print them all to visualize if the values are misused
3089 snprintf(buf, sizeof(buf),
3090 "%s%s%s%s%s%s(0x%08x)",
3091 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3092 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3093 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3094 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3095 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3096 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3102 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3104 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3105 struct drm_device *dev = &dev_priv->drm;
3106 struct intel_plane *intel_plane;
3108 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3109 struct drm_plane_state *state;
3110 struct drm_plane *plane = &intel_plane->base;
3111 struct drm_format_name_buf format_name;
3113 if (!plane->state) {
3114 seq_puts(m, "plane->state is NULL!\n");
3118 state = plane->state;
3121 drm_get_format_name(state->fb->format->format,
3124 sprintf(format_name.str, "N/A");
3127 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3129 plane_type(intel_plane->base.type),
3130 state->crtc_x, state->crtc_y,
3131 state->crtc_w, state->crtc_h,
3132 (state->src_x >> 16),
3133 ((state->src_x & 0xffff) * 15625) >> 10,
3134 (state->src_y >> 16),
3135 ((state->src_y & 0xffff) * 15625) >> 10,
3136 (state->src_w >> 16),
3137 ((state->src_w & 0xffff) * 15625) >> 10,
3138 (state->src_h >> 16),
3139 ((state->src_h & 0xffff) * 15625) >> 10,
3141 plane_rotation(state->rotation));
3145 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3147 struct intel_crtc_state *pipe_config;
3148 int num_scalers = intel_crtc->num_scalers;
3151 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3153 /* Not all platformas have a scaler */
3155 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3157 pipe_config->scaler_state.scaler_users,
3158 pipe_config->scaler_state.scaler_id);
3160 for (i = 0; i < num_scalers; i++) {
3161 struct intel_scaler *sc =
3162 &pipe_config->scaler_state.scalers[i];
3164 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3165 i, yesno(sc->in_use), sc->mode);
3169 seq_puts(m, "\tNo scalers available on this platform\n");
3173 static int i915_display_info(struct seq_file *m, void *unused)
3175 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3176 struct drm_device *dev = &dev_priv->drm;
3177 struct intel_crtc *crtc;
3178 struct drm_connector *connector;
3179 struct drm_connector_list_iter conn_iter;
3181 intel_runtime_pm_get(dev_priv);
3182 seq_printf(m, "CRTC info\n");
3183 seq_printf(m, "---------\n");
3184 for_each_intel_crtc(dev, crtc) {
3185 struct intel_crtc_state *pipe_config;
3187 drm_modeset_lock(&crtc->base.mutex, NULL);
3188 pipe_config = to_intel_crtc_state(crtc->base.state);
3190 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3191 crtc->base.base.id, pipe_name(crtc->pipe),
3192 yesno(pipe_config->base.active),
3193 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3194 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3196 if (pipe_config->base.active) {
3197 struct intel_plane *cursor =
3198 to_intel_plane(crtc->base.cursor);
3200 intel_crtc_info(m, crtc);
3202 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3203 yesno(cursor->base.state->visible),
3204 cursor->base.state->crtc_x,
3205 cursor->base.state->crtc_y,
3206 cursor->base.state->crtc_w,
3207 cursor->base.state->crtc_h,
3208 cursor->cursor.base);
3209 intel_scaler_info(m, crtc);
3210 intel_plane_info(m, crtc);
3213 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3214 yesno(!crtc->cpu_fifo_underrun_disabled),
3215 yesno(!crtc->pch_fifo_underrun_disabled));
3216 drm_modeset_unlock(&crtc->base.mutex);
3219 seq_printf(m, "\n");
3220 seq_printf(m, "Connector info\n");
3221 seq_printf(m, "--------------\n");
3222 mutex_lock(&dev->mode_config.mutex);
3223 drm_connector_list_iter_begin(dev, &conn_iter);
3224 drm_for_each_connector_iter(connector, &conn_iter)
3225 intel_connector_info(m, connector);
3226 drm_connector_list_iter_end(&conn_iter);
3227 mutex_unlock(&dev->mode_config.mutex);
3229 intel_runtime_pm_put(dev_priv);
3234 static int i915_engine_info(struct seq_file *m, void *unused)
3236 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3237 struct intel_engine_cs *engine;
3238 enum intel_engine_id id;
3239 struct drm_printer p;
3241 intel_runtime_pm_get(dev_priv);
3243 seq_printf(m, "GT awake? %s\n",
3244 yesno(dev_priv->gt.awake));
3245 seq_printf(m, "Global active requests: %d\n",
3246 dev_priv->gt.active_requests);
3248 p = drm_seq_file_printer(m);
3249 for_each_engine(engine, dev_priv, id)
3250 intel_engine_dump(engine, &p);
3252 intel_runtime_pm_put(dev_priv);
3257 static int i915_shrinker_info(struct seq_file *m, void *unused)
3259 struct drm_i915_private *i915 = node_to_i915(m->private);
3261 seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
3262 seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
3267 static int i915_semaphore_status(struct seq_file *m, void *unused)
3269 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3270 struct drm_device *dev = &dev_priv->drm;
3271 struct intel_engine_cs *engine;
3272 int num_rings = INTEL_INFO(dev_priv)->num_rings;
3273 enum intel_engine_id id;
3276 if (!i915_modparams.semaphores) {
3277 seq_puts(m, "Semaphores are disabled\n");
3281 ret = mutex_lock_interruptible(&dev->struct_mutex);
3284 intel_runtime_pm_get(dev_priv);
3286 if (IS_BROADWELL(dev_priv)) {
3290 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3292 seqno = (uint64_t *)kmap_atomic(page);
3293 for_each_engine(engine, dev_priv, id) {
3296 seq_printf(m, "%s\n", engine->name);
3298 seq_puts(m, " Last signal:");
3299 for (j = 0; j < num_rings; j++) {
3300 offset = id * I915_NUM_ENGINES + j;
3301 seq_printf(m, "0x%08llx (0x%02llx) ",
3302 seqno[offset], offset * 8);
3306 seq_puts(m, " Last wait: ");
3307 for (j = 0; j < num_rings; j++) {
3308 offset = id + (j * I915_NUM_ENGINES);
3309 seq_printf(m, "0x%08llx (0x%02llx) ",
3310 seqno[offset], offset * 8);
3315 kunmap_atomic(seqno);
3317 seq_puts(m, " Last signal:");
3318 for_each_engine(engine, dev_priv, id)
3319 for (j = 0; j < num_rings; j++)
3320 seq_printf(m, "0x%08x\n",
3321 I915_READ(engine->semaphore.mbox.signal[j]));
3325 intel_runtime_pm_put(dev_priv);
3326 mutex_unlock(&dev->struct_mutex);
3330 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3332 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3333 struct drm_device *dev = &dev_priv->drm;
3336 drm_modeset_lock_all(dev);
3337 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3338 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3340 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3341 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3342 pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3343 seq_printf(m, " tracked hardware state:\n");
3344 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
3345 seq_printf(m, " dpll_md: 0x%08x\n",
3346 pll->state.hw_state.dpll_md);
3347 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
3348 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
3349 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
3351 drm_modeset_unlock_all(dev);
3356 static int i915_wa_registers(struct seq_file *m, void *unused)
3360 struct intel_engine_cs *engine;
3361 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3362 struct drm_device *dev = &dev_priv->drm;
3363 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3364 enum intel_engine_id id;
3366 ret = mutex_lock_interruptible(&dev->struct_mutex);
3370 intel_runtime_pm_get(dev_priv);
3372 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3373 for_each_engine(engine, dev_priv, id)
3374 seq_printf(m, "HW whitelist count for %s: %d\n",
3375 engine->name, workarounds->hw_whitelist_count[id]);
3376 for (i = 0; i < workarounds->count; ++i) {
3378 u32 mask, value, read;
3381 addr = workarounds->reg[i].addr;
3382 mask = workarounds->reg[i].mask;
3383 value = workarounds->reg[i].value;
3384 read = I915_READ(addr);
3385 ok = (value & mask) == (read & mask);
3386 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3387 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3390 intel_runtime_pm_put(dev_priv);
3391 mutex_unlock(&dev->struct_mutex);
3396 static int i915_ipc_status_show(struct seq_file *m, void *data)
3398 struct drm_i915_private *dev_priv = m->private;
3400 seq_printf(m, "Isochronous Priority Control: %s\n",
3401 yesno(dev_priv->ipc_enabled));
3405 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3407 struct drm_i915_private *dev_priv = inode->i_private;
3409 if (!HAS_IPC(dev_priv))
3412 return single_open(file, i915_ipc_status_show, dev_priv);
3415 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3416 size_t len, loff_t *offp)
3418 struct seq_file *m = file->private_data;
3419 struct drm_i915_private *dev_priv = m->private;
3423 ret = kstrtobool_from_user(ubuf, len, &enable);
3427 intel_runtime_pm_get(dev_priv);
3428 if (!dev_priv->ipc_enabled && enable)
3429 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3430 dev_priv->wm.distrust_bios_wm = true;
3431 dev_priv->ipc_enabled = enable;
3432 intel_enable_ipc(dev_priv);
3433 intel_runtime_pm_put(dev_priv);
3438 static const struct file_operations i915_ipc_status_fops = {
3439 .owner = THIS_MODULE,
3440 .open = i915_ipc_status_open,
3442 .llseek = seq_lseek,
3443 .release = single_release,
3444 .write = i915_ipc_status_write
3447 static int i915_ddb_info(struct seq_file *m, void *unused)
3449 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3450 struct drm_device *dev = &dev_priv->drm;
3451 struct skl_ddb_allocation *ddb;
3452 struct skl_ddb_entry *entry;
3456 if (INTEL_GEN(dev_priv) < 9)
3459 drm_modeset_lock_all(dev);
3461 ddb = &dev_priv->wm.skl_hw.ddb;
3463 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3465 for_each_pipe(dev_priv, pipe) {
3466 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3468 for_each_universal_plane(dev_priv, pipe, plane) {
3469 entry = &ddb->plane[pipe][plane];
3470 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3471 entry->start, entry->end,
3472 skl_ddb_entry_size(entry));
3475 entry = &ddb->plane[pipe][PLANE_CURSOR];
3476 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3477 entry->end, skl_ddb_entry_size(entry));
3480 drm_modeset_unlock_all(dev);
3485 static void drrs_status_per_crtc(struct seq_file *m,
3486 struct drm_device *dev,
3487 struct intel_crtc *intel_crtc)
3489 struct drm_i915_private *dev_priv = to_i915(dev);
3490 struct i915_drrs *drrs = &dev_priv->drrs;
3492 struct drm_connector *connector;
3493 struct drm_connector_list_iter conn_iter;
3495 drm_connector_list_iter_begin(dev, &conn_iter);
3496 drm_for_each_connector_iter(connector, &conn_iter) {
3497 if (connector->state->crtc != &intel_crtc->base)
3500 seq_printf(m, "%s:\n", connector->name);
3502 drm_connector_list_iter_end(&conn_iter);
3504 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3505 seq_puts(m, "\tVBT: DRRS_type: Static");
3506 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3507 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3508 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3509 seq_puts(m, "\tVBT: DRRS_type: None");
3511 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3513 seq_puts(m, "\n\n");
3515 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3516 struct intel_panel *panel;
3518 mutex_lock(&drrs->mutex);
3519 /* DRRS Supported */
3520 seq_puts(m, "\tDRRS Supported: Yes\n");
3522 /* disable_drrs() will make drrs->dp NULL */
3524 seq_puts(m, "Idleness DRRS: Disabled");
3525 mutex_unlock(&drrs->mutex);
3529 panel = &drrs->dp->attached_connector->panel;
3530 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3531 drrs->busy_frontbuffer_bits);
3533 seq_puts(m, "\n\t\t");
3534 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3535 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3536 vrefresh = panel->fixed_mode->vrefresh;
3537 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3538 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3539 vrefresh = panel->downclock_mode->vrefresh;
3541 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3542 drrs->refresh_rate_type);
3543 mutex_unlock(&drrs->mutex);
3546 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3548 seq_puts(m, "\n\t\t");
3549 mutex_unlock(&drrs->mutex);
3551 /* DRRS not supported. Print the VBT parameter*/
3552 seq_puts(m, "\tDRRS Supported : No");
3557 static int i915_drrs_status(struct seq_file *m, void *unused)
3559 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3560 struct drm_device *dev = &dev_priv->drm;
3561 struct intel_crtc *intel_crtc;
3562 int active_crtc_cnt = 0;
3564 drm_modeset_lock_all(dev);
3565 for_each_intel_crtc(dev, intel_crtc) {
3566 if (intel_crtc->base.state->active) {
3568 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3570 drrs_status_per_crtc(m, dev, intel_crtc);
3573 drm_modeset_unlock_all(dev);
3575 if (!active_crtc_cnt)
3576 seq_puts(m, "No active crtc found\n");
3581 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3583 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3584 struct drm_device *dev = &dev_priv->drm;
3585 struct intel_encoder *intel_encoder;
3586 struct intel_digital_port *intel_dig_port;
3587 struct drm_connector *connector;
3588 struct drm_connector_list_iter conn_iter;
3590 drm_connector_list_iter_begin(dev, &conn_iter);
3591 drm_for_each_connector_iter(connector, &conn_iter) {
3592 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3595 intel_encoder = intel_attached_encoder(connector);
3596 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3599 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3600 if (!intel_dig_port->dp.can_mst)
3603 seq_printf(m, "MST Source Port %c\n",
3604 port_name(intel_dig_port->port));
3605 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3607 drm_connector_list_iter_end(&conn_iter);
3612 static ssize_t i915_displayport_test_active_write(struct file *file,
3613 const char __user *ubuf,
3614 size_t len, loff_t *offp)
3618 struct drm_device *dev;
3619 struct drm_connector *connector;
3620 struct drm_connector_list_iter conn_iter;
3621 struct intel_dp *intel_dp;
3624 dev = ((struct seq_file *)file->private_data)->private;
3629 input_buffer = memdup_user_nul(ubuf, len);
3630 if (IS_ERR(input_buffer))
3631 return PTR_ERR(input_buffer);
3633 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3635 drm_connector_list_iter_begin(dev, &conn_iter);
3636 drm_for_each_connector_iter(connector, &conn_iter) {
3637 struct intel_encoder *encoder;
3639 if (connector->connector_type !=
3640 DRM_MODE_CONNECTOR_DisplayPort)
3643 encoder = to_intel_encoder(connector->encoder);
3644 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3647 if (encoder && connector->status == connector_status_connected) {
3648 intel_dp = enc_to_intel_dp(&encoder->base);
3649 status = kstrtoint(input_buffer, 10, &val);
3652 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3653 /* To prevent erroneous activation of the compliance
3654 * testing code, only accept an actual value of 1 here
3657 intel_dp->compliance.test_active = 1;
3659 intel_dp->compliance.test_active = 0;
3662 drm_connector_list_iter_end(&conn_iter);
3663 kfree(input_buffer);
3671 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3673 struct drm_device *dev = m->private;
3674 struct drm_connector *connector;
3675 struct drm_connector_list_iter conn_iter;
3676 struct intel_dp *intel_dp;
3678 drm_connector_list_iter_begin(dev, &conn_iter);
3679 drm_for_each_connector_iter(connector, &conn_iter) {
3680 struct intel_encoder *encoder;
3682 if (connector->connector_type !=
3683 DRM_MODE_CONNECTOR_DisplayPort)
3686 encoder = to_intel_encoder(connector->encoder);
3687 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3690 if (encoder && connector->status == connector_status_connected) {
3691 intel_dp = enc_to_intel_dp(&encoder->base);
3692 if (intel_dp->compliance.test_active)
3699 drm_connector_list_iter_end(&conn_iter);
3704 static int i915_displayport_test_active_open(struct inode *inode,
3707 struct drm_i915_private *dev_priv = inode->i_private;
3709 return single_open(file, i915_displayport_test_active_show,
3713 static const struct file_operations i915_displayport_test_active_fops = {
3714 .owner = THIS_MODULE,
3715 .open = i915_displayport_test_active_open,
3717 .llseek = seq_lseek,
3718 .release = single_release,
3719 .write = i915_displayport_test_active_write
3722 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3724 struct drm_device *dev = m->private;
3725 struct drm_connector *connector;
3726 struct drm_connector_list_iter conn_iter;
3727 struct intel_dp *intel_dp;
3729 drm_connector_list_iter_begin(dev, &conn_iter);
3730 drm_for_each_connector_iter(connector, &conn_iter) {
3731 struct intel_encoder *encoder;
3733 if (connector->connector_type !=
3734 DRM_MODE_CONNECTOR_DisplayPort)
3737 encoder = to_intel_encoder(connector->encoder);
3738 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3741 if (encoder && connector->status == connector_status_connected) {
3742 intel_dp = enc_to_intel_dp(&encoder->base);
3743 if (intel_dp->compliance.test_type ==
3744 DP_TEST_LINK_EDID_READ)
3745 seq_printf(m, "%lx",
3746 intel_dp->compliance.test_data.edid);
3747 else if (intel_dp->compliance.test_type ==
3748 DP_TEST_LINK_VIDEO_PATTERN) {
3749 seq_printf(m, "hdisplay: %d\n",
3750 intel_dp->compliance.test_data.hdisplay);
3751 seq_printf(m, "vdisplay: %d\n",
3752 intel_dp->compliance.test_data.vdisplay);
3753 seq_printf(m, "bpc: %u\n",
3754 intel_dp->compliance.test_data.bpc);
3759 drm_connector_list_iter_end(&conn_iter);
3763 static int i915_displayport_test_data_open(struct inode *inode,
3766 struct drm_i915_private *dev_priv = inode->i_private;
3768 return single_open(file, i915_displayport_test_data_show,
3772 static const struct file_operations i915_displayport_test_data_fops = {
3773 .owner = THIS_MODULE,
3774 .open = i915_displayport_test_data_open,
3776 .llseek = seq_lseek,
3777 .release = single_release
3780 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3782 struct drm_device *dev = m->private;
3783 struct drm_connector *connector;
3784 struct drm_connector_list_iter conn_iter;
3785 struct intel_dp *intel_dp;
3787 drm_connector_list_iter_begin(dev, &conn_iter);
3788 drm_for_each_connector_iter(connector, &conn_iter) {
3789 struct intel_encoder *encoder;
3791 if (connector->connector_type !=
3792 DRM_MODE_CONNECTOR_DisplayPort)
3795 encoder = to_intel_encoder(connector->encoder);
3796 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3799 if (encoder && connector->status == connector_status_connected) {
3800 intel_dp = enc_to_intel_dp(&encoder->base);
3801 seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3805 drm_connector_list_iter_end(&conn_iter);
3810 static int i915_displayport_test_type_open(struct inode *inode,
3813 struct drm_i915_private *dev_priv = inode->i_private;
3815 return single_open(file, i915_displayport_test_type_show,
3819 static const struct file_operations i915_displayport_test_type_fops = {
3820 .owner = THIS_MODULE,
3821 .open = i915_displayport_test_type_open,
3823 .llseek = seq_lseek,
3824 .release = single_release
3827 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3829 struct drm_i915_private *dev_priv = m->private;
3830 struct drm_device *dev = &dev_priv->drm;
3834 if (IS_CHERRYVIEW(dev_priv))
3836 else if (IS_VALLEYVIEW(dev_priv))
3838 else if (IS_G4X(dev_priv))
3841 num_levels = ilk_wm_max_level(dev_priv) + 1;
3843 drm_modeset_lock_all(dev);
3845 for (level = 0; level < num_levels; level++) {
3846 unsigned int latency = wm[level];
3849 * - WM1+ latency values in 0.5us units
3850 * - latencies are in us on gen9/vlv/chv
3852 if (INTEL_GEN(dev_priv) >= 9 ||
3853 IS_VALLEYVIEW(dev_priv) ||
3854 IS_CHERRYVIEW(dev_priv) ||
3860 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3861 level, wm[level], latency / 10, latency % 10);
3864 drm_modeset_unlock_all(dev);
3867 static int pri_wm_latency_show(struct seq_file *m, void *data)
3869 struct drm_i915_private *dev_priv = m->private;
3870 const uint16_t *latencies;
3872 if (INTEL_GEN(dev_priv) >= 9)
3873 latencies = dev_priv->wm.skl_latency;
3875 latencies = dev_priv->wm.pri_latency;
3877 wm_latency_show(m, latencies);
3882 static int spr_wm_latency_show(struct seq_file *m, void *data)
3884 struct drm_i915_private *dev_priv = m->private;
3885 const uint16_t *latencies;
3887 if (INTEL_GEN(dev_priv) >= 9)
3888 latencies = dev_priv->wm.skl_latency;
3890 latencies = dev_priv->wm.spr_latency;
3892 wm_latency_show(m, latencies);
3897 static int cur_wm_latency_show(struct seq_file *m, void *data)
3899 struct drm_i915_private *dev_priv = m->private;
3900 const uint16_t *latencies;
3902 if (INTEL_GEN(dev_priv) >= 9)
3903 latencies = dev_priv->wm.skl_latency;
3905 latencies = dev_priv->wm.cur_latency;
3907 wm_latency_show(m, latencies);
3912 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3914 struct drm_i915_private *dev_priv = inode->i_private;
3916 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3919 return single_open(file, pri_wm_latency_show, dev_priv);
3922 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3924 struct drm_i915_private *dev_priv = inode->i_private;
3926 if (HAS_GMCH_DISPLAY(dev_priv))
3929 return single_open(file, spr_wm_latency_show, dev_priv);
3932 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3934 struct drm_i915_private *dev_priv = inode->i_private;
3936 if (HAS_GMCH_DISPLAY(dev_priv))
3939 return single_open(file, cur_wm_latency_show, dev_priv);
3942 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3943 size_t len, loff_t *offp, uint16_t wm[8])
3945 struct seq_file *m = file->private_data;
3946 struct drm_i915_private *dev_priv = m->private;
3947 struct drm_device *dev = &dev_priv->drm;
3948 uint16_t new[8] = { 0 };
3954 if (IS_CHERRYVIEW(dev_priv))
3956 else if (IS_VALLEYVIEW(dev_priv))
3958 else if (IS_G4X(dev_priv))
3961 num_levels = ilk_wm_max_level(dev_priv) + 1;
3963 if (len >= sizeof(tmp))
3966 if (copy_from_user(tmp, ubuf, len))
3971 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3972 &new[0], &new[1], &new[2], &new[3],
3973 &new[4], &new[5], &new[6], &new[7]);
3974 if (ret != num_levels)
3977 drm_modeset_lock_all(dev);
3979 for (level = 0; level < num_levels; level++)
3980 wm[level] = new[level];
3982 drm_modeset_unlock_all(dev);
3988 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3989 size_t len, loff_t *offp)
3991 struct seq_file *m = file->private_data;
3992 struct drm_i915_private *dev_priv = m->private;
3993 uint16_t *latencies;
3995 if (INTEL_GEN(dev_priv) >= 9)
3996 latencies = dev_priv->wm.skl_latency;
3998 latencies = dev_priv->wm.pri_latency;
4000 return wm_latency_write(file, ubuf, len, offp, latencies);
4003 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4004 size_t len, loff_t *offp)
4006 struct seq_file *m = file->private_data;
4007 struct drm_i915_private *dev_priv = m->private;
4008 uint16_t *latencies;
4010 if (INTEL_GEN(dev_priv) >= 9)
4011 latencies = dev_priv->wm.skl_latency;
4013 latencies = dev_priv->wm.spr_latency;
4015 return wm_latency_write(file, ubuf, len, offp, latencies);
4018 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4019 size_t len, loff_t *offp)
4021 struct seq_file *m = file->private_data;
4022 struct drm_i915_private *dev_priv = m->private;
4023 uint16_t *latencies;
4025 if (INTEL_GEN(dev_priv) >= 9)
4026 latencies = dev_priv->wm.skl_latency;
4028 latencies = dev_priv->wm.cur_latency;
4030 return wm_latency_write(file, ubuf, len, offp, latencies);
4033 static const struct file_operations i915_pri_wm_latency_fops = {
4034 .owner = THIS_MODULE,
4035 .open = pri_wm_latency_open,
4037 .llseek = seq_lseek,
4038 .release = single_release,
4039 .write = pri_wm_latency_write
4042 static const struct file_operations i915_spr_wm_latency_fops = {
4043 .owner = THIS_MODULE,
4044 .open = spr_wm_latency_open,
4046 .llseek = seq_lseek,
4047 .release = single_release,
4048 .write = spr_wm_latency_write
4051 static const struct file_operations i915_cur_wm_latency_fops = {
4052 .owner = THIS_MODULE,
4053 .open = cur_wm_latency_open,
4055 .llseek = seq_lseek,
4056 .release = single_release,
4057 .write = cur_wm_latency_write
4061 i915_wedged_get(void *data, u64 *val)
4063 struct drm_i915_private *dev_priv = data;
4065 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4071 i915_wedged_set(void *data, u64 val)
4073 struct drm_i915_private *i915 = data;
4074 struct intel_engine_cs *engine;
4078 * There is no safeguard against this debugfs entry colliding
4079 * with the hangcheck calling same i915_handle_error() in
4080 * parallel, causing an explosion. For now we assume that the
4081 * test harness is responsible enough not to inject gpu hangs
4082 * while it is writing to 'i915_wedged'
4085 if (i915_reset_backoff(&i915->gpu_error))
4088 for_each_engine_masked(engine, i915, val, tmp) {
4089 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
4090 engine->hangcheck.stalled = true;
4093 i915_handle_error(i915, val, "Manually setting wedged to %llu", val);
4095 wait_on_bit(&i915->gpu_error.flags,
4097 TASK_UNINTERRUPTIBLE);
4102 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4103 i915_wedged_get, i915_wedged_set,
4107 fault_irq_set(struct drm_i915_private *i915,
4113 err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4117 err = i915_gem_wait_for_idle(i915,
4119 I915_WAIT_INTERRUPTIBLE);
4124 mutex_unlock(&i915->drm.struct_mutex);
4126 /* Flush idle worker to disarm irq */
4127 drain_delayed_work(&i915->gt.idle_work);
4132 mutex_unlock(&i915->drm.struct_mutex);
4137 i915_ring_missed_irq_get(void *data, u64 *val)
4139 struct drm_i915_private *dev_priv = data;
4141 *val = dev_priv->gpu_error.missed_irq_rings;
4146 i915_ring_missed_irq_set(void *data, u64 val)
4148 struct drm_i915_private *i915 = data;
4150 return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4153 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4154 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4158 i915_ring_test_irq_get(void *data, u64 *val)
4160 struct drm_i915_private *dev_priv = data;
4162 *val = dev_priv->gpu_error.test_irq_rings;
4168 i915_ring_test_irq_set(void *data, u64 val)
4170 struct drm_i915_private *i915 = data;
4172 val &= INTEL_INFO(i915)->ring_mask;
4173 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4175 return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4178 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4179 i915_ring_test_irq_get, i915_ring_test_irq_set,
4182 #define DROP_UNBOUND BIT(0)
4183 #define DROP_BOUND BIT(1)
4184 #define DROP_RETIRE BIT(2)
4185 #define DROP_ACTIVE BIT(3)
4186 #define DROP_FREED BIT(4)
4187 #define DROP_SHRINK_ALL BIT(5)
4188 #define DROP_IDLE BIT(6)
4189 #define DROP_ALL (DROP_UNBOUND | \
4197 i915_drop_caches_get(void *data, u64 *val)
4205 i915_drop_caches_set(void *data, u64 val)
4207 struct drm_i915_private *dev_priv = data;
4208 struct drm_device *dev = &dev_priv->drm;
4211 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
4212 val, val & DROP_ALL);
4214 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4215 * on ioctls on -EAGAIN. */
4216 if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4217 ret = mutex_lock_interruptible(&dev->struct_mutex);
4221 if (val & DROP_ACTIVE)
4222 ret = i915_gem_wait_for_idle(dev_priv,
4223 I915_WAIT_INTERRUPTIBLE |
4226 if (val & DROP_RETIRE)
4227 i915_gem_retire_requests(dev_priv);
4229 mutex_unlock(&dev->struct_mutex);
4232 fs_reclaim_acquire(GFP_KERNEL);
4233 if (val & DROP_BOUND)
4234 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4236 if (val & DROP_UNBOUND)
4237 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4239 if (val & DROP_SHRINK_ALL)
4240 i915_gem_shrink_all(dev_priv);
4241 fs_reclaim_release(GFP_KERNEL);
4243 if (val & DROP_IDLE)
4244 drain_delayed_work(&dev_priv->gt.idle_work);
4246 if (val & DROP_FREED) {
4248 i915_gem_drain_freed_objects(dev_priv);
4254 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4255 i915_drop_caches_get, i915_drop_caches_set,
4259 i915_max_freq_get(void *data, u64 *val)
4261 struct drm_i915_private *dev_priv = data;
4263 if (INTEL_GEN(dev_priv) < 6)
4266 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
4271 i915_max_freq_set(void *data, u64 val)
4273 struct drm_i915_private *dev_priv = data;
4274 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4278 if (INTEL_GEN(dev_priv) < 6)
4281 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4283 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4288 * Turbo will still be enabled, but won't go above the set value.
4290 val = intel_freq_opcode(dev_priv, val);
4292 hw_max = rps->max_freq;
4293 hw_min = rps->min_freq;
4295 if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
4296 mutex_unlock(&dev_priv->pcu_lock);
4300 rps->max_freq_softlimit = val;
4302 if (intel_set_rps(dev_priv, val))
4303 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4305 mutex_unlock(&dev_priv->pcu_lock);
4310 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4311 i915_max_freq_get, i915_max_freq_set,
4315 i915_min_freq_get(void *data, u64 *val)
4317 struct drm_i915_private *dev_priv = data;
4319 if (INTEL_GEN(dev_priv) < 6)
4322 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
4327 i915_min_freq_set(void *data, u64 val)
4329 struct drm_i915_private *dev_priv = data;
4330 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4334 if (INTEL_GEN(dev_priv) < 6)
4337 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4339 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4344 * Turbo will still be enabled, but won't go below the set value.
4346 val = intel_freq_opcode(dev_priv, val);
4348 hw_max = rps->max_freq;
4349 hw_min = rps->min_freq;
4352 val > hw_max || val > rps->max_freq_softlimit) {
4353 mutex_unlock(&dev_priv->pcu_lock);
4357 rps->min_freq_softlimit = val;
4359 if (intel_set_rps(dev_priv, val))
4360 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4362 mutex_unlock(&dev_priv->pcu_lock);
4367 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4368 i915_min_freq_get, i915_min_freq_set,
4372 i915_cache_sharing_get(void *data, u64 *val)
4374 struct drm_i915_private *dev_priv = data;
4377 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4380 intel_runtime_pm_get(dev_priv);
4382 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4384 intel_runtime_pm_put(dev_priv);
4386 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4392 i915_cache_sharing_set(void *data, u64 val)
4394 struct drm_i915_private *dev_priv = data;
4397 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4403 intel_runtime_pm_get(dev_priv);
4404 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4406 /* Update the cache sharing policy here as well */
4407 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4408 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4409 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4410 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4412 intel_runtime_pm_put(dev_priv);
4416 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4417 i915_cache_sharing_get, i915_cache_sharing_set,
4420 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4421 struct sseu_dev_info *sseu)
4425 u32 sig1[ss_max], sig2[ss_max];
4427 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4428 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4429 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4430 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4432 for (ss = 0; ss < ss_max; ss++) {
4433 unsigned int eu_cnt;
4435 if (sig1[ss] & CHV_SS_PG_ENABLE)
4436 /* skip disabled subslice */
4439 sseu->slice_mask = BIT(0);
4440 sseu->subslice_mask |= BIT(ss);
4441 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4442 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4443 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4444 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4445 sseu->eu_total += eu_cnt;
4446 sseu->eu_per_subslice = max_t(unsigned int,
4447 sseu->eu_per_subslice, eu_cnt);
4451 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4452 struct sseu_dev_info *sseu)
4454 int s_max = 3, ss_max = 4;
4456 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4458 /* BXT has a single slice and at most 3 subslices. */
4459 if (IS_GEN9_LP(dev_priv)) {
4464 for (s = 0; s < s_max; s++) {
4465 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4466 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4467 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4470 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4471 GEN9_PGCTL_SSA_EU19_ACK |
4472 GEN9_PGCTL_SSA_EU210_ACK |
4473 GEN9_PGCTL_SSA_EU311_ACK;
4474 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4475 GEN9_PGCTL_SSB_EU19_ACK |
4476 GEN9_PGCTL_SSB_EU210_ACK |
4477 GEN9_PGCTL_SSB_EU311_ACK;
4479 for (s = 0; s < s_max; s++) {
4480 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4481 /* skip disabled slice */
4484 sseu->slice_mask |= BIT(s);
4486 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
4487 sseu->subslice_mask =
4488 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4490 for (ss = 0; ss < ss_max; ss++) {
4491 unsigned int eu_cnt;
4493 if (IS_GEN9_LP(dev_priv)) {
4494 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4495 /* skip disabled subslice */
4498 sseu->subslice_mask |= BIT(ss);
4501 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4503 sseu->eu_total += eu_cnt;
4504 sseu->eu_per_subslice = max_t(unsigned int,
4505 sseu->eu_per_subslice,
4511 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4512 struct sseu_dev_info *sseu)
4514 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4517 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4519 if (sseu->slice_mask) {
4520 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4521 sseu->eu_per_subslice =
4522 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4523 sseu->eu_total = sseu->eu_per_subslice *
4524 sseu_subslice_total(sseu);
4526 /* subtract fused off EU(s) from enabled slice(s) */
4527 for (s = 0; s < fls(sseu->slice_mask); s++) {
4529 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4531 sseu->eu_total -= hweight8(subslice_7eu);
4536 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4537 const struct sseu_dev_info *sseu)
4539 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4540 const char *type = is_available_info ? "Available" : "Enabled";
4542 seq_printf(m, " %s Slice Mask: %04x\n", type,
4544 seq_printf(m, " %s Slice Total: %u\n", type,
4545 hweight8(sseu->slice_mask));
4546 seq_printf(m, " %s Subslice Total: %u\n", type,
4547 sseu_subslice_total(sseu));
4548 seq_printf(m, " %s Subslice Mask: %04x\n", type,
4549 sseu->subslice_mask);
4550 seq_printf(m, " %s Subslice Per Slice: %u\n", type,
4551 hweight8(sseu->subslice_mask));
4552 seq_printf(m, " %s EU Total: %u\n", type,
4554 seq_printf(m, " %s EU Per Subslice: %u\n", type,
4555 sseu->eu_per_subslice);
4557 if (!is_available_info)
4560 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4561 if (HAS_POOLED_EU(dev_priv))
4562 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
4564 seq_printf(m, " Has Slice Power Gating: %s\n",
4565 yesno(sseu->has_slice_pg));
4566 seq_printf(m, " Has Subslice Power Gating: %s\n",
4567 yesno(sseu->has_subslice_pg));
4568 seq_printf(m, " Has EU Power Gating: %s\n",
4569 yesno(sseu->has_eu_pg));
4572 static int i915_sseu_status(struct seq_file *m, void *unused)
4574 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4575 struct sseu_dev_info sseu;
4577 if (INTEL_GEN(dev_priv) < 8)
4580 seq_puts(m, "SSEU Device Info\n");
4581 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4583 seq_puts(m, "SSEU Device Status\n");
4584 memset(&sseu, 0, sizeof(sseu));
4586 intel_runtime_pm_get(dev_priv);
4588 if (IS_CHERRYVIEW(dev_priv)) {
4589 cherryview_sseu_device_status(dev_priv, &sseu);
4590 } else if (IS_BROADWELL(dev_priv)) {
4591 broadwell_sseu_device_status(dev_priv, &sseu);
4592 } else if (INTEL_GEN(dev_priv) >= 9) {
4593 gen9_sseu_device_status(dev_priv, &sseu);
4596 intel_runtime_pm_put(dev_priv);
4598 i915_print_sseu_info(m, false, &sseu);
4603 static int i915_forcewake_open(struct inode *inode, struct file *file)
4605 struct drm_i915_private *i915 = inode->i_private;
4607 if (INTEL_GEN(i915) < 6)
4610 intel_runtime_pm_get(i915);
4611 intel_uncore_forcewake_user_get(i915);
4616 static int i915_forcewake_release(struct inode *inode, struct file *file)
4618 struct drm_i915_private *i915 = inode->i_private;
4620 if (INTEL_GEN(i915) < 6)
4623 intel_uncore_forcewake_user_put(i915);
4624 intel_runtime_pm_put(i915);
4629 static const struct file_operations i915_forcewake_fops = {
4630 .owner = THIS_MODULE,
4631 .open = i915_forcewake_open,
4632 .release = i915_forcewake_release,
4635 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4637 struct drm_i915_private *dev_priv = m->private;
4638 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4640 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4641 seq_printf(m, "Detected: %s\n",
4642 yesno(delayed_work_pending(&hotplug->reenable_work)));
4647 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4648 const char __user *ubuf, size_t len,
4651 struct seq_file *m = file->private_data;
4652 struct drm_i915_private *dev_priv = m->private;
4653 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4654 unsigned int new_threshold;
4659 if (len >= sizeof(tmp))
4662 if (copy_from_user(tmp, ubuf, len))
4667 /* Strip newline, if any */
4668 newline = strchr(tmp, '\n');
4672 if (strcmp(tmp, "reset") == 0)
4673 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4674 else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4677 if (new_threshold > 0)
4678 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4681 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4683 spin_lock_irq(&dev_priv->irq_lock);
4684 hotplug->hpd_storm_threshold = new_threshold;
4685 /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4687 hotplug->stats[i].count = 0;
4688 spin_unlock_irq(&dev_priv->irq_lock);
4690 /* Re-enable hpd immediately if we were in an irq storm */
4691 flush_delayed_work(&dev_priv->hotplug.reenable_work);
4696 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4698 return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4701 static const struct file_operations i915_hpd_storm_ctl_fops = {
4702 .owner = THIS_MODULE,
4703 .open = i915_hpd_storm_ctl_open,
4705 .llseek = seq_lseek,
4706 .release = single_release,
4707 .write = i915_hpd_storm_ctl_write
4710 static const struct drm_info_list i915_debugfs_list[] = {
4711 {"i915_capabilities", i915_capabilities, 0},
4712 {"i915_gem_objects", i915_gem_object_info, 0},
4713 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4714 {"i915_gem_stolen", i915_gem_stolen_list_info },
4715 {"i915_gem_seqno", i915_gem_seqno_info, 0},
4716 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4717 {"i915_gem_interrupt", i915_interrupt_info, 0},
4718 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4719 {"i915_guc_info", i915_guc_info, 0},
4720 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4721 {"i915_guc_log_dump", i915_guc_log_dump, 0},
4722 {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4723 {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4724 {"i915_huc_load_status", i915_huc_load_status_info, 0},
4725 {"i915_frequency_info", i915_frequency_info, 0},
4726 {"i915_hangcheck_info", i915_hangcheck_info, 0},
4727 {"i915_reset_info", i915_reset_info, 0},
4728 {"i915_drpc_info", i915_drpc_info, 0},
4729 {"i915_emon_status", i915_emon_status, 0},
4730 {"i915_ring_freq_table", i915_ring_freq_table, 0},
4731 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4732 {"i915_fbc_status", i915_fbc_status, 0},
4733 {"i915_ips_status", i915_ips_status, 0},
4734 {"i915_sr_status", i915_sr_status, 0},
4735 {"i915_opregion", i915_opregion, 0},
4736 {"i915_vbt", i915_vbt, 0},
4737 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4738 {"i915_context_status", i915_context_status, 0},
4739 {"i915_dump_lrc", i915_dump_lrc, 0},
4740 {"i915_forcewake_domains", i915_forcewake_domains, 0},
4741 {"i915_swizzle_info", i915_swizzle_info, 0},
4742 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4743 {"i915_llc", i915_llc, 0},
4744 {"i915_edp_psr_status", i915_edp_psr_status, 0},
4745 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4746 {"i915_energy_uJ", i915_energy_uJ, 0},
4747 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4748 {"i915_power_domain_info", i915_power_domain_info, 0},
4749 {"i915_dmc_info", i915_dmc_info, 0},
4750 {"i915_display_info", i915_display_info, 0},
4751 {"i915_engine_info", i915_engine_info, 0},
4752 {"i915_shrinker_info", i915_shrinker_info, 0},
4753 {"i915_semaphore_status", i915_semaphore_status, 0},
4754 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4755 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4756 {"i915_wa_registers", i915_wa_registers, 0},
4757 {"i915_ddb_info", i915_ddb_info, 0},
4758 {"i915_sseu_status", i915_sseu_status, 0},
4759 {"i915_drrs_status", i915_drrs_status, 0},
4760 {"i915_rps_boost_info", i915_rps_boost_info, 0},
4762 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4764 static const struct i915_debugfs_files {
4766 const struct file_operations *fops;
4767 } i915_debugfs_files[] = {
4768 {"i915_wedged", &i915_wedged_fops},
4769 {"i915_max_freq", &i915_max_freq_fops},
4770 {"i915_min_freq", &i915_min_freq_fops},
4771 {"i915_cache_sharing", &i915_cache_sharing_fops},
4772 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4773 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4774 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4775 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4776 {"i915_error_state", &i915_error_state_fops},
4777 {"i915_gpu_info", &i915_gpu_info_fops},
4779 {"i915_next_seqno", &i915_next_seqno_fops},
4780 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4781 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4782 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4783 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4784 {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4785 {"i915_dp_test_data", &i915_displayport_test_data_fops},
4786 {"i915_dp_test_type", &i915_displayport_test_type_fops},
4787 {"i915_dp_test_active", &i915_displayport_test_active_fops},
4788 {"i915_guc_log_control", &i915_guc_log_control_fops},
4789 {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4790 {"i915_ipc_status", &i915_ipc_status_fops}
4793 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4795 struct drm_minor *minor = dev_priv->drm.primary;
4799 ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4800 minor->debugfs_root, to_i915(minor->dev),
4801 &i915_forcewake_fops);
4805 ret = intel_pipe_crc_create(minor);
4809 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4810 ent = debugfs_create_file(i915_debugfs_files[i].name,
4812 minor->debugfs_root,
4813 to_i915(minor->dev),
4814 i915_debugfs_files[i].fops);
4819 return drm_debugfs_create_files(i915_debugfs_list,
4820 I915_DEBUGFS_ENTRIES,
4821 minor->debugfs_root, minor);
4825 /* DPCD dump start address. */
4826 unsigned int offset;
4827 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4829 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4831 /* Only valid for eDP. */
4835 static const struct dpcd_block i915_dpcd_debug[] = {
4836 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4837 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4838 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4839 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4840 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4841 { .offset = DP_SET_POWER },
4842 { .offset = DP_EDP_DPCD_REV },
4843 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4844 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4845 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4848 static int i915_dpcd_show(struct seq_file *m, void *data)
4850 struct drm_connector *connector = m->private;
4851 struct intel_dp *intel_dp =
4852 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4857 if (connector->status != connector_status_connected)
4860 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4861 const struct dpcd_block *b = &i915_dpcd_debug[i];
4862 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4865 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4868 /* low tech for now */
4869 if (WARN_ON(size > sizeof(buf)))
4872 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4874 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4875 size, b->offset, err);
4879 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4885 static int i915_dpcd_open(struct inode *inode, struct file *file)
4887 return single_open(file, i915_dpcd_show, inode->i_private);
4890 static const struct file_operations i915_dpcd_fops = {
4891 .owner = THIS_MODULE,
4892 .open = i915_dpcd_open,
4894 .llseek = seq_lseek,
4895 .release = single_release,
4898 static int i915_panel_show(struct seq_file *m, void *data)
4900 struct drm_connector *connector = m->private;
4901 struct intel_dp *intel_dp =
4902 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4904 if (connector->status != connector_status_connected)
4907 seq_printf(m, "Panel power up delay: %d\n",
4908 intel_dp->panel_power_up_delay);
4909 seq_printf(m, "Panel power down delay: %d\n",
4910 intel_dp->panel_power_down_delay);
4911 seq_printf(m, "Backlight on delay: %d\n",
4912 intel_dp->backlight_on_delay);
4913 seq_printf(m, "Backlight off delay: %d\n",
4914 intel_dp->backlight_off_delay);
4919 static int i915_panel_open(struct inode *inode, struct file *file)
4921 return single_open(file, i915_panel_show, inode->i_private);
4924 static const struct file_operations i915_panel_fops = {
4925 .owner = THIS_MODULE,
4926 .open = i915_panel_open,
4928 .llseek = seq_lseek,
4929 .release = single_release,
4933 * i915_debugfs_connector_add - add i915 specific connector debugfs files
4934 * @connector: pointer to a registered drm_connector
4936 * Cleanup will be done by drm_connector_unregister() through a call to
4937 * drm_debugfs_connector_remove().
4939 * Returns 0 on success, negative error codes on error.
4941 int i915_debugfs_connector_add(struct drm_connector *connector)
4943 struct dentry *root = connector->debugfs_entry;
4945 /* The connector must have been registered beforehands. */
4949 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4950 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4951 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4952 connector, &i915_dpcd_fops);
4954 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4955 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4956 connector, &i915_panel_fops);