drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /* Hisilicon Hibmc SoC drm driver
   3  *
   4  * Based on the bochs drm driver.
   5  *
   6  * Copyright (c) 2016 Huawei Limited.
   7  *
   8  * Author:
   9  *      Rongrong Zou <zourongrong@huawei.com>
  10  *      Rongrong Zou <zourongrong@gmail.com>
  11  *      Jianhua Li <lijianhua@huawei.com>
  12  */
  13
  14 #ifndef HIBMC_DRM_HW_H
  15 #define HIBMC_DRM_HW_H
  16
  17 /* register definition */
  18 #define HIBMC_MISC_CTRL                         0x4
  19
  20 #define HIBMC_MSCCTL_LOCALMEM_RESET(x)          ((x) << 6)
  21 #define HIBMC_MSCCTL_LOCALMEM_RESET_MASK        0x40
  22
  23 #define HIBMC_CURRENT_GATE                      0x000040
  24 #define HIBMC_CURR_GATE_DISPLAY(x)              ((x) << 2)
  25 #define HIBMC_CURR_GATE_DISPLAY_MASK            0x4
  26
  27 #define HIBMC_CURR_GATE_LOCALMEM(x)             ((x) << 1)
  28 #define HIBMC_CURR_GATE_LOCALMEM_MASK           0x2
  29
  30 #define HIBMC_MODE0_GATE                        0x000044
  31 #define HIBMC_MODE1_GATE                        0x000048
  32 #define HIBMC_POWER_MODE_CTRL                   0x00004C
  33
  34 #define HIBMC_PW_MODE_CTL_OSC_INPUT(x)          ((x) << 3)
  35 #define HIBMC_PW_MODE_CTL_OSC_INPUT_MASK        0x8
  36
  37 #define HIBMC_PW_MODE_CTL_MODE(x)               ((x) << 0)
  38 #define HIBMC_PW_MODE_CTL_MODE_MASK             0x03
  39 #define HIBMC_PW_MODE_CTL_MODE_SHIFT            0
  40
  41 #define HIBMC_PW_MODE_CTL_MODE_MODE0            0
  42 #define HIBMC_PW_MODE_CTL_MODE_MODE1            1
  43 #define HIBMC_PW_MODE_CTL_MODE_SLEEP            2
  44
  45 #define HIBMC_PANEL_PLL_CTRL                    0x00005C
  46 #define HIBMC_CRT_PLL_CTRL                      0x000060
  47
  48 #define HIBMC_PLL_CTRL_BYPASS(x)                ((x) << 18)
  49 #define HIBMC_PLL_CTRL_BYPASS_MASK              0x40000
  50
  51 #define HIBMC_PLL_CTRL_POWER(x)                 ((x) << 17)
  52 #define HIBMC_PLL_CTRL_POWER_MASK               0x20000
  53
  54 #define HIBMC_PLL_CTRL_INPUT(x)                 ((x) << 16)
  55 #define HIBMC_PLL_CTRL_INPUT_MASK               0x10000
  56
  57 #define HIBMC_PLL_CTRL_POD(x)                   ((x) << 14)
  58 #define HIBMC_PLL_CTRL_POD_MASK                 0xC000
  59
  60 #define HIBMC_PLL_CTRL_OD(x)                    ((x) << 12)
  61 #define HIBMC_PLL_CTRL_OD_MASK                  0x3000
  62
  63 #define HIBMC_PLL_CTRL_N(x)                     ((x) << 8)
  64 #define HIBMC_PLL_CTRL_N_MASK                   0xF00
  65
  66 #define HIBMC_PLL_CTRL_M(x)                     ((x) << 0)
  67 #define HIBMC_PLL_CTRL_M_MASK                   0xFF
  68
  69 #define HIBMC_CRT_DISP_CTL                      0x80200
  70
  71 #define HIBMC_CRT_DISP_CTL_CRTSELECT(x)         ((x) << 25)
  72 #define HIBMC_CRT_DISP_CTL_CRTSELECT_MASK       0x2000000
  73
  74 #define HIBMC_CRTSELECT_CRT                     1
  75
  76 #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE(x)       ((x) << 14)
  77 #define HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK     0x4000
  78
  79 #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE(x)       ((x) << 13)
  80 #define HIBMC_CRT_DISP_CTL_VSYNC_PHASE_MASK     0x2000
  81
  82 #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE(x)       ((x) << 12)
  83 #define HIBMC_CRT_DISP_CTL_HSYNC_PHASE_MASK     0x1000
  84
  85 #define HIBMC_CRT_DISP_CTL_TIMING(x)            ((x) << 8)
  86 #define HIBMC_CRT_DISP_CTL_TIMING_MASK          0x100
  87
  88 #define HIBMC_CRT_DISP_CTL_PLANE(x)             ((x) << 2)
  89 #define HIBMC_CRT_DISP_CTL_PLANE_MASK           4
  90
  91 #define HIBMC_CRT_DISP_CTL_FORMAT(x)            ((x) << 0)
  92 #define HIBMC_CRT_DISP_CTL_FORMAT_MASK          0x03
  93
  94 #define HIBMC_CRT_FB_ADDRESS                    0x080204
  95
  96 #define HIBMC_CRT_FB_WIDTH                      0x080208
  97 #define HIBMC_CRT_FB_WIDTH_WIDTH(x)             ((x) << 16)
  98 #define HIBMC_CRT_FB_WIDTH_WIDTH_MASK           0x3FFF0000
  99 #define HIBMC_CRT_FB_WIDTH_OFFS(x)              ((x) << 0)
 100 #define HIBMC_CRT_FB_WIDTH_OFFS_MASK            0x3FFF
 101
 102 #define HIBMC_CRT_HORZ_TOTAL                    0x08020C
 103 #define HIBMC_CRT_HORZ_TOTAL_TOTAL(x)           ((x) << 16)
 104 #define HIBMC_CRT_HORZ_TOTAL_TOTAL_MASK         0xFFF0000
 105
 106 #define HIBMC_CRT_HORZ_TOTAL_DISP_END(x)        ((x) << 0)
 107 #define HIBMC_CRT_HORZ_TOTAL_DISP_END_MASK      0xFFF
 108
 109 #define HIBMC_CRT_HORZ_SYNC                     0x080210
 110 #define HIBMC_CRT_HORZ_SYNC_WIDTH(x)            ((x) << 16)
 111 #define HIBMC_CRT_HORZ_SYNC_WIDTH_MASK          0xFF0000
 112
 113 #define HIBMC_CRT_HORZ_SYNC_START(x)            ((x) << 0)
 114 #define HIBMC_CRT_HORZ_SYNC_START_MASK          0xFFF
 115
 116 #define HIBMC_CRT_VERT_TOTAL                    0x080214
 117 #define HIBMC_CRT_VERT_TOTAL_TOTAL(x)           ((x) << 16)
 118 #define HIBMC_CRT_VERT_TOTAL_TOTAL_MASK         0x7FFF0000
 119
 120 #define HIBMC_CRT_VERT_TOTAL_DISP_END(x)        ((x) << 0)
 121 #define HIBMC_CRT_VERT_TOTAL_DISP_END_MASK      0x7FF
 122
 123 #define HIBMC_CRT_VERT_SYNC                     0x080218
 124 #define HIBMC_CRT_VERT_SYNC_HEIGHT(x)           ((x) << 16)
 125 #define HIBMC_CRT_VERT_SYNC_HEIGHT_MASK         0x3F0000
 126
 127 #define HIBMC_CRT_VERT_SYNC_START(x)            ((x) << 0)
 128 #define HIBMC_CRT_VERT_SYNC_START_MASK          0x7FF
 129
 130 /* Auto Centering */
 131 #define HIBMC_CRT_AUTO_CENTERING_TL             0x080280
 132 #define HIBMC_CRT_AUTO_CENTERING_TL_TOP(x)      ((x) << 16)
 133 #define HIBMC_CRT_AUTO_CENTERING_TL_TOP_MASK    0x7FF0000
 134
 135 #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT(x)     ((x) << 0)
 136 #define HIBMC_CRT_AUTO_CENTERING_TL_LEFT_MASK   0x7FF
 137
 138 #define HIBMC_CRT_AUTO_CENTERING_BR             0x080284
 139 #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM(x)   ((x) << 16)
 140 #define HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM_MASK 0x7FF0000
 141
 142 #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT(x)    ((x) << 0)
 143 #define HIBMC_CRT_AUTO_CENTERING_BR_RIGHT_MASK  0x7FF
 144
 145 /* register to control panel output */
 146 #define HIBMC_DISPLAY_CONTROL_HISILE            0x80288
 147 #define HIBMC_DISPLAY_CONTROL_FPVDDEN(x)        ((x) << 0)
 148 #define HIBMC_DISPLAY_CONTROL_PANELDATE(x)      ((x) << 1)
 149 #define HIBMC_DISPLAY_CONTROL_FPEN(x)           ((x) << 2)
 150 #define HIBMC_DISPLAY_CONTROL_VBIASEN(x)        ((x) << 3)
 151
 152 #define HIBMC_RAW_INTERRUPT                     0x80290
 153 #define HIBMC_RAW_INTERRUPT_VBLANK(x)           ((x) << 2)
 154 #define HIBMC_RAW_INTERRUPT_VBLANK_MASK         0x4
 155
 156 #define HIBMC_RAW_INTERRUPT_EN                  0x80298
 157 #define HIBMC_RAW_INTERRUPT_EN_VBLANK(x)        ((x) << 2)
 158 #define HIBMC_RAW_INTERRUPT_EN_VBLANK_MASK      0x4
 159
 160 /* register and values for PLL control */
 161 #define CRT_PLL1_HS                             0x802a8
 162 #define CRT_PLL1_HS_OUTER_BYPASS(x)             ((x) << 30)
 163 #define CRT_PLL1_HS_INTER_BYPASS(x)             ((x) << 29)
 164 #define CRT_PLL1_HS_POWERON(x)                  ((x) << 24)
 165
 166 #define CRT_PLL1_HS_25MHZ                       0x23d40f02
 167 #define CRT_PLL1_HS_40MHZ                       0x23940801
 168 #define CRT_PLL1_HS_65MHZ                       0x23940d01
 169 #define CRT_PLL1_HS_78MHZ                       0x23540F82
 170 #define CRT_PLL1_HS_74MHZ                       0x23941dc2
 171 #define CRT_PLL1_HS_80MHZ                       0x23941001
 172 #define CRT_PLL1_HS_80MHZ_1152                  0x23540fc2
 173 #define CRT_PLL1_HS_108MHZ                      0x23b41b01
 174 #define CRT_PLL1_HS_162MHZ                      0x23480681
 175 #define CRT_PLL1_HS_148MHZ                      0x23541dc2
 176 #define CRT_PLL1_HS_193MHZ                      0x234807c1
 177
 178 #define CRT_PLL2_HS                             0x802ac
 179 #define CRT_PLL2_HS_25MHZ                       0x206B851E
 180 #define CRT_PLL2_HS_40MHZ                       0x30000000
 181 #define CRT_PLL2_HS_65MHZ                       0x40000000
 182 #define CRT_PLL2_HS_78MHZ                       0x50E147AE
 183 #define CRT_PLL2_HS_74MHZ                       0x602B6AE7
 184 #define CRT_PLL2_HS_80MHZ                       0x70000000
 185 #define CRT_PLL2_HS_108MHZ                      0x80000000
 186 #define CRT_PLL2_HS_162MHZ                      0xA0000000
 187 #define CRT_PLL2_HS_148MHZ                      0xB0CCCCCD
 188 #define CRT_PLL2_HS_193MHZ                      0xC0872B02
 189
 190 #define HIBMC_FIELD(field, value) (field(value) & field##_MASK)
 191 #endif