drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Hisilicon Hibmc SoC drm driver
   3  *
   4  * Based on the bochs drm driver.
   5  *
   6  * Copyright (c) 2016 Huawei Limited.
   7  *
   8  * Author:
   9  *      Rongrong Zou <zourongrong@huawei.com>
  10  *      Rongrong Zou <zourongrong@gmail.com>
  11  *      Jianhua Li <lijianhua@huawei.com>
  12  */
  13
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_plane_helper.h>
  17 #include <drm/drm_probe_helper.h>
  18
  19 #include "hibmc_drm_drv.h"
  20 #include "hibmc_drm_regs.h"
  21
  22 struct hibmc_display_panel_pll {
  23         unsigned long M;
  24         unsigned long N;
  25         unsigned long OD;
  26         unsigned long POD;
  27 };
  28
  29 struct hibmc_dislay_pll_config {
  30         unsigned long hdisplay;
  31         unsigned long vdisplay;
  32         u32 pll1_config_value;
  33         u32 pll2_config_value;
  34 };
  35
  36 static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {
  37         {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},
  38         {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},
  39         {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},
  40         {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ},
  41         {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},
  42         {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
  43         {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
  44         {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},
  45         {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},
  46         {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},
  47 };
  48
  49 #define PADDING(align, data) (((data) + (align) - 1) & (~((align) - 1)))
  50
  51 static int hibmc_plane_atomic_check(struct drm_plane *plane,
  52                                     struct drm_plane_state *state)
  53 {
  54         struct drm_framebuffer *fb = state->fb;
  55         struct drm_crtc *crtc = state->crtc;
  56         struct drm_crtc_state *crtc_state;
  57         u32 src_w = state->src_w >> 16;
  58         u32 src_h = state->src_h >> 16;
  59
  60         if (!crtc || !fb)
  61                 return 0;
  62
  63         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
  64         if (IS_ERR(crtc_state))
  65                 return PTR_ERR(crtc_state);
  66
  67         if (src_w != state->crtc_w || src_h != state->crtc_h) {
  68                 DRM_DEBUG_ATOMIC("scale not support\n");
  69                 return -EINVAL;
  70         }
  71
  72         if (state->crtc_x < 0 || state->crtc_y < 0) {
  73                 DRM_DEBUG_ATOMIC("crtc_x/y of drm_plane state is invalid\n");
  74                 return -EINVAL;
  75         }
  76
  77         if (state->crtc_x + state->crtc_w >
  78             crtc_state->adjusted_mode.hdisplay ||
  79             state->crtc_y + state->crtc_h >
  80             crtc_state->adjusted_mode.vdisplay) {
  81                 DRM_DEBUG_ATOMIC("visible portion of plane is invalid\n");
  82                 return -EINVAL;
  83         }
  84
  85         return 0;
  86 }
  87
  88 static void hibmc_plane_atomic_update(struct drm_plane *plane,
  89                                       struct drm_plane_state *old_state)
  90 {
  91         struct drm_plane_state  *state  = plane->state;
  92         u32 reg;
  93         int ret;
  94         s64 gpu_addr = 0;
  95         unsigned int line_l;
  96         struct hibmc_drm_private *priv = plane->dev->dev_private;
  97         struct hibmc_framebuffer *hibmc_fb;
  98         struct drm_gem_vram_object *gbo;
  99
 100         if (!state->fb)
 101                 return;
 102
 103         hibmc_fb = to_hibmc_framebuffer(state->fb);
 104         gbo = drm_gem_vram_of_gem(hibmc_fb->obj);
 105
 106         ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM);
 107         if (ret) {
 108                 DRM_ERROR("failed to pin bo: %d", ret);
 109                 return;
 110         }
 111         gpu_addr = drm_gem_vram_offset(gbo);
 112         if (gpu_addr < 0) {
 113                 drm_gem_vram_unpin(gbo);
 114                 return;
 115         }
 116
 117         writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
 118
 119         reg = state->fb->width * (state->fb->format->cpp[0]);
 120         /* now line_pad is 16 */
 121         reg = PADDING(16, reg);
 122
 123         line_l = state->fb->width * state->fb->format->cpp[0];
 124         line_l = PADDING(16, line_l);
 125         writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |
 126                HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),
 127                priv->mmio + HIBMC_CRT_FB_WIDTH);
 128
 129         /* SET PIXEL FORMAT */
 130         reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
 131         reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK;
 132         reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,
 133                            state->fb->format->cpp[0] * 8 / 16);
 134         writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
 135 }
 136
 137 static const u32 channel_formats1[] = {
 138         DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
 139         DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
 140         DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
 141         DRM_FORMAT_ABGR8888
 142 };
 143
 144 static struct drm_plane_funcs hibmc_plane_funcs = {
 145         .update_plane   = drm_atomic_helper_update_plane,
 146         .disable_plane  = drm_atomic_helper_disable_plane,
 147         .destroy = drm_plane_cleanup,
 148         .reset = drm_atomic_helper_plane_reset,
 149         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 150         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 151 };
 152
 153 static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = {
 154         .atomic_check = hibmc_plane_atomic_check,
 155         .atomic_update = hibmc_plane_atomic_update,
 156 };
 157
 158 static struct drm_plane *hibmc_plane_init(struct hibmc_drm_private *priv)
 159 {
 160         struct drm_device *dev = priv->dev;
 161         struct drm_plane *plane;
 162         int ret = 0;
 163
 164         plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL);
 165         if (!plane) {
 166                 DRM_ERROR("failed to alloc memory when init plane\n");
 167                 return ERR_PTR(-ENOMEM);
 168         }
 169         /*
 170          * plane init
 171          * TODO: Now only support primary plane, overlay planes
 172          * need to do.
 173          */
 174         ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs,
 175                                        channel_formats1,
 176                                        ARRAY_SIZE(channel_formats1),
 177                                        NULL,
 178                                        DRM_PLANE_TYPE_PRIMARY,
 179                                        NULL);
 180         if (ret) {
 181                 DRM_ERROR("failed to init plane: %d\n", ret);
 182                 return ERR_PTR(ret);
 183         }
 184
 185         drm_plane_helper_add(plane, &hibmc_plane_helper_funcs);
 186         return plane;
 187 }
 188
 189 static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc,
 190                                      struct drm_crtc_state *old_state)
 191 {
 192         unsigned int reg;
 193         struct hibmc_drm_private *priv = crtc->dev->dev_private;
 194
 195         hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
 196
 197         /* Enable display power gate & LOCALMEM power gate*/
 198         reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
 199         reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
 200         reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
 201         reg |= HIBMC_CURR_GATE_LOCALMEM(1);
 202         reg |= HIBMC_CURR_GATE_DISPLAY(1);
 203         hibmc_set_current_gate(priv, reg);
 204         drm_crtc_vblank_on(crtc);
 205 }
 206
 207 static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc,
 208                                       struct drm_crtc_state *old_state)
 209 {
 210         unsigned int reg;
 211         struct hibmc_drm_private *priv = crtc->dev->dev_private;
 212
 213         drm_crtc_vblank_off(crtc);
 214
 215         hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP);
 216
 217         /* Enable display power gate & LOCALMEM power gate*/
 218         reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
 219         reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
 220         reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
 221         reg |= HIBMC_CURR_GATE_LOCALMEM(0);
 222         reg |= HIBMC_CURR_GATE_DISPLAY(0);
 223         hibmc_set_current_gate(priv, reg);
 224 }
 225
 226 static unsigned int format_pll_reg(void)
 227 {
 228         unsigned int pllreg = 0;
 229         struct hibmc_display_panel_pll pll = {0};
 230
 231         /*
 232          * Note that all PLL's have the same format. Here,
 233          * we just use Panel PLL parameter to work out the bit
 234          * fields in the register.On returning a 32 bit number, the value can
 235          * be applied to any PLL in the calling function.
 236          */
 237         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0);
 238         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1);
 239         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0);
 240         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);
 241         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);
 242         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);
 243         pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);
 244
 245         return pllreg;
 246 }
 247
 248 static void set_vclock_hisilicon(struct drm_device *dev, unsigned long pll)
 249 {
 250         u32 val;
 251         struct hibmc_drm_private *priv = dev->dev_private;
 252
 253         val = readl(priv->mmio + CRT_PLL1_HS);
 254         val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1));
 255         writel(val, priv->mmio + CRT_PLL1_HS);
 256
 257         val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1);
 258         writel(val, priv->mmio + CRT_PLL1_HS);
 259
 260         writel(pll, priv->mmio + CRT_PLL1_HS);
 261
 262         usleep_range(1000, 2000);
 263
 264         val = pll & ~(CRT_PLL1_HS_POWERON(1));
 265         writel(val, priv->mmio + CRT_PLL1_HS);
 266
 267         usleep_range(1000, 2000);
 268
 269         val &= ~(CRT_PLL1_HS_INTER_BYPASS(1));
 270         writel(val, priv->mmio + CRT_PLL1_HS);
 271
 272         usleep_range(1000, 2000);
 273
 274         val |= CRT_PLL1_HS_OUTER_BYPASS(1);
 275         writel(val, priv->mmio + CRT_PLL1_HS);
 276 }
 277
 278 static void get_pll_config(unsigned long x, unsigned long y,
 279                            u32 *pll1, u32 *pll2)
 280 {
 281         int i;
 282         int count = ARRAY_SIZE(hibmc_pll_table);
 283
 284         for (i = 0; i < count; i++) {
 285                 if (hibmc_pll_table[i].hdisplay == x &&
 286                     hibmc_pll_table[i].vdisplay == y) {
 287                         *pll1 = hibmc_pll_table[i].pll1_config_value;
 288                         *pll2 = hibmc_pll_table[i].pll2_config_value;
 289                         return;
 290                 }
 291         }
 292
 293         /* if found none, we use default value */
 294         *pll1 = CRT_PLL1_HS_25MHZ;
 295         *pll2 = CRT_PLL2_HS_25MHZ;
 296 }
 297
 298 /*
 299  * This function takes care the extra registers and bit fields required to
 300  * setup a mode in board.
 301  * Explanation about Display Control register:
 302  * FPGA only supports 7 predefined pixel clocks, and clock select is
 303  * in bit 4:0 of new register 0x802a8.
 304  */
 305 static unsigned int display_ctrl_adjust(struct drm_device *dev,
 306                                         struct drm_display_mode *mode,
 307                                         unsigned int ctrl)
 308 {
 309         unsigned long x, y;
 310         u32 pll1; /* bit[31:0] of PLL */
 311         u32 pll2; /* bit[63:32] of PLL */
 312         struct hibmc_drm_private *priv = dev->dev_private;
 313
 314         x = mode->hdisplay;
 315         y = mode->vdisplay;
 316
 317         get_pll_config(x, y, &pll1, &pll2);
 318         writel(pll2, priv->mmio + CRT_PLL2_HS);
 319         set_vclock_hisilicon(dev, pll1);
 320
 321         /*
 322          * Hisilicon has to set up the top-left and bottom-right
 323          * registers as well.
 324          * Note that normal chip only use those two register for
 325          * auto-centering mode.
 326          */
 327         writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |
 328                HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0),
 329                priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL);
 330
 331         writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |
 332                HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1),
 333                priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR);
 334
 335         /*
 336          * Assume common fields in ctrl have been properly set before
 337          * calling this function.
 338          * This function only sets the extra fields in ctrl.
 339          */
 340
 341         /* Set bit 25 of display controller: Select CRT or VGA clock */
 342         ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK;
 343         ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK;
 344
 345         ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT);
 346
 347         /* clock_phase_polarity is 0 */
 348         ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0);
 349
 350         writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL);
 351
 352         return ctrl;
 353 }
 354
 355 static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 356 {
 357         unsigned int val;
 358         struct drm_display_mode *mode = &crtc->state->mode;
 359         struct drm_device *dev = crtc->dev;
 360         struct hibmc_drm_private *priv = dev->dev_private;
 361         int width = mode->hsync_end - mode->hsync_start;
 362         int height = mode->vsync_end - mode->vsync_start;
 363
 364         writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL);
 365         writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |
 366                HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1),
 367                priv->mmio + HIBMC_CRT_HORZ_TOTAL);
 368
 369         writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |
 370                HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1),
 371                priv->mmio + HIBMC_CRT_HORZ_SYNC);
 372
 373         writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |
 374                HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1),
 375                priv->mmio + HIBMC_CRT_VERT_TOTAL);
 376
 377         writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |
 378                HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1),
 379                priv->mmio + HIBMC_CRT_VERT_SYNC);
 380
 381         val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0);
 382         val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0);
 383         val |= HIBMC_CRT_DISP_CTL_TIMING(1);
 384         val |= HIBMC_CRT_DISP_CTL_PLANE(1);
 385
 386         display_ctrl_adjust(dev, mode, val);
 387 }
 388
 389 static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc,
 390                                     struct drm_crtc_state *old_state)
 391 {
 392         unsigned int reg;
 393         struct drm_device *dev = crtc->dev;
 394         struct hibmc_drm_private *priv = dev->dev_private;
 395
 396         hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
 397
 398         /* Enable display power gate & LOCALMEM power gate*/
 399         reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
 400         reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
 401         reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
 402         reg |= HIBMC_CURR_GATE_DISPLAY(1);
 403         reg |= HIBMC_CURR_GATE_LOCALMEM(1);
 404         hibmc_set_current_gate(priv, reg);
 405
 406         /* We can add more initialization as needed. */
 407 }
 408
 409 static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc,
 410                                     struct drm_crtc_state *old_state)
 411
 412 {
 413         unsigned long flags;
 414
 415         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 416         if (crtc->state->event)
 417                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 418         crtc->state->event = NULL;
 419         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 420 }
 421
 422 static int hibmc_crtc_enable_vblank(struct drm_crtc *crtc)
 423 {
 424         struct hibmc_drm_private *priv = crtc->dev->dev_private;
 425
 426         writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1),
 427                priv->mmio + HIBMC_RAW_INTERRUPT_EN);
 428
 429         return 0;
 430 }
 431
 432 static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc)
 433 {
 434         struct hibmc_drm_private *priv = crtc->dev->dev_private;
 435
 436         writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0),
 437                priv->mmio + HIBMC_RAW_INTERRUPT_EN);
 438 }
 439
 440 static const struct drm_crtc_funcs hibmc_crtc_funcs = {
 441         .page_flip = drm_atomic_helper_page_flip,
 442         .set_config = drm_atomic_helper_set_config,
 443         .destroy = drm_crtc_cleanup,
 444         .reset = drm_atomic_helper_crtc_reset,
 445         .atomic_duplicate_state =  drm_atomic_helper_crtc_duplicate_state,
 446         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 447         .enable_vblank = hibmc_crtc_enable_vblank,
 448         .disable_vblank = hibmc_crtc_disable_vblank,
 449 };
 450
 451 static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = {
 452         .mode_set_nofb  = hibmc_crtc_mode_set_nofb,
 453         .atomic_begin   = hibmc_crtc_atomic_begin,
 454         .atomic_flush   = hibmc_crtc_atomic_flush,
 455         .atomic_enable  = hibmc_crtc_atomic_enable,
 456         .atomic_disable = hibmc_crtc_atomic_disable,
 457 };
 458
 459 int hibmc_de_init(struct hibmc_drm_private *priv)
 460 {
 461         struct drm_device *dev = priv->dev;
 462         struct drm_crtc *crtc;
 463         struct drm_plane *plane;
 464         int ret;
 465
 466         plane = hibmc_plane_init(priv);
 467         if (IS_ERR(plane)) {
 468                 DRM_ERROR("failed to create plane: %ld\n", PTR_ERR(plane));
 469                 return PTR_ERR(plane);
 470         }
 471
 472         crtc = devm_kzalloc(dev->dev, sizeof(*crtc), GFP_KERNEL);
 473         if (!crtc) {
 474                 DRM_ERROR("failed to alloc memory when init crtc\n");
 475                 return -ENOMEM;
 476         }
 477
 478         ret = drm_crtc_init_with_planes(dev, crtc, plane,
 479                                         NULL, &hibmc_crtc_funcs, NULL);
 480         if (ret) {
 481                 DRM_ERROR("failed to init crtc: %d\n", ret);
 482                 return ret;
 483         }
 484
 485         ret = drm_mode_crtc_set_gamma_size(crtc, 256);
 486         if (ret) {
 487                 DRM_ERROR("failed to set gamma size: %d\n", ret);
 488                 return ret;
 489         }
 490         drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs);
 491
 492         return 0;
 493 }