1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright(c) 2016, Analogix Semiconductor.
5 * Based on anx7808 driver obtained from chromeos with copyright:
6 * Copyright(c) 2013, Google Inc.
8 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_platform.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/types.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_crtc.h>
23 #include <drm/drm_dp_helper.h>
24 #include <drm/drm_edid.h>
25 #include <drm/drm_print.h>
26 #include <drm/drm_probe_helper.h>
28 #include "analogix-anx78xx.h"
30 #define I2C_NUM_ADDRESSES 5
31 #define I2C_IDX_TX_P0 0
32 #define I2C_IDX_TX_P1 1
33 #define I2C_IDX_TX_P2 2
34 #define I2C_IDX_RX_P0 3
35 #define I2C_IDX_RX_P1 4
37 #define XTAL_CLK 270 /* 27M */
38 #define AUX_CH_BUFFER_SIZE 16
39 #define AUX_WAIT_TIMEOUT_MS 15
41 static const u8 anx78xx_i2c_addresses[] = {
42 [I2C_IDX_TX_P0] = TX_P0,
43 [I2C_IDX_TX_P1] = TX_P1,
44 [I2C_IDX_TX_P2] = TX_P2,
45 [I2C_IDX_RX_P0] = RX_P0,
46 [I2C_IDX_RX_P1] = RX_P1,
49 struct anx78xx_platform_data {
50 struct regulator *dvdd10;
51 struct gpio_desc *gpiod_hpd;
52 struct gpio_desc *gpiod_pd;
53 struct gpio_desc *gpiod_reset;
60 struct drm_dp_aux aux;
61 struct drm_bridge bridge;
62 struct i2c_client *client;
64 struct drm_connector connector;
65 struct drm_dp_link link;
66 struct anx78xx_platform_data pdata;
70 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,
73 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
74 struct regmap *map[I2C_NUM_ADDRESSES];
77 u8 dpcd[DP_RECEIVER_CAP_SIZE];
82 static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
84 return container_of(c, struct anx78xx, connector);
87 static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
89 return container_of(bridge, struct anx78xx, bridge);
92 static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
94 return regmap_update_bits(map, reg, mask, mask);
97 static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
99 return regmap_update_bits(map, reg, mask, 0);
102 static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx)
107 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
112 return (value & SP_AUX_EN) == 0;
115 static int anx78xx_aux_wait(struct anx78xx *anx78xx)
117 unsigned long timeout;
121 timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
123 while (!anx78xx_aux_op_finished(anx78xx)) {
124 if (time_after(jiffies, timeout)) {
125 if (!anx78xx_aux_op_finished(anx78xx)) {
126 DRM_ERROR("Timed out waiting AUX to finish\n");
133 usleep_range(1000, 2000);
136 /* Read the AUX channel access status */
137 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG,
140 DRM_ERROR("Failed to read from AUX channel: %d\n", err);
144 if (status & SP_AUX_STATUS) {
145 DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
153 static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr)
157 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG,
162 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG,
163 (addr & 0xff00) >> 8);
168 * DP AUX CH Address Register #2, only update bits[3:0]
170 * [3:0] AUX_ADDR[19:16], Register control AUX CH address.
172 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
173 SP_AUX_ADDR_19_16_REG,
174 SP_AUX_ADDR_19_16_MASK,
175 (addr & 0xf0000) >> 16);
183 static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
184 struct drm_dp_aux_msg *msg)
186 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
187 u8 ctrl1 = msg->request;
188 u8 ctrl2 = SP_AUX_EN;
189 u8 *buffer = msg->buffer;
192 /* The DP AUX transmit and receive buffer has 16 bytes. */
193 if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
196 /* Zero-sized messages specify address-only transactions. */
198 ctrl2 |= SP_ADDR_ONLY;
199 else /* For non-zero-sized set the length field. */
200 ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
202 if ((msg->request & DP_AUX_I2C_READ) == 0) {
203 /* When WRITE | MOT write values to data buffer */
204 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0],
205 SP_DP_BUF_DATA0_REG, buffer,
211 /* Write address and request */
212 err = anx78xx_aux_address(anx78xx, msg->address);
216 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG,
221 /* Start transaction */
222 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
223 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY |
228 err = anx78xx_aux_wait(anx78xx);
232 msg->reply = DP_AUX_I2C_REPLY_ACK;
234 if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
235 /* Read values from data buffer */
236 err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0],
237 SP_DP_BUF_DATA0_REG, buffer,
243 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
244 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY);
251 static int anx78xx_set_hpd(struct anx78xx *anx78xx)
255 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
256 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
260 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
268 static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
272 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
277 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
278 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
285 static const struct reg_sequence tmds_phy_initialization[] = {
286 { SP_TMDS_CTRL_BASE + 1, 0x90 },
287 { SP_TMDS_CTRL_BASE + 2, 0xa9 },
288 { SP_TMDS_CTRL_BASE + 6, 0x92 },
289 { SP_TMDS_CTRL_BASE + 7, 0x80 },
290 { SP_TMDS_CTRL_BASE + 20, 0xf2 },
291 { SP_TMDS_CTRL_BASE + 22, 0xc4 },
292 { SP_TMDS_CTRL_BASE + 23, 0x18 },
295 static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
299 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
300 SP_AUD_MUTE | SP_VID_MUTE);
304 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
305 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
310 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
311 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
312 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
316 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
317 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
318 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
322 /* Sync detect change, GP set mute */
323 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
324 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
329 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
330 SP_AUD_EXCEPTION_ENABLE_BASE + 3,
335 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
336 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
340 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
341 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
345 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
346 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
350 /* Enable DDC stretch */
351 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
352 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
356 /* TMDS phy initialization */
357 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
358 tmds_phy_initialization,
359 ARRAY_SIZE(tmds_phy_initialization));
363 err = anx78xx_clear_hpd(anx78xx);
370 static const u8 dp_tx_output_precise_tune_bits[20] = {
371 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
372 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
373 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
376 static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
381 * REVISIT : It is writing to a RESERVED bits in Analog Control 0
384 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
390 * Write DP TX output emphasis precise tune bits.
392 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
393 SP_DP_TX_LT_CTRL0_REG,
394 dp_tx_output_precise_tune_bits,
395 ARRAY_SIZE(dp_tx_output_precise_tune_bits));
403 static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
408 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
409 SP_ANALOG_DEBUG2_REG,
410 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
415 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
416 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
420 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
421 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
425 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
426 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
430 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
431 SP_I2C_GEN_10US_TIMER1_REG,
432 (XTAL_CLK & 0xff00) >> 8);
436 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
441 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
442 SP_HDMI_US_TIMER_CTRL_REG,
447 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
448 SP_HDMI_US_TIMER_CTRL_REG,
449 (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
450 ((((XTAL_CLK / 10) >> 1) - 2) << 3));
457 static const struct reg_sequence otp_key_protect[] = {
458 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
459 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
460 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
463 static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
467 /* Set terminal resistor to 50 ohm */
468 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
473 /* Enable aux double diff output */
474 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
475 SP_DP_AUX_CH_CTRL2_REG, 0x08);
479 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
480 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
485 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
487 ARRAY_SIZE(otp_key_protect));
491 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
492 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
496 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
502 * DP HDCP auto authentication wait timer (when downstream starts to
503 * auth, DP side will wait for this period then do auth automatically)
505 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
510 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
511 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
515 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
516 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
520 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
521 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
525 err = anx78xx_xtal_clk_sel(anx78xx);
529 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
530 SP_DEFER_CTRL_EN | 0x0c);
534 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
535 SP_DP_POLLING_CTRL_REG,
536 SP_AUTO_POLLING_DISABLE);
541 * Short the link integrity check timer to speed up bstatus
542 * polling for HDCP CTS item 1A-07
544 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
545 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
549 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
550 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
554 /* Power down the main link by default */
555 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
556 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
560 err = anx78xx_link_phy_initialization(anx78xx);
564 /* Gen m_clk with downspreading */
565 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
566 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
573 static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
578 * BIT0: INT pin assertion polarity: 1 = assert high
579 * BIT1: INT pin output type: 0 = push/pull
581 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
585 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
586 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
590 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
595 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
596 SP_CKDT_CHG | SP_SCDT_CHG);
603 static void anx78xx_poweron(struct anx78xx *anx78xx)
605 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
608 if (WARN_ON(anx78xx->powered))
612 err = regulator_enable(pdata->dvdd10);
614 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
619 usleep_range(1000, 2000);
622 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
623 usleep_range(1000, 2000);
625 gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
626 usleep_range(1000, 2000);
628 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
630 /* Power on registers module */
631 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
632 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
633 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
634 SP_REGISTER_PD | SP_TOTAL_PD);
636 anx78xx->powered = true;
639 static void anx78xx_poweroff(struct anx78xx *anx78xx)
641 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
644 if (WARN_ON(!anx78xx->powered))
647 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
648 usleep_range(1000, 2000);
650 gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
651 usleep_range(1000, 2000);
654 err = regulator_disable(pdata->dvdd10);
656 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
661 usleep_range(1000, 2000);
664 anx78xx->powered = false;
667 static int anx78xx_start(struct anx78xx *anx78xx)
671 /* Power on all modules */
672 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
673 SP_POWERDOWN_CTRL_REG,
674 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
677 err = anx78xx_enable_interrupts(anx78xx);
679 DRM_ERROR("Failed to enable interrupts: %d\n", err);
683 err = anx78xx_rx_initialization(anx78xx);
685 DRM_ERROR("Failed receiver initialization: %d\n", err);
689 err = anx78xx_tx_initialization(anx78xx);
691 DRM_ERROR("Failed transmitter initialization: %d\n", err);
696 * This delay seems to help keep the hardware in a good state. Without
697 * it, there are times where it fails silently.
699 usleep_range(10000, 15000);
704 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
705 anx78xx_poweroff(anx78xx);
710 static int anx78xx_init_pdata(struct anx78xx *anx78xx)
712 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
713 struct device *dev = &anx78xx->client->dev;
715 /* 1.0V digital core power regulator */
716 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
717 if (IS_ERR(pdata->dvdd10)) {
718 DRM_ERROR("DVDD10 regulator not found\n");
719 return PTR_ERR(pdata->dvdd10);
723 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
724 if (IS_ERR(pdata->gpiod_hpd))
725 return PTR_ERR(pdata->gpiod_hpd);
727 /* GPIO for chip power down */
728 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
729 if (IS_ERR(pdata->gpiod_pd))
730 return PTR_ERR(pdata->gpiod_pd);
732 /* GPIO for chip reset */
733 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
735 return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
738 static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
743 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
748 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
749 SP_POWERDOWN_CTRL_REG,
754 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
759 case DP_LINK_BW_1_62:
765 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
769 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
774 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
775 SP_VID_CTRL1_REG, SP_VIDEO_EN);
780 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
781 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
783 DRM_ERROR("Failed to read DPCD: %d\n", err);
787 /* Clear channel x SERDES power down */
788 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
789 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
793 /* Check link capabilities */
794 err = drm_dp_link_probe(&anx78xx->aux, &anx78xx->link);
796 DRM_ERROR("Failed to probe link capabilities: %d\n", err);
800 /* Power up the sink */
801 err = drm_dp_link_power_up(&anx78xx->aux, &anx78xx->link);
803 DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
807 /* Possibly enable downspread on the sink */
808 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
809 SP_DP_DOWNSPREAD_CTRL1_REG, 0);
813 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
814 DRM_DEBUG("Enable downspread on the sink\n");
816 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
817 SP_DP_DOWNSPREAD_CTRL1_REG, 8);
821 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
826 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
831 /* Set the lane count and the link rate on the sink */
832 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
833 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
834 SP_DP_SYSTEM_CTRL_BASE + 4,
837 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
838 SP_DP_SYSTEM_CTRL_BASE + 4,
843 value = drm_dp_link_rate_to_bw_code(anx78xx->link.rate);
844 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
845 SP_DP_MAIN_LINK_BW_SET_REG, value);
849 err = drm_dp_link_configure(&anx78xx->aux, &anx78xx->link);
851 DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
855 /* Start training on the source */
856 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
864 static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
868 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
873 /* Enable DP output */
874 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
882 static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
883 struct hdmi_avi_infoframe *frame)
885 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
888 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
890 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
894 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
895 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
899 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
900 SP_INFOFRAME_AVI_DB1_REG, buffer,
905 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
906 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
910 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
911 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
918 static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
923 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
925 DRM_ERROR("Get sink count failed %d\n", err);
929 if (!DP_GET_SINK_COUNT(value)) {
930 DRM_ERROR("Downstream disconnected\n");
937 static int anx78xx_get_modes(struct drm_connector *connector)
939 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
940 int err, num_modes = 0;
942 if (WARN_ON(!anx78xx->powered))
946 return drm_add_edid_modes(connector, anx78xx->edid);
948 mutex_lock(&anx78xx->lock);
950 err = anx78xx_get_downstream_info(anx78xx);
952 DRM_ERROR("Failed to get downstream info: %d\n", err);
956 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);
957 if (!anx78xx->edid) {
958 DRM_ERROR("Failed to read EDID\n");
962 err = drm_connector_update_edid_property(connector,
965 DRM_ERROR("Failed to update EDID property: %d\n", err);
969 num_modes = drm_add_edid_modes(connector, anx78xx->edid);
972 mutex_unlock(&anx78xx->lock);
977 static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
978 .get_modes = anx78xx_get_modes,
981 static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
984 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
986 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
987 return connector_status_disconnected;
989 return connector_status_connected;
992 static const struct drm_connector_funcs anx78xx_connector_funcs = {
993 .fill_modes = drm_helper_probe_single_connector_modes,
994 .detect = anx78xx_detect,
995 .destroy = drm_connector_cleanup,
996 .reset = drm_atomic_helper_connector_reset,
997 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
998 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1001 static int anx78xx_bridge_attach(struct drm_bridge *bridge)
1003 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1006 if (!bridge->encoder) {
1007 DRM_ERROR("Parent encoder object not found");
1011 /* Register aux channel */
1012 anx78xx->aux.name = "DP-AUX";
1013 anx78xx->aux.dev = &anx78xx->client->dev;
1014 anx78xx->aux.transfer = anx78xx_aux_transfer;
1016 err = drm_dp_aux_register(&anx78xx->aux);
1018 DRM_ERROR("Failed to register aux channel: %d\n", err);
1022 err = drm_connector_init(bridge->dev, &anx78xx->connector,
1023 &anx78xx_connector_funcs,
1024 DRM_MODE_CONNECTOR_DisplayPort);
1026 DRM_ERROR("Failed to initialize connector: %d\n", err);
1030 drm_connector_helper_add(&anx78xx->connector,
1031 &anx78xx_connector_helper_funcs);
1033 err = drm_connector_register(&anx78xx->connector);
1035 DRM_ERROR("Failed to register connector: %d\n", err);
1039 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
1041 err = drm_connector_attach_encoder(&anx78xx->connector,
1044 DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
1051 static enum drm_mode_status
1052 anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
1053 const struct drm_display_mode *mode)
1055 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1056 return MODE_NO_INTERLACE;
1058 /* Max 1200p at 5.4 Ghz, one lane */
1059 if (mode->clock > 154000)
1060 return MODE_CLOCK_HIGH;
1065 static void anx78xx_bridge_disable(struct drm_bridge *bridge)
1067 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1069 /* Power off all modules except configuration registers access */
1070 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
1071 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
1074 static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
1075 const struct drm_display_mode *mode,
1076 const struct drm_display_mode *adjusted_mode)
1078 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1079 struct hdmi_avi_infoframe frame;
1082 if (WARN_ON(!anx78xx->powered))
1085 mutex_lock(&anx78xx->lock);
1087 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1088 &anx78xx->connector,
1091 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
1095 err = anx78xx_send_video_infoframe(anx78xx, &frame);
1097 DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
1100 mutex_unlock(&anx78xx->lock);
1103 static void anx78xx_bridge_enable(struct drm_bridge *bridge)
1105 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1108 err = anx78xx_start(anx78xx);
1110 DRM_ERROR("Failed to initialize: %d\n", err);
1114 err = anx78xx_set_hpd(anx78xx);
1116 DRM_ERROR("Failed to set HPD: %d\n", err);
1119 static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
1120 .attach = anx78xx_bridge_attach,
1121 .mode_valid = anx78xx_bridge_mode_valid,
1122 .disable = anx78xx_bridge_disable,
1123 .mode_set = anx78xx_bridge_mode_set,
1124 .enable = anx78xx_bridge_enable,
1127 static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
1129 struct anx78xx *anx78xx = data;
1132 if (anx78xx->powered)
1135 mutex_lock(&anx78xx->lock);
1137 /* Cable is pulled, power on the chip */
1138 anx78xx_poweron(anx78xx);
1140 err = anx78xx_enable_interrupts(anx78xx);
1142 DRM_ERROR("Failed to enable interrupts: %d\n", err);
1144 mutex_unlock(&anx78xx->lock);
1149 static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
1153 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
1155 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1160 if (irq & SP_TRAINING_FINISH) {
1161 DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
1162 err = anx78xx_config_dp_output(anx78xx);
1168 static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
1173 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
1175 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1176 SP_COMMON_INT_STATUS4_REG, irq);
1178 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1182 if (irq & SP_HPD_LOST) {
1183 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
1185 anx78xx_poweroff(anx78xx);
1186 /* Free cached EDID */
1187 kfree(anx78xx->edid);
1188 anx78xx->edid = NULL;
1189 } else if (irq & SP_HPD_PLUG) {
1190 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1197 static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
1202 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
1204 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1207 DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1211 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
1212 DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
1214 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1215 SP_SYSTEM_STATUS_REG, &value);
1217 DRM_ERROR("Read system status reg failed: %d\n", err);
1221 if (!(value & SP_TMDS_CLOCK_DET)) {
1222 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
1226 if (!(value & SP_TMDS_DE_DET)) {
1227 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
1231 err = anx78xx_dp_link_training(anx78xx);
1233 DRM_ERROR("Failed to start link training: %d\n", err);
1237 static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
1239 struct anx78xx *anx78xx = data;
1244 mutex_lock(&anx78xx->lock);
1246 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1249 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1254 anx78xx_handle_dp_int_1(anx78xx, irq);
1256 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1257 SP_COMMON_INT_STATUS4_REG, &irq);
1259 DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
1265 event = anx78xx_handle_common_int_4(anx78xx, irq);
1267 /* Make sure we are still powered after handle HPD events */
1268 if (!anx78xx->powered)
1271 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1274 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1279 anx78xx_handle_hdmi_int_1(anx78xx, irq);
1282 mutex_unlock(&anx78xx->lock);
1285 drm_helper_hpd_irq_event(anx78xx->connector.dev);
1290 static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
1294 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
1295 i2c_unregister_device(anx78xx->i2c_dummy[i]);
1298 static const struct regmap_config anx78xx_regmap_config = {
1303 static const u16 anx78xx_chipid_list[] = {
1309 static int anx78xx_i2c_probe(struct i2c_client *client,
1310 const struct i2c_device_id *id)
1312 struct anx78xx *anx78xx;
1313 struct anx78xx_platform_data *pdata;
1314 unsigned int i, idl, idh, version;
1318 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
1322 pdata = &anx78xx->pdata;
1324 mutex_init(&anx78xx->lock);
1326 #if IS_ENABLED(CONFIG_OF)
1327 anx78xx->bridge.of_node = client->dev.of_node;
1330 anx78xx->client = client;
1331 i2c_set_clientdata(client, anx78xx);
1333 err = anx78xx_init_pdata(anx78xx);
1335 DRM_ERROR("Failed to initialize pdata: %d\n", err);
1339 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
1340 if (pdata->hpd_irq < 0) {
1341 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
1345 pdata->intp_irq = client->irq;
1346 if (!pdata->intp_irq) {
1347 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
1351 /* Map slave addresses of ANX7814 */
1352 for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
1353 anx78xx->i2c_dummy[i] = i2c_new_dummy(client->adapter,
1354 anx78xx_i2c_addresses[i] >> 1);
1355 if (!anx78xx->i2c_dummy[i]) {
1357 DRM_ERROR("Failed to reserve I2C bus %02x\n",
1358 anx78xx_i2c_addresses[i]);
1359 goto err_unregister_i2c;
1362 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
1363 &anx78xx_regmap_config);
1364 if (IS_ERR(anx78xx->map[i])) {
1365 err = PTR_ERR(anx78xx->map[i]);
1366 DRM_ERROR("Failed regmap initialization %02x\n",
1367 anx78xx_i2c_addresses[i]);
1368 goto err_unregister_i2c;
1372 /* Look for supported chip ID */
1373 anx78xx_poweron(anx78xx);
1375 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1380 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1385 anx78xx->chipid = (u8)idl | ((u8)idh << 8);
1387 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1392 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
1393 if (anx78xx->chipid == anx78xx_chipid_list[i]) {
1394 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
1395 anx78xx->chipid, version);
1402 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
1403 anx78xx->chipid, version);
1408 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1409 anx78xx_hpd_threaded_handler,
1410 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1411 "anx78xx-hpd", anx78xx);
1413 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
1418 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1419 anx78xx_intp_threaded_handler,
1420 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1421 "anx78xx-intp", anx78xx);
1423 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1427 anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
1429 drm_bridge_add(&anx78xx->bridge);
1431 /* If cable is pulled out, just poweroff and wait for HPD event */
1432 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1433 anx78xx_poweroff(anx78xx);
1438 anx78xx_poweroff(anx78xx);
1441 unregister_i2c_dummy_clients(anx78xx);
1445 static int anx78xx_i2c_remove(struct i2c_client *client)
1447 struct anx78xx *anx78xx = i2c_get_clientdata(client);
1449 drm_bridge_remove(&anx78xx->bridge);
1451 unregister_i2c_dummy_clients(anx78xx);
1453 kfree(anx78xx->edid);
1458 static const struct i2c_device_id anx78xx_id[] = {
1462 MODULE_DEVICE_TABLE(i2c, anx78xx_id);
1464 #if IS_ENABLED(CONFIG_OF)
1465 static const struct of_device_id anx78xx_match_table[] = {
1466 { .compatible = "analogix,anx7814", },
1469 MODULE_DEVICE_TABLE(of, anx78xx_match_table);
1472 static struct i2c_driver anx78xx_driver = {
1475 .of_match_table = of_match_ptr(anx78xx_match_table),
1477 .probe = anx78xx_i2c_probe,
1478 .remove = anx78xx_i2c_remove,
1479 .id_table = anx78xx_id,
1481 module_i2c_driver(anx78xx_driver);
1483 MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
1484 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
1485 MODULE_LICENSE("GPL v2");