2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef _SMU73_DISCRETE_H_
24 #define _SMU73_DISCRETE_H_
37 typedef struct SMIO_Pattern SMIO_Pattern;
41 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
44 typedef struct SMIO_Table SMIO_Table;
46 struct SMU73_Discrete_GraphicsLevel {
49 uint32_t SclkFrequency;
52 uint8_t DeepSleepDivId;
53 uint16_t ActivityLevel;
54 uint32_t CgSpllFuncCntl3;
55 uint32_t CgSpllFuncCntl4;
56 uint32_t SpllSpreadSpectrum;
57 uint32_t SpllSpreadSpectrum2;
61 uint8_t DisplayWatermark;
62 uint8_t EnabledForActivity;
63 uint8_t EnabledForThrottle;
66 uint8_t VoltageDownHyst;
67 uint8_t PowerThrottle;
70 typedef struct SMU73_Discrete_GraphicsLevel SMU73_Discrete_GraphicsLevel;
72 struct SMU73_Discrete_ACPILevel {
75 uint32_t SclkFrequency;
77 uint8_t DisplayWatermark;
78 uint8_t DeepSleepDivId;
80 uint32_t CgSpllFuncCntl;
81 uint32_t CgSpllFuncCntl2;
82 uint32_t CgSpllFuncCntl3;
83 uint32_t CgSpllFuncCntl4;
84 uint32_t SpllSpreadSpectrum;
85 uint32_t SpllSpreadSpectrum2;
90 typedef struct SMU73_Discrete_ACPILevel SMU73_Discrete_ACPILevel;
92 struct SMU73_Discrete_Ulv {
96 uint8_t VddcOffsetVid;
101 typedef struct SMU73_Discrete_Ulv SMU73_Discrete_Ulv;
103 struct SMU73_Discrete_MemoryLevel
108 uint32_t MclkFrequency;
110 uint8_t StutterEnable;
112 uint8_t EnabledForThrottle;
113 uint8_t EnabledForActivity;
117 uint8_t VoltageDownHyst;
120 uint16_t ActivityLevel;
121 uint8_t DisplayWatermark;
125 typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel;
127 struct SMU73_Discrete_LinkLevel
129 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
130 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
131 uint8_t EnabledForActivity;
133 uint32_t DownThreshold;
134 uint32_t UpThreshold;
138 typedef struct SMU73_Discrete_LinkLevel SMU73_Discrete_LinkLevel;
141 // MC ARB DRAM Timing registers.
142 struct SMU73_Discrete_MCArbDramTimingTableEntry
144 uint32_t McArbDramTiming;
145 uint32_t McArbDramTiming2;
146 uint8_t McArbBurstTime;
152 typedef struct SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MCArbDramTimingTableEntry;
154 struct SMU73_Discrete_MCArbDramTimingTable
156 SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
159 typedef struct SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTable;
161 // UVD VCLK/DCLK state (level) definition.
162 struct SMU73_Discrete_UvdLevel
164 uint32_t VclkFrequency;
165 uint32_t DclkFrequency;
172 typedef struct SMU73_Discrete_UvdLevel SMU73_Discrete_UvdLevel;
174 // Clocks for other external blocks (VCE, ACP, SAMU).
175 struct SMU73_Discrete_ExtClkLevel
183 typedef struct SMU73_Discrete_ExtClkLevel SMU73_Discrete_ExtClkLevel;
185 struct SMU73_Discrete_StateInfo
187 uint32_t SclkFrequency;
188 uint32_t MclkFrequency;
189 uint32_t VclkFrequency;
190 uint32_t DclkFrequency;
191 uint32_t SamclkFrequency;
192 uint32_t AclkFrequency;
193 uint32_t EclkFrequency;
194 uint16_t MvddVoltage;
196 uint8_t DisplayWatermark;
207 typedef struct SMU73_Discrete_StateInfo SMU73_Discrete_StateInfo;
209 struct SMU73_Discrete_DpmTable
211 // Multi-DPM controller settings
212 SMU73_PIDController GraphicsPIDController;
213 SMU73_PIDController MemoryPIDController;
214 SMU73_PIDController LinkPIDController;
216 uint32_t SystemFlags;
218 // SMIO masks for voltage and phase controls
222 SMIO_Table SmioTable1;
223 SMIO_Table SmioTable2;
225 uint32_t MvddLevelCount;
228 uint8_t BapmVddcVidHiSidd [SMU73_MAX_LEVELS_VDDC];
229 uint8_t BapmVddcVidLoSidd [SMU73_MAX_LEVELS_VDDC];
230 uint8_t BapmVddcVidHiSidd2 [SMU73_MAX_LEVELS_VDDC];
232 uint8_t GraphicsDpmLevelCount;
233 uint8_t MemoryDpmLevelCount;
234 uint8_t LinkLevelCount;
235 uint8_t MasterDeepSleepControl;
237 uint8_t UvdLevelCount;
238 uint8_t VceLevelCount;
239 uint8_t AcpLevelCount;
240 uint8_t SamuLevelCount;
242 uint8_t ThermOutGpio;
243 uint8_t ThermOutPolarity;
244 uint8_t ThermOutMode;
246 uint32_t Reserved[4];
248 // State table entries for each DPM state
249 SMU73_Discrete_GraphicsLevel GraphicsLevel [SMU73_MAX_LEVELS_GRAPHICS];
250 SMU73_Discrete_MemoryLevel MemoryACPILevel;
251 SMU73_Discrete_MemoryLevel MemoryLevel [SMU73_MAX_LEVELS_MEMORY];
252 SMU73_Discrete_LinkLevel LinkLevel [SMU73_MAX_LEVELS_LINK];
253 SMU73_Discrete_ACPILevel ACPILevel;
254 SMU73_Discrete_UvdLevel UvdLevel [SMU73_MAX_LEVELS_UVD];
255 SMU73_Discrete_ExtClkLevel VceLevel [SMU73_MAX_LEVELS_VCE];
256 SMU73_Discrete_ExtClkLevel AcpLevel [SMU73_MAX_LEVELS_ACP];
257 SMU73_Discrete_ExtClkLevel SamuLevel [SMU73_MAX_LEVELS_SAMU];
258 SMU73_Discrete_Ulv Ulv;
260 uint32_t SclkStepSize;
261 uint32_t Smio [SMU73_MAX_ENTRIES_SMIO];
263 uint8_t UvdBootLevel;
264 uint8_t VceBootLevel;
265 uint8_t AcpBootLevel;
266 uint8_t SamuBootLevel;
268 uint8_t GraphicsBootLevel;
269 uint8_t GraphicsVoltageChangeEnable;
270 uint8_t GraphicsThermThrottleEnable;
271 uint8_t GraphicsInterval;
273 uint8_t VoltageInterval;
274 uint8_t ThermalInterval;
275 uint16_t TemperatureLimitHigh;
277 uint16_t TemperatureLimitLow;
278 uint8_t MemoryBootLevel;
279 uint8_t MemoryVoltageChangeEnable;
282 uint8_t MemoryInterval;
283 uint8_t MemoryThermThrottleEnable;
285 uint16_t VoltageResponseTime;
286 uint16_t PhaseResponseTime;
288 uint8_t PCIeBootLinkLevel;
289 uint8_t PCIeGenInterval;
298 uint16_t PPM_PkgPwrLimit;
299 uint16_t PPM_TemperatureLimit;
304 uint16_t FpsHighThreshold;
305 uint16_t FpsLowThreshold;
307 uint16_t TemperatureLimitEdge;
308 uint16_t TemperatureLimitHotspot;
309 uint16_t TemperatureLimitLiquid1;
310 uint16_t TemperatureLimitLiquid2;
311 uint16_t TemperatureLimitVrVddc;
312 uint16_t TemperatureLimitVrMvdd;
313 uint16_t TemperatureLimitPlx;
315 uint16_t FanGainEdge;
316 uint16_t FanGainHotspot;
317 uint16_t FanGainLiquid;
318 uint16_t FanGainVrVddc;
319 uint16_t FanGainVrMvdd;
323 uint8_t Liquid1_I2C_address;
324 uint8_t Liquid2_I2C_address;
325 uint8_t Vr_I2C_address;
326 uint8_t Plx_I2C_address;
330 uint32_t GeminiApertureHigh;
331 uint32_t GeminiApertureLow;
333 uint8_t Liquid_I2C_LineSCL;
334 uint8_t Liquid_I2C_LineSDA;
335 uint8_t Vr_I2C_LineSCL;
336 uint8_t Vr_I2C_LineSDA;
337 uint8_t Plx_I2C_LineSCL;
338 uint8_t Plx_I2C_LineSDA;
340 uint8_t spare1253[2];
341 uint32_t spare123[2];
343 uint8_t DTEAmbientTempBase;
351 uint32_t BAPM_TEMP_GRADIENT;
353 uint32_t LowSclkInterruptThreshold;
354 uint32_t VddGfxReChkWait;
356 uint8_t ClockStretcherAmount;
357 uint8_t Sclk_CKS_masterEn0_7;
358 uint8_t Sclk_CKS_masterEn8_15;
359 uint8_t DPMFreezeAndForced;
361 uint8_t Sclk_voltageOffset[8];
363 SMU_ClockStretcherDataTable ClockStretcherDataTable;
364 SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
367 typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable;
370 // --------------------------------------------------- Fan Table -----------------------------------------------------------
371 struct SMU73_Discrete_FanTable
387 uint32_t RefreshPeriod;
393 typedef struct SMU73_Discrete_FanTable SMU73_Discrete_FanTable;
395 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
396 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
400 struct SMU7_MclkDpmScoreboard
403 uint32_t PercentageBusy;
409 uint32_t SigmaDeltaAccum;
410 uint32_t SigmaDeltaOutput;
411 uint32_t SigmaDeltaLevel;
413 uint32_t UtilizationSetpoint;
415 uint8_t TdpClampMode;
416 uint8_t TdcClampMode;
417 uint8_t ThermClampMode;
422 uint8_t LevelChangeInProgress;
426 uint8_t VoltageDownHyst;
431 uint8_t DpmForceLevel;
432 uint8_t DisplayWatermark;
435 uint32_t MinimumPerfMclk;
439 uint8_t MclkSwitchInProgress;
440 uint8_t MclkSwitchCritical;
442 uint8_t IgnoreVBlank;
443 uint8_t TargetMclkIndex;
444 uint8_t TargetMvddIndex;
445 uint8_t MclkSwitchResult;
447 uint16_t VbiFailureCount;
448 uint8_t VbiWaitCounter;
449 uint8_t EnabledLevelsChange;
451 uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_MEMORY];
452 uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_MEMORY];
454 void (*TargetStateCalculator)(uint8_t);
455 void (*SavedTargetStateCalculator)(uint8_t);
457 uint16_t AutoDpmInterval;
458 uint16_t AutoDpmRange;
460 uint16_t VbiTimeoutCount;
461 uint16_t MclkSwitchingTime;
464 uint8_t Save_PIC_VDDGFX_EXIT;
465 uint8_t Save_PIC_VDDGFX_ENTER;
470 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
472 struct SMU7_UlvScoreboard
477 uint8_t WaitingForUlv;
480 uint8_t UlvMasterEnable;
482 uint32_t UlvAbortedCount;
483 uint32_t UlvTimeStamp;
486 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
488 struct VddgfxSavedRegisters
491 uint32_t MEC_BaseAddress_Hi;
492 uint32_t MEC_BaseAddress_Lo;
493 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
494 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
495 uint32_t CP_INT_CNTL;
498 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
500 struct SMU7_VddGfxScoreboard
502 uint8_t VddGfxEnable;
503 uint8_t VddGfxActive;
504 uint8_t VPUResetOccured;
507 uint32_t VddGfxEnteredCount;
508 uint32_t VddGfxAbortedCount;
512 VddgfxSavedRegisters SavedRegisters;
515 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
517 struct SMU7_TdcLimitScoreboard {
521 uint32_t FilteredIddc;
524 SMU7_HystController_Data HystControllerData;
527 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
529 struct SMU7_PkgPwrLimitScoreboard {
533 uint32_t FilteredPkgPwr;
536 uint32_t LimitFromDriver;
537 SMU7_HystController_Data HystControllerData;
540 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
542 struct SMU7_BapmScoreboard {
543 uint32_t source_powers[SMU73_DTE_SOURCES];
544 uint32_t source_powers_last[SMU73_DTE_SOURCES];
545 int32_t entity_temperatures[SMU73_NUM_GPU_TES];
546 int32_t initial_entity_temperatures[SMU73_NUM_GPU_TES];
549 int32_t therm_influence_coeff_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS * 2];
550 int32_t therm_node_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS];
551 uint16_t ConfigTDPPowerScalar;
552 uint16_t FanSpeedPowerScalar;
553 uint16_t OverDrivePowerScalar;
554 uint16_t OverDriveLimitScalar;
555 uint16_t FinalPowerScalar;
559 SMU7_HystController_Data HystControllerData;
561 int32_t temperature_gradient_slope;
562 int32_t temperature_gradient;
563 uint32_t measured_temperature;
567 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
569 struct SMU7_AcpiScoreboard {
570 uint32_t SavedInterruptMask[2];
571 uint8_t LastACPIRequest;
575 SMU73_Discrete_ACPILevel D0Level;
578 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
580 struct SMU_QuadraticCoeffs {
589 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
591 struct SMU73_Discrete_PmFuses {
593 uint8_t BapmVddCVidHiSidd[8];
596 uint8_t BapmVddCVidLoSidd[8];
602 uint8_t SviLoadLineEn;
603 uint8_t SviLoadLineVddC;
604 uint8_t SviLoadLineTrimVddC;
605 uint8_t SviLoadLineOffsetVddC;
608 uint16_t TDC_VDDC_PkgLimit;
609 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
613 uint8_t TdcWaterfallCtl;
614 uint8_t LPMLTemperatureMin;
615 uint8_t LPMLTemperatureMax;
619 uint8_t LPMLTemperatureScaler[16];
622 int16_t FuzzyFan_ErrorSetDelta;
623 int16_t FuzzyFan_ErrorRateSetDelta;
624 int16_t FuzzyFan_PwmSetDelta;
631 uint8_t GnbLPMLMaxVid;
632 uint8_t GnbLPMLMinVid;
633 uint8_t Reserved1[2];
636 uint16_t BapmVddCBaseLeakageHiSidd;
637 uint16_t BapmVddCBaseLeakageLoSidd;
640 uint16_t VFT_Temp[3];
643 SMU_QuadraticCoeffs VFT_ATE[3];
645 SMU_QuadraticCoeffs AVFS_GB;
646 SMU_QuadraticCoeffs ATE_ACBTC_GB;
648 SMU_QuadraticCoeffs P2V;
650 uint32_t PsmCharzFreq;
652 uint16_t InversionVoltage;
653 uint16_t PsmCharzTemp;
655 uint32_t EnabledAvfsModules;
658 typedef struct SMU73_Discrete_PmFuses SMU73_Discrete_PmFuses;
660 struct SMU7_Discrete_Log_Header_Table {
666 uint32_t num_of_entries;
670 uint32_t filler_1[2];
673 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
675 struct SMU7_Discrete_Log_Cntl {
680 uint32_t SamplesLogged;
686 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
688 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
690 struct SMU7_Discrete_Cac_Collection_Table {
691 uint32_t temperature;
692 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
695 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
697 struct SMU7_Discrete_Cac_Verification_Table {
698 uint32_t VddcTotalPower;
699 uint32_t VddcLeakagePower;
700 uint32_t VddcConstantPower;
701 uint32_t VddcGfxDynamicPower;
702 uint32_t VddcUvdDynamicPower;
703 uint32_t VddcVceDynamicPower;
704 uint32_t VddcAcpDynamicPower;
705 uint32_t VddcPcieDynamicPower;
706 uint32_t VddcDceDynamicPower;
707 uint32_t VddcCurrent;
708 uint32_t VddcVoltage;
709 uint32_t VddciTotalPower;
710 uint32_t VddciLeakagePower;
711 uint32_t VddciConstantPower;
712 uint32_t VddciDynamicPower;
713 uint32_t Vddr1TotalPower;
714 uint32_t Vddr1LeakagePower;
715 uint32_t Vddr1ConstantPower;
716 uint32_t Vddr1DynamicPower;
718 uint32_t temperature;
721 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
723 struct SMU7_Discrete_Pm_Status_Table {
725 int32_t T_meas_max[SMU73_THERMAL_INPUT_LOOP_COUNT];
726 int32_t T_meas_acc[SMU73_THERMAL_INPUT_LOOP_COUNT];
727 int32_t T_meas_acc_cnt[SMU73_THERMAL_INPUT_LOOP_COUNT];
734 uint32_t V_meas_load_acc;
736 uint32_t P_meas_acc_vddci;
737 uint32_t V_meas_load_acc_vddci;
738 uint32_t I_meas_acc_vddci;
741 uint16_t Sclk_dpm_residency[8];
742 uint16_t Uvd_dpm_residency[8];
743 uint16_t Vce_dpm_residency[8];
749 uint32_t MclkSwitchingTime_max;
750 uint32_t MclkSwitchingTime_acc;
753 uint32_t Gfx_busy_acc;
754 uint32_t Mc_busy_acc;
760 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
762 //FIXME THESE NEED TO BE UPDATED
763 #define SMU7_SCLK_CAC 0x561
764 #define SMU7_MCLK_CAC 0xF9
765 #define SMU7_VCLK_CAC 0x2DE
766 #define SMU7_DCLK_CAC 0x2DE
767 #define SMU7_ECLK_CAC 0x25E
768 #define SMU7_ACLK_CAC 0x25E
769 #define SMU7_SAMCLK_CAC 0x25E
770 #define SMU7_DISPCLK_CAC 0x100
771 #define SMU7_CAC_CONSTANT 0x2EE3430
772 #define SMU7_CAC_CONSTANT_SHIFT 18
774 #define SMU7_VDDCI_MCLK_CONST 1765
775 #define SMU7_VDDCI_MCLK_CONST_SHIFT 16
776 #define SMU7_VDDCI_VDDCI_CONST 50958
777 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
778 #define SMU7_VDDCI_CONST 11781
779 #define SMU7_VDDCI_STROBE_PWR 1331
781 #define SMU7_VDDR1_CONST 693
782 #define SMU7_VDDR1_CAC_WEIGHT 20
783 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
784 #define SMU7_VDDR1_STROBE_PWR 512
786 #define SMU7_AREA_COEFF_UVD 0xA78
787 #define SMU7_AREA_COEFF_VCE 0x190A
788 #define SMU7_AREA_COEFF_ACP 0x22D1
789 #define SMU7_AREA_COEFF_SAMU 0x534
791 //ThermOutMode values
792 #define SMU7_THERM_OUT_MODE_DISABLE 0x0
793 #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
794 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2