drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "hwmgr.h"
  25 #include "vega10_hwmgr.h"
  26 #include "vega10_smumgr.h"
  27 #include "vega10_powertune.h"
  28 #include "vega10_ppsmc.h"
  29 #include "vega10_inc.h"
  30 #include "pp_debug.h"
  31 #include "soc15_common.h"
  32
  33 static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] =
  34 {
  35 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  36  *      Offset                             Mask                                                 Shift                                                  Value
  37  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  38  */
  39         /* DIDT_SQ */
  40         {   ixDIDT_SQ_TUNING_CTRL,             DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,        DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,        0x3853 },
  41         {   ixDIDT_SQ_TUNING_CTRL,             DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,        DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,        0x3153 },
  42
  43         /* DIDT_TD */
  44         {   ixDIDT_TD_TUNING_CTRL,             DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,        DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,        0x0dde },
  45         {   ixDIDT_TD_TUNING_CTRL,             DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,        DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,        0x0dde },
  46
  47         /* DIDT_TCP */
  48         {   ixDIDT_TCP_TUNING_CTRL,            DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,       DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,       0x3dde },
  49         {   ixDIDT_TCP_TUNING_CTRL,            DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,       DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,       0x3dde },
  50
  51         /* DIDT_DB */
  52         {   ixDIDT_DB_TUNING_CTRL,             DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,        DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,        0x3dde },
  53         {   ixDIDT_DB_TUNING_CTRL,             DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,        DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,        0x3dde },
  54
  55         {   0xFFFFFFFF  }  /* End of list */
  56 };
  57
  58 static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] =
  59 {
  60 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  61  *      Offset               Mask                                                     Shift                                                            Value
  62  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  63  */
  64         /*DIDT_SQ_CTRL3 */
  65         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK,       DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT,             0x0000 },
  66         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,       DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,             0x0000 },
  67         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK,       DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT,             0x0003 },
  68         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,       DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,             0x0000 },
  69         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,       DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,             0x0000 },
  70         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,       DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,             0x0003 },
  71         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,       DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
  72         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,       DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
  73         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK,       DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT,             0x0000 },
  74         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK,       DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT,             0x0000 },
  75         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK,       DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT,             0x0000 },
  76         {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK,       DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,             0x0000 },
  77
  78         /*DIDT_TCP_CTRL3 */
  79         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK,      DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT,            0x0000 },
  80         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,      DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,            0x0000 },
  81         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK,      DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT,            0x0003 },
  82         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,      DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,            0x0000 },
  83         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,      DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,            0x0000 },
  84         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,      DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,            0x0003 },
  85         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,      DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,            0x0000 },
  86         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,      DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,            0x0000 },
  87         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK,      DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT,            0x0000 },
  88         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK,      DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT,            0x0000 },
  89         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK,      DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT,            0x0000 },
  90         {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK,      DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,            0x0000 },
  91
  92         /*DIDT_TD_CTRL3 */
  93         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK,       DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT,             0x0000 },
  94         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,       DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,             0x0000 },
  95         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__THROTTLE_POLICY_MASK,       DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT,             0x0003 },
  96         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,       DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,             0x0000 },
  97         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,       DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,             0x0000 },
  98         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,       DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,             0x0003 },
  99         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,       DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
 100         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,       DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
 101         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK,       DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT,             0x0000 },
 102         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK,       DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT,             0x0000 },
 103         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK,       DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT,             0x0000 },
 104         {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK,       DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,             0x0000 },
 105
 106         /*DIDT_DB_CTRL3 */
 107         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK,       DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT,             0x0000 },
 108         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,       DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,             0x0000 },
 109         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__THROTTLE_POLICY_MASK,       DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT,             0x0003 },
 110         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,       DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,             0x0000 },
 111         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,       DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,             0x0000 },
 112         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,       DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,             0x0003 },
 113         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,       DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
 114         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,       DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
 115         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK,       DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT,             0x0000 },
 116         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK,       DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT,             0x0000 },
 117         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK,       DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT,             0x0000 },
 118         {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK,       DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,             0x0000 },
 119
 120         {   0xFFFFFFFF  }  /* End of list */
 121 };
 122
 123 static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] =
 124 {
 125 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 126  *      Offset                            Mask                                                 Shift                                                  Value
 127  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 128  */
 129         /* DIDT_SQ */
 130         {   ixDIDT_SQ_CTRL2,                  DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK,                 DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT,                 0x3853 },
 131         {   ixDIDT_SQ_CTRL2,                  DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,        DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,        0x00c0 },
 132         {   ixDIDT_SQ_CTRL2,                  DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,        DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,        0x0000 },
 133
 134         /* DIDT_TD */
 135         {   ixDIDT_TD_CTRL2,                  DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK,                 DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT,                 0x3fff },
 136         {   ixDIDT_TD_CTRL2,                  DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,        DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,        0x00c0 },
 137         {   ixDIDT_TD_CTRL2,                  DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,        DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,        0x0001 },
 138
 139         /* DIDT_TCP */
 140         {   ixDIDT_TCP_CTRL2,                 DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK,                DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT,                0x3dde },
 141         {   ixDIDT_TCP_CTRL2,                 DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,       DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,       0x00c0 },
 142         {   ixDIDT_TCP_CTRL2,                 DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,       DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,       0x0001 },
 143
 144         /* DIDT_DB */
 145         {   ixDIDT_DB_CTRL2,                  DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK,                 DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT,                 0x3dde },
 146         {   ixDIDT_DB_CTRL2,                  DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,        DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,        0x00c0 },
 147         {   ixDIDT_DB_CTRL2,                  DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,        DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,        0x0001 },
 148
 149         {   0xFFFFFFFF  }  /* End of list */
 150 };
 151
 152 static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] =
 153 {
 154 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 155  *      Offset                             Mask                                                 Shift                                                  Value
 156  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 157  */
 158         /* DIDT_SQ */
 159         {   ixDIDT_SQ_CTRL1,                   DIDT_SQ_CTRL1__MIN_POWER_MASK,                       DIDT_SQ_CTRL1__MIN_POWER__SHIFT,                       0x0000 },
 160         {   ixDIDT_SQ_CTRL1,                   DIDT_SQ_CTRL1__MAX_POWER_MASK,                       DIDT_SQ_CTRL1__MAX_POWER__SHIFT,                       0xffff },
 161         /* DIDT_TD */
 162         {   ixDIDT_TD_CTRL1,                   DIDT_TD_CTRL1__MIN_POWER_MASK,                       DIDT_TD_CTRL1__MIN_POWER__SHIFT,                       0x0000 },
 163         {   ixDIDT_TD_CTRL1,                   DIDT_TD_CTRL1__MAX_POWER_MASK,                       DIDT_TD_CTRL1__MAX_POWER__SHIFT,                       0xffff },
 164         /* DIDT_TCP */
 165         {   ixDIDT_TCP_CTRL1,                  DIDT_TCP_CTRL1__MIN_POWER_MASK,                      DIDT_TCP_CTRL1__MIN_POWER__SHIFT,                      0x0000 },
 166         {   ixDIDT_TCP_CTRL1,                  DIDT_TCP_CTRL1__MAX_POWER_MASK,                      DIDT_TCP_CTRL1__MAX_POWER__SHIFT,                      0xffff },
 167         /* DIDT_DB */
 168         {   ixDIDT_DB_CTRL1,                   DIDT_DB_CTRL1__MIN_POWER_MASK,                       DIDT_DB_CTRL1__MIN_POWER__SHIFT,                       0x0000 },
 169         {   ixDIDT_DB_CTRL1,                   DIDT_DB_CTRL1__MAX_POWER_MASK,                       DIDT_DB_CTRL1__MAX_POWER__SHIFT,                       0xffff },
 170
 171         {   0xFFFFFFFF  }  /* End of list */
 172 };
 173
 174
 175 static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] =
 176 {
 177 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 178  *      Offset                             Mask                                                  Shift                                                 Value
 179  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 180  */
 181         /* DIDT_SQ */
 182         {   ixDIDT_SQ_WEIGHT0_3,               0xFFFFFFFF,                                           0,                                                    0x2B363B1A },
 183         {   ixDIDT_SQ_WEIGHT4_7,               0xFFFFFFFF,                                           0,                                                    0x270B2432 },
 184         {   ixDIDT_SQ_WEIGHT8_11,              0xFFFFFFFF,                                           0,                                                    0x00000018 },
 185
 186         /* DIDT_TD */
 187         {   ixDIDT_TD_WEIGHT0_3,               0xFFFFFFFF,                                           0,                                                    0x2B1D220F },
 188         {   ixDIDT_TD_WEIGHT4_7,               0xFFFFFFFF,                                           0,                                                    0x00007558 },
 189         {   ixDIDT_TD_WEIGHT8_11,              0xFFFFFFFF,                                           0,                                                    0x00000000 },
 190
 191         /* DIDT_TCP */
 192         {   ixDIDT_TCP_WEIGHT0_3,               0xFFFFFFFF,                                          0,                                                    0x5ACE160D },
 193         {   ixDIDT_TCP_WEIGHT4_7,               0xFFFFFFFF,                                          0,                                                    0x00000000 },
 194         {   ixDIDT_TCP_WEIGHT8_11,              0xFFFFFFFF,                                          0,                                                    0x00000000 },
 195
 196         /* DIDT_DB */
 197         {   ixDIDT_DB_WEIGHT0_3,                0xFFFFFFFF,                                          0,                                                    0x0E152A0F },
 198         {   ixDIDT_DB_WEIGHT4_7,                0xFFFFFFFF,                                          0,                                                    0x09061813 },
 199         {   ixDIDT_DB_WEIGHT8_11,               0xFFFFFFFF,                                          0,                                                    0x00000013 },
 200
 201         {   0xFFFFFFFF  }  /* End of list */
 202 };
 203
 204 static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] =
 205 {
 206 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 207  *      Offset                             Mask                                                 Shift                                                  Value
 208  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 209  */
 210         /* DIDT_SQ */
 211         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK,   DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
 212         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__PHASE_OFFSET_MASK,   DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
 213         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK,   DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT,  0x0000 },
 214         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
 215         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT,  0x0001 },
 216         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK,   DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT,  0x0001 },
 217         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT,  0x0001 },
 218         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,   DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT,  0xffff },
 219         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK,   DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT,  0x0000 },
 220         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT,  0x0000 },
 221         {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT,  0x0000 },
 222         /* DIDT_TD */
 223         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK,   DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
 224         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__PHASE_OFFSET_MASK,   DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
 225         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK,   DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT,  0x0000 },
 226         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
 227         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK,   DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT,  0x0001 },
 228         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK,   DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT,  0x0001 },
 229         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,   DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT,  0x0001 },
 230         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,   DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT,  0xffff },
 231         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK,   DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT,  0x0000 },
 232         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK,   DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT,  0x0000 },
 233         {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,   DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT,  0x0000 },
 234         /* DIDT_TCP */
 235         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK,  DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
 236         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__PHASE_OFFSET_MASK,  DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
 237         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK,  DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
 238         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,  DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
 239         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
 240         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK,  DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
 241         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
 242         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,  DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
 243         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK,  DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
 244         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
 245         {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
 246         /* DIDT_DB */
 247         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK,   DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
 248         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__PHASE_OFFSET_MASK,   DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
 249         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK,   DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT,  0x0000 },
 250         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
 251         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK,   DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT,  0x0001 },
 252         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK,   DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT,  0x0001 },
 253         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,   DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT,  0x0001 },
 254         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,   DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT,  0xffff },
 255         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK,   DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT,  0x0000 },
 256         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK,   DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT,  0x0000 },
 257         {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,   DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT,  0x0000 },
 258
 259         {   0xFFFFFFFF  }  /* End of list */
 260 };
 261
 262
 263 static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] =
 264 {
 265 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 266  *      Offset                   Mask                                                     Shift                                                      Value
 267  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 268  */
 269         /* DIDT_SQ */
 270         {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,     0x0004 },
 271         {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,     0x0004 },
 272         {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,     0x000a },
 273         {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,     0x000a },
 274
 275         /* DIDT_TD */
 276         {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,     0x0001 },
 277         {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,     0x0001 },
 278         {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,     0x000a },
 279         {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,     0x000a },
 280
 281         /* DIDT_TCP */
 282         {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,    0x0001 },
 283         {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,    0x0001 },
 284         {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,    0x000a },
 285         {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,    0x000a },
 286
 287         /* DIDT_DB */
 288         {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,     0x0004 },
 289         {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,     0x0004 },
 290         {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,     0x000a },
 291         {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,     0x000a },
 292
 293         {   0xFFFFFFFF  }  /* End of list */
 294 };
 295
 296 static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] =
 297 {
 298 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 299  *      Offset                        Mask                                                      Shift                                                    Value
 300  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 301  */
 302         /* DIDT_SQ_STALL_PATTERN_1_2 */
 303         {   ixDIDT_SQ_STALL_PATTERN_1_2,  DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,    DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT,  0x0001 },
 304         {   ixDIDT_SQ_STALL_PATTERN_1_2,  DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,    DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT,  0x0001 },
 305
 306         /* DIDT_SQ_STALL_PATTERN_3_4 */
 307         {   ixDIDT_SQ_STALL_PATTERN_3_4,  DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,    DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT,  0x0001 },
 308         {   ixDIDT_SQ_STALL_PATTERN_3_4,  DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,    DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT,  0x0001 },
 309
 310         /* DIDT_SQ_STALL_PATTERN_5_6 */
 311         {   ixDIDT_SQ_STALL_PATTERN_5_6,  DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,    DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT,  0x0000 },
 312         {   ixDIDT_SQ_STALL_PATTERN_5_6,  DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,    DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT,  0x0000 },
 313
 314         /* DIDT_SQ_STALL_PATTERN_7 */
 315         {   ixDIDT_SQ_STALL_PATTERN_7,    DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,      DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,    0x0000 },
 316
 317         /* DIDT_TCP_STALL_PATTERN_1_2 */
 318         {   ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,   DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
 319         {   ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,   DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
 320
 321         /* DIDT_TCP_STALL_PATTERN_3_4 */
 322         {   ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,   DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
 323         {   ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,   DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
 324
 325         /* DIDT_TCP_STALL_PATTERN_5_6 */
 326         {   ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,   DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
 327         {   ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,   DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
 328
 329         /* DIDT_TCP_STALL_PATTERN_7 */
 330         {   ixDIDT_TCP_STALL_PATTERN_7,   DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,     DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,   0x0000 },
 331
 332         /* DIDT_TD_STALL_PATTERN_1_2 */
 333         {   ixDIDT_TD_STALL_PATTERN_1_2,  DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,    DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT,  0x0001 },
 334         {   ixDIDT_TD_STALL_PATTERN_1_2,  DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,    DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT,  0x0001 },
 335
 336         /* DIDT_TD_STALL_PATTERN_3_4 */
 337         {   ixDIDT_TD_STALL_PATTERN_3_4,  DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,    DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT,  0x0001 },
 338         {   ixDIDT_TD_STALL_PATTERN_3_4,  DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,    DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT,  0x0001 },
 339
 340         /* DIDT_TD_STALL_PATTERN_5_6 */
 341         {   ixDIDT_TD_STALL_PATTERN_5_6,  DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,    DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT,  0x0000 },
 342         {   ixDIDT_TD_STALL_PATTERN_5_6,  DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,    DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT,  0x0000 },
 343
 344         /* DIDT_TD_STALL_PATTERN_7 */
 345         {   ixDIDT_TD_STALL_PATTERN_7,    DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,      DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,    0x0000 },
 346
 347         /* DIDT_DB_STALL_PATTERN_1_2 */
 348         {   ixDIDT_DB_STALL_PATTERN_1_2,  DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,    DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT,  0x0001 },
 349         {   ixDIDT_DB_STALL_PATTERN_1_2,  DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,    DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT,  0x0001 },
 350
 351         /* DIDT_DB_STALL_PATTERN_3_4 */
 352         {   ixDIDT_DB_STALL_PATTERN_3_4,  DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,    DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT,  0x0001 },
 353         {   ixDIDT_DB_STALL_PATTERN_3_4,  DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,    DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT,  0x0001 },
 354
 355         /* DIDT_DB_STALL_PATTERN_5_6 */
 356         {   ixDIDT_DB_STALL_PATTERN_5_6,  DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,    DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT,  0x0000 },
 357         {   ixDIDT_DB_STALL_PATTERN_5_6,  DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,    DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT,  0x0000 },
 358
 359         /* DIDT_DB_STALL_PATTERN_7 */
 360         {   ixDIDT_DB_STALL_PATTERN_7,    DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,      DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,    0x0000 },
 361
 362         {   0xFFFFFFFF  }  /* End of list */
 363 };
 364
 365 static const struct vega10_didt_config_reg SELCacConfig_Vega10[] =
 366 {
 367 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 368  *      Offset                             Mask                                                 Shift                                                  Value
 369  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 370  */
 371         /* SQ */
 372         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00060021 },
 373         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00860021 },
 374         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01060021 },
 375         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01860021 },
 376         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x02060021 },
 377         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x02860021 },
 378         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x03060021 },
 379         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x03860021 },
 380         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x04060021 },
 381         /* TD */
 382         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x000E0020 },
 383         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x008E0020 },
 384         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x010E0020 },
 385         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x018E0020 },
 386         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x020E0020 },
 387         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x028E0020 },
 388         /* TCP */
 389         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x001c0020 },
 390         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x009c0020 },
 391         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x011c0020 },
 392         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x019c0020 },
 393         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x021c0020 },
 394         /* DB */
 395         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00200008 },
 396         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00820008 },
 397         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01020008 },
 398         {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01820008 },
 399
 400         {   0xFFFFFFFF  }  /* End of list */
 401 };
 402
 403
 404 static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] =
 405 {
 406 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 407  *      Offset                             Mask                                                 Shift                                                  Value
 408  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 409  */
 410         /* SQ */
 411         {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00030001 },
 412         {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x000F0007 },
 413         {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x003F001F },
 414         {   ixDIDT_SQ_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x0000007F },
 415         /* TD */
 416         {   ixDIDT_TD_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 417         {   ixDIDT_TD_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 418         {   ixDIDT_TD_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 419         {   ixDIDT_TD_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
 420         /* TCP */
 421         {   ixDIDT_TCP_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                         0,                                                     0x00000000 },
 422         {   ixDIDT_TCP_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                         0,                                                     0x00000000 },
 423         {   ixDIDT_TCP_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                         0,                                                     0x00000000 },
 424         {   ixDIDT_TCP_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                         0,                                                     0x00000000 },
 425         /* DB */
 426         {   ixDIDT_DB_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 427         {   ixDIDT_DB_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 428         {   ixDIDT_DB_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 429         {   ixDIDT_DB_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
 430
 431         {   0xFFFFFFFF  }  /* End of list */
 432 };
 433
 434 static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] =
 435 {
 436 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 437  *      Offset                             Mask                                                 Shift                                                  Value
 438  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 439  */
 440         /* SQ */
 441         {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000015 },
 442         {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 443         {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 444         {   ixDIDT_SQ_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
 445         /* TD */
 446         {   ixDIDT_TD_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000015 },
 447         {   ixDIDT_TD_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 448         {   ixDIDT_TD_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
 449         {   ixDIDT_TD_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
 450
 451         {   0xFFFFFFFF  }  /* End of list */
 452 };
 453
 454 static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] =
 455 {
 456 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 457  *      Offset                             Mask                                                 Shift                                                  Value
 458  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 459  */
 460         /* SQ */
 461         {   ixDIDT_SQ_EDC_STALL_DELAY_1,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
 462         {   ixDIDT_SQ_EDC_STALL_DELAY_2,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
 463         {   ixDIDT_SQ_EDC_STALL_DELAY_3,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
 464         {   ixDIDT_SQ_EDC_STALL_DELAY_4,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
 465         /* TD */
 466         {   ixDIDT_TD_EDC_STALL_DELAY_1,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
 467         {   ixDIDT_TD_EDC_STALL_DELAY_2,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
 468         {   ixDIDT_TD_EDC_STALL_DELAY_3,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
 469         {   ixDIDT_TD_EDC_STALL_DELAY_4,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
 470         /* TCP */
 471         {   ixDIDT_TCP_EDC_STALL_DELAY_1,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
 472         {   ixDIDT_TCP_EDC_STALL_DELAY_2,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
 473         {   ixDIDT_TCP_EDC_STALL_DELAY_3,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
 474         {   ixDIDT_TCP_EDC_STALL_DELAY_4,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
 475         /* DB */
 476         {   ixDIDT_DB_EDC_STALL_DELAY_1,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
 477
 478         {   0xFFFFFFFF  }  /* End of list */
 479 };
 480
 481 static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] =
 482 {
 483 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 484  *      Offset                             Mask                                                 Shift                                                  Value
 485  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 486  */
 487         {   ixDIDT_SQ_EDC_THRESHOLD,           0xFFFFFFFF,                                          0,                                                     0x0000010E },
 488         {   ixDIDT_TD_EDC_THRESHOLD,           0xFFFFFFFF,                                          0,                                                     0xFFFFFFFF },
 489         {   ixDIDT_TCP_EDC_THRESHOLD,          0xFFFFFFFF,                                          0,                                                     0xFFFFFFFF },
 490         {   ixDIDT_DB_EDC_THRESHOLD,           0xFFFFFFFF,                                          0,                                                     0xFFFFFFFF },
 491
 492         {   0xFFFFFFFF  }  /* End of list */
 493 };
 494
 495 static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] =
 496 {
 497 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 498  *      Offset                             Mask                                                 Shift                                                  Value
 499  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 500  */
 501         /* SQ */
 502         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
 503         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0001 },
 504         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
 505         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
 506         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0000 },
 507         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x0000 },
 508         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
 509         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
 510         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
 511         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
 512         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
 513
 514         {   0xFFFFFFFF  }  /* End of list */
 515 };
 516
 517 static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] =
 518 {
 519 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 520  *      Offset                             Mask                                                 Shift                                                  Value
 521  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 522  */
 523         /* SQ */
 524         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0001 },
 525         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
 526         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
 527         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
 528         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0004 },
 529         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x0006 },
 530         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
 531         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
 532         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
 533         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
 534         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
 535
 536         {   0xFFFFFFFF  }  /* End of list */
 537 };
 538
 539 static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] =
 540 {
 541 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 542  *      Offset                             Mask                                                 Shift                                                  Value
 543  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 544  */
 545         /* SQ */
 546         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
 547         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
 548         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
 549         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0001 },
 550         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0001 },
 551         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x000C },
 552         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
 553         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
 554         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
 555         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
 556         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
 557
 558         /* TD */
 559         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_EN_MASK,                       DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
 560         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
 561         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
 562         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0001 },
 563         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0001 },
 564         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x000E },
 565         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
 566         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
 567         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
 568         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
 569         {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
 570
 571         {   0xFFFFFFFF  }  /* End of list */
 572 };
 573
 574 static const struct vega10_didt_config_reg    GCDiDtDroopCtrlConfig_vega10[] =
 575 {
 576 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 577  *      Offset                             Mask                                                 Shift                                                  Value
 578  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 579  */
 580         {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT,  0x0000 },
 581         {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT,  0x0000 },
 582         {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT,  0x0000 },
 583         {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK,   GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT,  0x0000 },
 584         {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT,  0x0000 },
 585
 586         {   0xFFFFFFFF  }  /* End of list */
 587 };
 588
 589 static const struct vega10_didt_config_reg    GCDiDtCtrl0Config_vega10[] =
 590 {
 591 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 592  *      Offset                             Mask                                                 Shift                                                  Value
 593  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 594  */
 595         {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK,   GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
 596         {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__PHASE_OFFSET_MASK,   GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
 597         {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_SW_RST_MASK,   GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT,  0x0000 },
 598         {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
 599         {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,   GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,  0x0000 },
 600         {   0xFFFFFFFF  }  /* End of list */
 601 };
 602
 603
 604 static const struct vega10_didt_config_reg   PSMSEEDCStallPatternConfig_Vega10[] =
 605 {
 606 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 607  *      Offset                             Mask                                                 Shift                                                  Value
 608  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 609  */
 610         /* SQ EDC STALL PATTERNs */
 611         {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,  DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK,   DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT,   0x0101 },
 612         {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,  DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK,   DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT,   0x0101 },
 613         {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,  DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK,   DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT,   0x1111 },
 614         {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,  DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK,   DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT,   0x1111 },
 615
 616         {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,  DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK,   DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT,   0x1515 },
 617         {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,  DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK,   DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT,   0x1515 },
 618
 619         {   ixDIDT_SQ_EDC_STALL_PATTERN_7,  DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK,   DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT,     0x5555 },
 620
 621         {   0xFFFFFFFF  }  /* End of list */
 622 };
 623
 624 static const struct vega10_didt_config_reg   PSMSEEDCStallDelayConfig_Vega10[] =
 625 {
 626 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 627  *      Offset                             Mask                                                 Shift                                                  Value
 628  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 629  */
 630         /* SQ EDC STALL DELAYs */
 631         {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT,  0x0000 },
 632         {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT,  0x0000 },
 633         {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT,  0x0000 },
 634         {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT,  0x0000 },
 635
 636         {   ixDIDT_SQ_EDC_STALL_DELAY_2,      DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK,  DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT,  0x0000 },
 637         {   ixDIDT_SQ_EDC_STALL_DELAY_2,      DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK,  DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT,  0x0000 },
 638         {   ixDIDT_SQ_EDC_STALL_DELAY_2,      DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK,  DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT,  0x0000 },
 639         {   ixDIDT_SQ_EDC_STALL_DELAY_2,      DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK,  DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT,  0x0000 },
 640
 641         {   ixDIDT_SQ_EDC_STALL_DELAY_3,      DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK,  DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT,  0x0000 },
 642         {   ixDIDT_SQ_EDC_STALL_DELAY_3,      DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK,  DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT,  0x0000 },
 643         {   ixDIDT_SQ_EDC_STALL_DELAY_3,      DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 },
 644         {   ixDIDT_SQ_EDC_STALL_DELAY_3,      DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 },
 645
 646         {   ixDIDT_SQ_EDC_STALL_DELAY_4,      DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 },
 647         {   ixDIDT_SQ_EDC_STALL_DELAY_4,      DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 },
 648         {   ixDIDT_SQ_EDC_STALL_DELAY_4,      DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 },
 649         {   ixDIDT_SQ_EDC_STALL_DELAY_4,      DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 },
 650
 651         {   0xFFFFFFFF  }  /* End of list */
 652 };
 653
 654 static const struct vega10_didt_config_reg   PSMSEEDCThresholdConfig_Vega10[] =
 655 {
 656 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 657  *      Offset                             Mask                                                 Shift                                                  Value
 658  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 659  */
 660         /* SQ EDC THRESHOLD */
 661         {   ixDIDT_SQ_EDC_THRESHOLD,           DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK,           DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT,            0x0000 },
 662
 663         {   0xFFFFFFFF  }  /* End of list */
 664 };
 665
 666 static const struct vega10_didt_config_reg   PSMSEEDCCtrlResetConfig_Vega10[] =
 667 {
 668 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 669  *      Offset                             Mask                                                 Shift                                                  Value
 670  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 671  */
 672         /* SQ EDC CTRL */
 673         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
 674         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0001 },
 675         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
 676         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
 677         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0000 },
 678         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x0000 },
 679         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
 680         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
 681         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
 682         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
 683         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
 684
 685         {   0xFFFFFFFF  }  /* End of list */
 686 };
 687
 688 static const struct vega10_didt_config_reg   PSMSEEDCCtrlConfig_Vega10[] =
 689 {
 690 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 691  *      Offset                             Mask                                                 Shift                                                  Value
 692  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 693  */
 694         /* SQ EDC CTRL */
 695         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0001 },
 696         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
 697         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
 698         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
 699         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0000 },
 700         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x000E },
 701         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
 702         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0001 },
 703         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0003 },
 704         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
 705         {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
 706
 707         {   0xFFFFFFFF  }  /* End of list */
 708 };
 709
 710 static const struct vega10_didt_config_reg   PSMGCEDCThresholdConfig_vega10[] =
 711 {
 712 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 713  *      Offset                             Mask                                                 Shift                                                  Value
 714  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 715  */
 716         {   mmGC_EDC_THRESHOLD,                GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK,                GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT,                 0x0000000 },
 717
 718         {   0xFFFFFFFF  }  /* End of list */
 719 };
 720
 721 static const struct vega10_didt_config_reg   PSMGCEDCDroopCtrlConfig_vega10[] =
 722 {
 723 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 724  *      Offset                             Mask                                                 Shift                                                  Value
 725  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 726  */
 727         {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK,          GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT,           0x0001 },
 728         {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK,         GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT,          0x0384 },
 729         {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK,       GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT,        0x0001 },
 730         {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK,                 GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT,                  0x0001 },
 731         {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK,               GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT,                0x0001 },
 732
 733         {   0xFFFFFFFF  }  /* End of list */
 734 };
 735
 736 static const struct vega10_didt_config_reg   PSMGCEDCCtrlResetConfig_vega10[] =
 737 {
 738 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 739  *      Offset                             Mask                                                 Shift                                                  Value
 740  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 741  */
 742         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_EN_MASK,                            GC_EDC_CTRL__EDC_EN__SHIFT,                             0x0000 },
 743         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_SW_RST_MASK,                        GC_EDC_CTRL__EDC_SW_RST__SHIFT,                         0x0001 },
 744         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,               GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,                0x0000 },
 745         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_FORCE_STALL_MASK,                   GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT,                    0x0000 },
 746         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,       GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,        0x0000 },
 747         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,          GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,           0x0000 },
 748
 749         {   0xFFFFFFFF  }  /* End of list */
 750 };
 751
 752 static const struct vega10_didt_config_reg   PSMGCEDCCtrlConfig_vega10[] =
 753 {
 754 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 755  *      Offset                             Mask                                                 Shift                                                  Value
 756  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 757  */
 758         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_EN_MASK,                            GC_EDC_CTRL__EDC_EN__SHIFT,                             0x0001 },
 759         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_SW_RST_MASK,                        GC_EDC_CTRL__EDC_SW_RST__SHIFT,                         0x0000 },
 760         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,               GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,                0x0000 },
 761         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_FORCE_STALL_MASK,                   GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT,                    0x0000 },
 762         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,       GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,        0x0000 },
 763         {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,          GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,           0x0000 },
 764
 765         {   0xFFFFFFFF  }  /* End of list */
 766 };
 767
 768 static const struct vega10_didt_config_reg    AvfsPSMResetConfig_vega10[]=
 769 {
 770 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 771  *      Offset                             Mask                                                 Shift                                                  Value
 772  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 773  */
 774         {   0x16A02,                         0xFFFFFFFF,                                            0x0,                                                    0x0000005F },
 775         {   0x16A05,                         0xFFFFFFFF,                                            0x0,                                                    0x00000001 },
 776         {   0x16A06,                         0x00000001,                                            0x0,                                                    0x02000000 },
 777         {   0x16A01,                         0xFFFFFFFF,                                            0x0,                                                    0x00003027 },
 778
 779         {   0xFFFFFFFF  }  /* End of list */
 780 };
 781
 782 static const struct vega10_didt_config_reg    AvfsPSMInitConfig_vega10[] =
 783 {
 784 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 785  *      Offset                             Mask                                                 Shift                                                  Value
 786  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 787  */
 788         {   0x16A05,                         0xFFFFFFFF,                                            0x18,                                                    0x00000001 },
 789         {   0x16A05,                         0xFFFFFFFF,                                            0x8,                                                     0x00000003 },
 790         {   0x16A05,                         0xFFFFFFFF,                                            0xa,                                                     0x00000006 },
 791         {   0x16A05,                         0xFFFFFFFF,                                            0x7,                                                     0x00000000 },
 792         {   0x16A06,                         0xFFFFFFFF,                                            0x18,                                                    0x00000001 },
 793         {   0x16A06,                         0xFFFFFFFF,                                            0x19,                                                    0x00000001 },
 794         {   0x16A01,                         0xFFFFFFFF,                                            0x0,                                                     0x00003027 },
 795
 796         {   0xFFFFFFFF  }  /* End of list */
 797 };
 798
 799 static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type)
 800 {
 801         uint32_t data;
 802
 803         PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);
 804
 805         while (config_regs->offset != 0xFFFFFFFF) {
 806                 switch (reg_type) {
 807                 case VEGA10_CONFIGREG_DIDT:
 808                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
 809                         data &= ~config_regs->mask;
 810                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 811                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
 812                         break;
 813                 case VEGA10_CONFIGREG_GCCAC:
 814                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
 815                         data &= ~config_regs->mask;
 816                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 817                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
 818                         break;
 819                 case VEGA10_CONFIGREG_SECAC:
 820                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset);
 821                         data &= ~config_regs->mask;
 822                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 823                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data);
 824                         break;
 825                 default:
 826                         return -EINVAL;
 827                 }
 828
 829                 config_regs++;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs)
 836 {
 837         uint32_t data;
 838
 839         while (config_regs->offset != 0xFFFFFFFF) {
 840                 data = cgs_read_register(hwmgr->device, config_regs->offset);
 841                 data &= ~config_regs->mask;
 842                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 843                 cgs_write_register(hwmgr->device, config_regs->offset, data);
 844                 config_regs++;
 845         }
 846
 847         return 0;
 848 }
 849
 850 static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
 851 {
 852         uint32_t data;
 853         uint32_t en = (enable ? 1 : 0);
 854         uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
 855
 856         if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
 857                 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
 858                                      DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
 859                 didt_block_info &= ~SQ_Enable_MASK;
 860                 didt_block_info |= en << SQ_Enable_SHIFT;
 861         }
 862
 863         if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
 864                 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
 865                                      DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
 866                 didt_block_info &= ~DB_Enable_MASK;
 867                 didt_block_info |= en << DB_Enable_SHIFT;
 868         }
 869
 870         if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
 871                 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
 872                                      DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
 873                 didt_block_info &= ~TD_Enable_MASK;
 874                 didt_block_info |= en << TD_Enable_SHIFT;
 875         }
 876
 877         if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
 878                 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
 879                                      DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
 880                 didt_block_info &= ~TCP_Enable_MASK;
 881                 didt_block_info |= en << TCP_Enable_SHIFT;
 882         }
 883
 884         if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
 885                 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
 886                                      DIDT_DBR_CTRL0, DIDT_CTRL_EN, en);
 887         }
 888
 889         if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
 890                 if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
 891                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
 892                         data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
 893                         data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
 894                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
 895                 }
 896
 897                 if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
 898                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
 899                         data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
 900                         data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
 901                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
 902                 }
 903
 904                 if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
 905                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
 906                         data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
 907                         data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
 908                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
 909                 }
 910
 911                 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
 912                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
 913                         data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
 914                         data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
 915                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
 916                 }
 917
 918                 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
 919                         data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
 920                         data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
 921                         data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
 922                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
 923                 }
 924         }
 925
 926         /* For Vega10, SMC does not support any mask yet. */
 927         if (enable)
 928                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
 929
 930 }
 931
 932 static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
 933 {
 934         struct amdgpu_device *adev = hwmgr->adev;
 935         int result;
 936         uint32_t num_se = 0, count, data;
 937
 938         num_se = adev->gfx.config.max_shader_engines;
 939
 940         amdgpu_gfx_rlc_enter_safe_mode(adev);
 941
 942         mutex_lock(&adev->grbm_idx_mutex);
 943         for (count = 0; count < num_se; count++) {
 944                 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
 945                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
 946
 947                 result =  vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
 948                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
 949                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
 950                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT);
 951                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT);
 952                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
 953                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
 954                 result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC);
 955                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
 956
 957                 if (0 != result)
 958                         break;
 959         }
 960         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
 961         mutex_unlock(&adev->grbm_idx_mutex);
 962
 963         vega10_didt_set_mask(hwmgr, true);
 964
 965         amdgpu_gfx_rlc_exit_safe_mode(adev);
 966
 967         return 0;
 968 }
 969
 970 static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
 971 {
 972         struct amdgpu_device *adev = hwmgr->adev;
 973
 974         amdgpu_gfx_rlc_enter_safe_mode(adev);
 975
 976         vega10_didt_set_mask(hwmgr, false);
 977
 978         amdgpu_gfx_rlc_exit_safe_mode(adev);
 979
 980         return 0;
 981 }
 982
 983 static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
 984 {
 985         struct amdgpu_device *adev = hwmgr->adev;
 986         int result;
 987         uint32_t num_se = 0, count, data;
 988
 989         num_se = adev->gfx.config.max_shader_engines;
 990
 991         amdgpu_gfx_rlc_enter_safe_mode(adev);
 992
 993         mutex_lock(&adev->grbm_idx_mutex);
 994         for (count = 0; count < num_se; count++) {
 995                 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
 996                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
 997
 998                 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
 999                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
1000                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
1001                 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
1002                 if (0 != result)
1003                         break;
1004         }
1005         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1006         mutex_unlock(&adev->grbm_idx_mutex);
1007
1008         vega10_didt_set_mask(hwmgr, true);
1009
1010         amdgpu_gfx_rlc_exit_safe_mode(adev);
1011
1012         vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
1013         if (PP_CAP(PHM_PlatformCaps_GCEDC))
1014                 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
1015
1016         if (PP_CAP(PHM_PlatformCaps_PSM))
1017                 vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega10);
1018
1019         return 0;
1020 }
1021
1022 static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
1023 {
1024         struct amdgpu_device *adev = hwmgr->adev;
1025         uint32_t data;
1026
1027         amdgpu_gfx_rlc_enter_safe_mode(adev);
1028
1029         vega10_didt_set_mask(hwmgr, false);
1030
1031         amdgpu_gfx_rlc_exit_safe_mode(adev);
1032
1033         if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1034                 data = 0x00000000;
1035                 cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
1036         }
1037
1038         if (PP_CAP(PHM_PlatformCaps_PSM))
1039                 vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega10);
1040
1041         return 0;
1042 }
1043
1044 static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
1045 {
1046         struct amdgpu_device *adev = hwmgr->adev;
1047         int result;
1048         uint32_t num_se = 0, count, data;
1049
1050         num_se = adev->gfx.config.max_shader_engines;
1051
1052         amdgpu_gfx_rlc_enter_safe_mode(adev);
1053
1054         mutex_lock(&adev->grbm_idx_mutex);
1055         for (count = 0; count < num_se; count++) {
1056                 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1057                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1058                 result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1059                 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1060                 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1061                 result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1062                 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1063                 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1064
1065                 if (0 != result)
1066                         break;
1067         }
1068         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1069         mutex_unlock(&adev->grbm_idx_mutex);
1070
1071         vega10_didt_set_mask(hwmgr, true);
1072
1073         amdgpu_gfx_rlc_exit_safe_mode(adev);
1074
1075         return 0;
1076 }
1077
1078 static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr)
1079 {
1080         struct amdgpu_device *adev = hwmgr->adev;
1081
1082         amdgpu_gfx_rlc_enter_safe_mode(adev);
1083
1084         vega10_didt_set_mask(hwmgr, false);
1085
1086         amdgpu_gfx_rlc_exit_safe_mode(adev);
1087
1088         return 0;
1089 }
1090
1091 static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1092 {
1093         struct amdgpu_device *adev = hwmgr->adev;
1094         int result = 0;
1095         uint32_t num_se = 0;
1096         uint32_t count, data;
1097
1098         num_se = adev->gfx.config.max_shader_engines;
1099
1100         amdgpu_gfx_rlc_enter_safe_mode(adev);
1101
1102         vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1103
1104         mutex_lock(&adev->grbm_idx_mutex);
1105         for (count = 0; count < num_se; count++) {
1106                 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1107                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1108                 result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1109                 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1110                 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1111                 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1112
1113                 if (0 != result)
1114                         break;
1115         }
1116         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1117         mutex_unlock(&adev->grbm_idx_mutex);
1118
1119         vega10_didt_set_mask(hwmgr, true);
1120
1121         amdgpu_gfx_rlc_exit_safe_mode(adev);
1122
1123         vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
1124
1125         if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1126                 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
1127                 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
1128         }
1129
1130         if (PP_CAP(PHM_PlatformCaps_PSM))
1131                 vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega10);
1132
1133         return 0;
1134 }
1135
1136 static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1137 {
1138         struct amdgpu_device *adev = hwmgr->adev;
1139         uint32_t data;
1140
1141         amdgpu_gfx_rlc_enter_safe_mode(adev);
1142
1143         vega10_didt_set_mask(hwmgr, false);
1144
1145         amdgpu_gfx_rlc_exit_safe_mode(adev);
1146
1147         if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1148                 data = 0x00000000;
1149                 cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
1150         }
1151
1152         if (PP_CAP(PHM_PlatformCaps_PSM))
1153                 vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega10);
1154
1155         return 0;
1156 }
1157
1158 static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1159 {
1160         struct amdgpu_device *adev = hwmgr->adev;
1161         int result;
1162
1163         amdgpu_gfx_rlc_enter_safe_mode(adev);
1164
1165         mutex_lock(&adev->grbm_idx_mutex);
1166         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1167         mutex_unlock(&adev->grbm_idx_mutex);
1168
1169         result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1170         result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1171         if (0 != result)
1172                 return result;
1173
1174         vega10_didt_set_mask(hwmgr, false);
1175
1176         amdgpu_gfx_rlc_exit_safe_mode(adev);
1177
1178         return 0;
1179 }
1180
1181 static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1182 {
1183         int result;
1184
1185         result = vega10_disable_se_edc_config(hwmgr);
1186         PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);
1187
1188         return 0;
1189 }
1190
1191 int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
1192 {
1193         int result = 0;
1194         struct vega10_hwmgr *data = hwmgr->backend;
1195
1196         if (data->smu_features[GNLD_DIDT].supported) {
1197                 if (data->smu_features[GNLD_DIDT].enabled)
1198                         PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n");
1199
1200                 switch (data->registry_data.didt_mode) {
1201                 case 0:
1202                         result = vega10_enable_cac_driving_se_didt_config(hwmgr);
1203                         PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);
1204                         break;
1205                 case 2:
1206                         result = vega10_enable_psm_gc_didt_config(hwmgr);
1207                         PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);
1208                         break;
1209                 case 3:
1210                         result = vega10_enable_se_edc_config(hwmgr);
1211                         PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);
1212                         break;
1213                 case 1:
1214                 case 4:
1215                 case 5:
1216                         result = vega10_enable_psm_gc_edc_config(hwmgr);
1217                         PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);
1218                         break;
1219                 case 6:
1220                         result = vega10_enable_se_edc_force_stall_config(hwmgr);
1221                         PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);
1222                         break;
1223                 default:
1224                         result = -EINVAL;
1225                         break;
1226                 }
1227
1228                 if (0 == result) {
1229                         result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1230                         PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
1231                         data->smu_features[GNLD_DIDT].enabled = true;
1232                 }
1233         }
1234
1235         return result;
1236 }
1237
1238 int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
1239 {
1240         int result = 0;
1241         struct vega10_hwmgr *data = hwmgr->backend;
1242
1243         if (data->smu_features[GNLD_DIDT].supported) {
1244                 if (!data->smu_features[GNLD_DIDT].enabled)
1245                         PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n");
1246
1247                 switch (data->registry_data.didt_mode) {
1248                 case 0:
1249                         result = vega10_disable_cac_driving_se_didt_config(hwmgr);
1250                         PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);
1251                         break;
1252                 case 2:
1253                         result = vega10_disable_psm_gc_didt_config(hwmgr);
1254                         PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result);
1255                         break;
1256                 case 3:
1257                         result = vega10_disable_se_edc_config(hwmgr);
1258                         PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result);
1259                         break;
1260                 case 1:
1261                 case 4:
1262                 case 5:
1263                         result = vega10_disable_psm_gc_edc_config(hwmgr);
1264                         PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result);
1265                         break;
1266                 case 6:
1267                         result = vega10_disable_se_edc_force_stall_config(hwmgr);
1268                         PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result);
1269                         break;
1270                 default:
1271                         result = -EINVAL;
1272                         break;
1273                 }
1274
1275                 if (0 == result) {
1276                         result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1277                         PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
1278                         data->smu_features[GNLD_DIDT].enabled = false;
1279                 }
1280         }
1281
1282         return result;
1283 }
1284
1285 void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1286 {
1287         struct vega10_hwmgr *data = hwmgr->backend;
1288         struct phm_ppt_v2_information *table_info =
1289                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1290         struct phm_tdp_table *tdp_table = table_info->tdp_table;
1291         PPTable_t *table = &(data->smc_state_table.pp_table);
1292
1293         table->SocketPowerLimit = cpu_to_le16(
1294                         tdp_table->usMaximumPowerDeliveryLimit);
1295         table->TdcLimit = cpu_to_le16(tdp_table->usTDC);
1296         table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit);
1297         table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge);
1298         table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot);
1299         table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM);
1300         table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc);
1301         table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd);
1302         table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1);
1303         table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2);
1304         table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx);
1305         table->LoadLineResistance =
1306                         hwmgr->platform_descriptor.LoadLineSlope * 256;
1307         table->FitLimit = 0; /* Not used for Vega10 */
1308
1309         table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address;
1310         table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address;
1311         table->Vr_I2C_address = tdp_table->ucVr_I2C_address;
1312         table->Plx_I2C_address = tdp_table->ucPlx_I2C_address;
1313
1314         table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line;
1315         table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA;
1316
1317         table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line;
1318         table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA;
1319
1320         table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line;
1321         table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA;
1322 }
1323
1324 int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1325 {
1326         struct vega10_hwmgr *data = hwmgr->backend;
1327
1328         if (data->registry_data.enable_pkg_pwr_tracking_feature)
1329                 smum_send_msg_to_smc_with_parameter(hwmgr,
1330                                 PPSMC_MSG_SetPptLimit, n);
1331
1332         return 0;
1333 }
1334
1335 int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
1336 {
1337         struct vega10_hwmgr *data = hwmgr->backend;
1338         struct phm_ppt_v2_information *table_info =
1339                         (struct phm_ppt_v2_information *)(hwmgr->pptable);
1340         struct phm_tdp_table *tdp_table = table_info->tdp_table;
1341         int result = 0;
1342
1343         hwmgr->default_power_limit = hwmgr->power_limit =
1344                         (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
1345
1346         if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1347                 if (data->smu_features[GNLD_PPT].supported)
1348                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1349                                         true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1350                                         "Attempt to enable PPT feature Failed!",
1351                                         data->smu_features[GNLD_PPT].supported = false);
1352
1353                 if (data->smu_features[GNLD_TDC].supported)
1354                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1355                                         true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1356                                         "Attempt to enable PPT feature Failed!",
1357                                         data->smu_features[GNLD_TDC].supported = false);
1358
1359                 result = vega10_set_power_limit(hwmgr, hwmgr->power_limit);
1360                 PP_ASSERT_WITH_CODE(!result,
1361                                 "Failed to set Default Power Limit in SMC!",
1362                                 return result);
1363         }
1364
1365         return result;
1366 }
1367
1368 int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
1369 {
1370         struct vega10_hwmgr *data = hwmgr->backend;
1371
1372         if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1373                 if (data->smu_features[GNLD_PPT].supported)
1374                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1375                                         false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1376                                         "Attempt to disable PPT feature Failed!",
1377                                         data->smu_features[GNLD_PPT].supported = false);
1378
1379                 if (data->smu_features[GNLD_TDC].supported)
1380                         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1381                                         false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1382                                         "Attempt to disable PPT feature Failed!",
1383                                         data->smu_features[GNLD_TDC].supported = false);
1384         }
1385
1386         return 0;
1387 }
1388
1389 static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
1390                 uint32_t adjust_percent)
1391 {
1392         smum_send_msg_to_smc_with_parameter(hwmgr,
1393                         PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
1394 }
1395
1396 int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
1397 {
1398         int adjust_percent;
1399
1400         if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1401                 adjust_percent =
1402                                 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
1403                                 hwmgr->platform_descriptor.TDPAdjustment :
1404                                 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
1405                 vega10_set_overdrive_target_percentage(hwmgr,
1406                                 (uint32_t)adjust_percent);
1407         }
1408         return 0;
1409 }