2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 #ifndef _smuio_11_0_0_SH_MASK_HEADER
22 #define _smuio_11_0_0_SH_MASK_HEADER
25 // addressBlock: smuio_smuio_SmuSmuioDec
27 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0
28 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10
29 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL
30 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L
32 #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0
33 #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2
34 #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x5
35 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x6
36 #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L
37 #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL
38 #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L
39 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x000000C0L
41 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0
42 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L
44 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2
45 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3
46 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L
47 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L
49 #define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0
50 #define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4
51 #define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L
52 #define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L
54 #define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0
55 #define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14
56 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15
57 #define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16
58 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17
59 #define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
60 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c
61 #define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L
62 #define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L
63 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L
64 #define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L
65 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L
66 #define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L
67 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L
69 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
70 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
71 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
72 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
73 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x00FFFFFFL
74 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x01000000L
75 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L
76 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L
78 #define ROM_STATUS__ROM_BUSY__SHIFT 0x0
79 #define ROM_STATUS__ROM_BUSY_MASK 0x00000001L
81 #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
82 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
83 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
84 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
85 #define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
86 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
87 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
88 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
90 #define ROM_INDEX__ROM_INDEX__SHIFT 0x0
91 #define ROM_INDEX__ROM_INDEX_MASK 0x00FFFFFFL
93 #define ROM_DATA__ROM_DATA__SHIFT 0x0
94 #define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL
96 #define ROM_START__ROM_START__SHIFT 0x0
97 #define ROM_START__ROM_START_MASK 0x00FFFFFFL
99 #define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
100 #define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
101 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
102 #define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL
103 #define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L
104 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L
106 #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
107 #define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L
109 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
110 #define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
111 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL
112 #define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L
114 #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
115 #define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL
117 #define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
118 #define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL
120 #define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
121 #define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL
123 #define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
124 #define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL
126 #define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
127 #define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL
129 #define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
130 #define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL
132 #define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
133 #define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL
135 #define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
136 #define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL
138 #define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
139 #define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL
141 #define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
142 #define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL
144 #define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
145 #define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL
147 #define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
148 #define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL
150 #define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
151 #define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL
153 #define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
154 #define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL
156 #define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
157 #define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL
159 #define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
160 #define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL
162 #define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
163 #define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL
165 #define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
166 #define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL
168 #define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
169 #define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL
171 #define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
172 #define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL
174 #define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
175 #define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL
177 #define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
178 #define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL
180 #define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
181 #define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL
183 #define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
184 #define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL
186 #define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
187 #define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL
189 #define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
190 #define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL
192 #define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
193 #define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL
195 #define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
196 #define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL
198 #define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
199 #define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL
201 #define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
202 #define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL
204 #define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
205 #define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL
207 #define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
208 #define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL
210 #define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
211 #define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL
213 #define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
214 #define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL
216 #define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
217 #define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL
219 #define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
220 #define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL
222 #define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
223 #define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL
225 #define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
226 #define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL
228 #define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
229 #define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL
231 #define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
232 #define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL
234 #define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
235 #define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL
237 #define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
238 #define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL
240 #define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
241 #define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL
243 #define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
244 #define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL
246 #define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
247 #define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL
249 #define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
250 #define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL
252 #define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
253 #define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL
255 #define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
256 #define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL
258 #define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
259 #define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL
261 #define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
262 #define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL
264 #define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
265 #define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL
267 #define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
268 #define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL
270 #define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
271 #define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL
273 #define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
274 #define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL
276 #define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
277 #define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL
279 #define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
280 #define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL
282 #define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
283 #define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL
285 #define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
286 #define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL
288 #define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
289 #define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL
291 #define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
292 #define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL
294 #define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
295 #define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL
297 #define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
298 #define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL
300 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
301 #define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL
303 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
304 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL
305 //SMU_GPIOPAD_SW_INT_STAT
306 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
307 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L
309 #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
310 #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL
312 #define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0
313 #define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL
314 //SMU_GPIOPAD_TXIMPSEL
315 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0
316 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL
318 #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0
319 #define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL
321 #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0
322 #define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL
324 #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0
325 #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL
326 //SMU_GPIOPAD_RCVR_SEL0
327 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0
328 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL
329 //SMU_GPIOPAD_RCVR_SEL1
330 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0
331 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL
333 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
334 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL
336 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
337 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL
338 //SMU_GPIOPAD_PINSTRAPS
339 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
340 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
341 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
342 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
343 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
344 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
345 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
346 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
347 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
348 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
349 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
350 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
351 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
352 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
353 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
354 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
355 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
356 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
357 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
358 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
359 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
360 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
361 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
362 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
363 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
364 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
365 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
366 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
367 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
368 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
369 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
370 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L
371 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L
372 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L
373 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L
374 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L
375 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L
376 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L
377 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L
378 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L
379 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L
380 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L
381 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L
382 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L
383 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L
384 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L
385 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L
386 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L
387 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L
388 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L
389 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L
390 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L
391 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L
392 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L
393 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L
394 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L
395 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L
396 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L
397 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L
398 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L
399 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L
400 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L
402 #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0
403 #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000000FFL
404 //SMU_GPIOPAD_INT_STAT_EN
405 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
406 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
407 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL
408 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L
409 //SMU_GPIOPAD_INT_STAT
410 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
411 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
412 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL
413 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L
414 //SMU_GPIOPAD_INT_STAT_AK
415 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
416 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
417 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
418 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
419 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
420 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
421 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
422 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
423 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
424 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
425 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
426 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
427 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
428 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
429 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
430 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
431 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
432 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
433 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
434 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
435 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
436 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
437 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
438 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
439 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
440 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
441 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
442 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
443 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
444 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
445 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L
446 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L
447 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L
448 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L
449 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L
450 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L
451 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L
452 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L
453 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L
454 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L
455 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L
456 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L
457 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L
458 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L
459 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L
460 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L
461 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L
462 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L
463 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L
464 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L
465 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L
466 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L
467 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L
468 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L
469 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L
470 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L
471 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L
472 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L
473 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L
474 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L
476 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
477 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
478 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL
479 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L
480 //SMU_GPIOPAD_INT_TYPE
481 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
482 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
483 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL
484 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L
485 //SMU_GPIOPAD_INT_POLARITY
486 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
487 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
488 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL
489 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L
490 //ROM_CC_BIF_PINSTRAP
491 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x0
492 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT 0x1
493 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x4
494 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x7
495 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x8
496 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x9
497 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT 0xa
498 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L
499 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK 0x0000000EL
500 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L
501 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L
502 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L
503 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L
504 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK 0x00000400L
506 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0
507 #define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3
508 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x5
509 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT 0x8
510 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L
511 #define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L
512 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000E0L
513 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK 0x00000100L
515 #define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
516 #define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L
517 //SMUIO_PCC_GPIO_SELECT
518 #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
519 #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL
520 //SMUIO_GPIO_INT0_SELECT
521 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0
522 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL
523 //SMUIO_GPIO_INT1_SELECT
524 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0
525 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL
526 //SMUIO_GPIO_INT2_SELECT
527 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0
528 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL
529 //SMUIO_GPIO_INT3_SELECT
530 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0
531 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL
532 //SMU_GPIOPAD_MP_INT0_STAT
533 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0
534 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL
535 //SMU_GPIOPAD_MP_INT1_STAT
536 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0
537 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL
538 //SMU_GPIOPAD_MP_INT2_STAT
539 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0
540 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL
541 //SMU_GPIOPAD_MP_INT3_STAT
542 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0
543 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL
545 #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0
546 #define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L
548 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0
549 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL
551 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0
552 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL
554 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0
555 #define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f
556 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL
557 #define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L
559 #define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0
560 #define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL
562 #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0
563 #define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL
565 #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0
566 #define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL
568 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0
569 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL
571 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0
572 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL
574 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0
575 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL
578 // addressBlock: smuio_smuio_pwr_SmuSmuioDec
579 //IP_DISCOVERY_VERSION
580 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0
581 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL
583 #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0
584 #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L
586 #define GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT 0x0
587 #define GFX_GAP_PWROK__gfx_gap_pwrok_MASK 0x00000001L
588 //PWROK_REFCLK_GAP_CYCLES
589 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0
590 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8
591 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL
592 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L
593 //GOLDEN_TSC_INCREMENT_UPPER
594 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0
595 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL
596 //GOLDEN_TSC_INCREMENT_LOWER
597 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0
598 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL
599 //GOLDEN_TSC_COUNT_UPPER
600 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0
601 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL
602 //GOLDEN_TSC_COUNT_LOWER
603 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0
604 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL
605 //SOC_GOLDEN_TSC_SHADOW_UPPER
606 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper__SHIFT 0x0
607 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper_MASK 0x00FFFFFFL
608 //SOC_GOLDEN_TSC_SHADOW_LOWER
609 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower__SHIFT 0x0
610 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower_MASK 0xFFFFFFFFL
611 //GFX_GOLDEN_TSC_SHADOW_UPPER
612 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT 0x0
613 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK 0x00FFFFFFL
614 //GFX_GOLDEN_TSC_SHADOW_LOWER
615 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT 0x0
616 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK 0xFFFFFFFFL
618 #define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
619 #define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f
620 #define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL
621 #define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L
623 #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0
624 #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL
626 #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0
627 #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL
629 #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0
630 #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL
632 #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0
633 #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL
635 #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0
636 #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL
638 #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0
639 #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL
641 #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0
642 #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL
644 #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0
645 #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL
646 //PWR_DISP_TIMER_CONTROL
647 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
648 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
649 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
650 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
651 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
652 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
653 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
654 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
655 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
656 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
657 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
658 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
659 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
660 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
661 //PWR_DISP_TIMER2_CONTROL
662 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
663 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
664 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
665 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
666 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
667 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
668 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
669 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
670 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
671 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
672 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
673 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
674 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
675 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
676 //PWR_DISP_TIMER_GLOBAL_CONTROL
677 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
678 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa
679 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL
680 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L
682 #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0
683 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5
684 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6
685 #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL
686 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L
687 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L