2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef _nbio_7_4_0_SMN_HEADER
23 #define _nbio_7_4_0_SMN_HEADER
26 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
27 #define smnCPM_CONTROL 0x11180460
28 #define smnPCIE_CNTL2 0x11180070
29 #define smnPCIE_CI_CNTL 0x11180080
31 #define smnPCIE_PERF_COUNT_CNTL 0x11180200
32 #define smnPCIE_PERF_CNTL_TXCLK1 0x11180204
33 #define smnPCIE_PERF_COUNT0_TXCLK1 0x11180208
34 #define smnPCIE_PERF_COUNT1_TXCLK1 0x1118020c
35 #define smnPCIE_PERF_CNTL_TXCLK2 0x11180210
36 #define smnPCIE_PERF_COUNT0_TXCLK2 0x11180214
37 #define smnPCIE_PERF_COUNT1_TXCLK2 0x11180218
38 #define smnPCIE_PERF_CNTL_TXCLK3 0x1118021c
39 #define smnPCIE_PERF_COUNT0_TXCLK3 0x11180220
40 #define smnPCIE_PERF_COUNT1_TXCLK3 0x11180224
41 #define smnPCIE_PERF_CNTL_TXCLK4 0x11180228
42 #define smnPCIE_PERF_COUNT0_TXCLK4 0x1118022c
43 #define smnPCIE_PERF_COUNT1_TXCLK4 0x11180230
44 #define smnPCIE_PERF_CNTL_SCLK1 0x11180234
45 #define smnPCIE_PERF_COUNT0_SCLK1 0x11180238
46 #define smnPCIE_PERF_COUNT1_SCLK1 0x1118023c
47 #define smnPCIE_PERF_CNTL_SCLK2 0x11180240
48 #define smnPCIE_PERF_COUNT0_SCLK2 0x11180244
49 #define smnPCIE_PERF_COUNT1_SCLK2 0x11180248
50 #define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x1118024c
51 #define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x11180250
53 #define smnPCIE_RX_NUM_NAK 0x11180038
54 #define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c
56 #endif // _nbio_7_4_0_SMN_HEADER