drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__
  27 #define __DAL_TIMING_GENERATOR_TYPES_H__
  28
  29 #include "hw_shared.h"
  30
  31 struct dc_bios;
  32
  33 /* Contains CRTC vertical/horizontal pixel counters */
  34 struct crtc_position {
  35         int32_t vertical_count;
  36         int32_t horizontal_count;
  37         int32_t nominal_vcount;
  38 };
  39
  40 struct dcp_gsl_params {
  41         int gsl_group;
  42         int gsl_master;
  43 };
  44
  45 struct gsl_params {
  46         int gsl0_en;
  47         int gsl1_en;
  48         int gsl2_en;
  49         int gsl_master_en;
  50         int gsl_master_mode;
  51         int master_update_lock_gsl_en;
  52         int gsl_window_start_x;
  53         int gsl_window_end_x;
  54         int gsl_window_start_y;
  55         int gsl_window_end_y;
  56 };
  57
  58 /* define the structure of Dynamic Refresh Mode */
  59 struct drr_params {
  60         uint32_t vertical_total_min;
  61         uint32_t vertical_total_max;
  62         bool immediate_flip;
  63 };
  64
  65 #define LEFT_EYE_3D_PRIMARY_SURFACE 1
  66 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0
  67
  68 enum crtc_state {
  69         CRTC_STATE_VBLANK = 0,
  70         CRTC_STATE_VACTIVE
  71 };
  72
  73 struct vupdate_keepout_params {
  74         int start_offset;
  75         int end_offset;
  76         int enable;
  77 };
  78
  79 struct crtc_stereo_flags {
  80         uint8_t PROGRAM_STEREO         : 1;
  81         uint8_t PROGRAM_POLARITY       : 1;
  82         uint8_t RIGHT_EYE_POLARITY     : 1;
  83         uint8_t FRAME_PACKED           : 1;
  84         uint8_t DISABLE_STEREO_DP_SYNC : 1;
  85 };
  86
  87 enum crc_selection {
  88         /* Order must match values expected by hardware */
  89         UNION_WINDOW_A_B = 0,
  90         UNION_WINDOW_A_NOT_B,
  91         UNION_WINDOW_NOT_A_B,
  92         UNION_WINDOW_NOT_A_NOT_B,
  93         INTERSECT_WINDOW_A_B,
  94         INTERSECT_WINDOW_A_NOT_B,
  95         INTERSECT_WINDOW_NOT_A_B,
  96         INTERSECT_WINDOW_NOT_A_NOT_B,
  97 };
  98
  99 struct crc_params {
 100         /* Regions used to calculate CRC*/
 101         uint16_t windowa_x_start;
 102         uint16_t windowa_x_end;
 103         uint16_t windowa_y_start;
 104         uint16_t windowa_y_end;
 105
 106         uint16_t windowb_x_start;
 107         uint16_t windowb_x_end;
 108         uint16_t windowb_y_start;
 109         uint16_t windowb_y_end;
 110
 111         enum crc_selection selection;
 112
 113         bool continuous_mode;
 114         bool enable;
 115 };
 116
 117 struct timing_generator {
 118         const struct timing_generator_funcs *funcs;
 119         struct dc_bios *bp;
 120         struct dc_context *ctx;
 121         int inst;
 122 };
 123
 124 struct dc_crtc_timing;
 125
 126 struct drr_params;
 127
 128
 129 struct timing_generator_funcs {
 130         bool (*validate_timing)(struct timing_generator *tg,
 131                                                         const struct dc_crtc_timing *timing);
 132         void (*program_timing)(struct timing_generator *tg,
 133                                                         const struct dc_crtc_timing *timing,
 134                                                         int vready_offset,
 135                                                         int vstartup_start,
 136                                                         int vupdate_offset,
 137                                                         int vupdate_width,
 138                                                         const enum signal_type signal,
 139                                                         bool use_vbios
 140         );
 141         void (*setup_vertical_interrupt0)(
 142                         struct timing_generator *optc,
 143                         uint32_t start_line,
 144                         uint32_t end_line);
 145         void (*setup_vertical_interrupt1)(
 146                         struct timing_generator *optc,
 147                         uint32_t start_line);
 148         void (*setup_vertical_interrupt2)(
 149                         struct timing_generator *optc,
 150                         uint32_t start_line);
 151
 152         bool (*enable_crtc)(struct timing_generator *tg);
 153         bool (*disable_crtc)(struct timing_generator *tg);
 154         bool (*is_counter_moving)(struct timing_generator *tg);
 155         void (*get_position)(struct timing_generator *tg,
 156                                 struct crtc_position *position);
 157
 158         uint32_t (*get_frame_count)(struct timing_generator *tg);
 159         void (*get_scanoutpos)(
 160                 struct timing_generator *tg,
 161                 uint32_t *v_blank_start,
 162                 uint32_t *v_blank_end,
 163                 uint32_t *h_position,
 164                 uint32_t *v_position);
 165         bool (*get_otg_active_size)(struct timing_generator *optc,
 166                         uint32_t *otg_active_width,
 167                         uint32_t *otg_active_height);
 168         bool (*is_matching_timing)(struct timing_generator *tg,
 169                         const struct dc_crtc_timing *otg_timing);
 170         void (*set_early_control)(struct timing_generator *tg,
 171                                                            uint32_t early_cntl);
 172         void (*wait_for_state)(struct timing_generator *tg,
 173                                                         enum crtc_state state);
 174         void (*set_blank)(struct timing_generator *tg,
 175                                         bool enable_blanking);
 176         bool (*is_blanked)(struct timing_generator *tg);
 177         void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
 178         void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
 179         void (*set_colors)(struct timing_generator *tg,
 180                                                 const struct tg_color *blank_color,
 181                                                 const struct tg_color *overscan_color);
 182
 183         void (*disable_vga)(struct timing_generator *tg);
 184         bool (*did_triggered_reset_occur)(struct timing_generator *tg);
 185         void (*setup_global_swap_lock)(struct timing_generator *tg,
 186                                                         const struct dcp_gsl_params *gsl_params);
 187         void (*setup_global_lock)(struct timing_generator *tg);
 188         void (*unlock)(struct timing_generator *tg);
 189         void (*lock)(struct timing_generator *tg);
 190         void (*lock_global)(struct timing_generator *tg);
 191         void (*lock_doublebuffer_disable)(struct timing_generator *tg);
 192         void (*lock_doublebuffer_enable)(struct timing_generator *tg);
 193 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 194         void(*triplebuffer_unlock)(struct timing_generator *tg);
 195         void(*triplebuffer_lock)(struct timing_generator *tg);
 196 #endif
 197         void (*enable_reset_trigger)(struct timing_generator *tg,
 198                                      int source_tg_inst);
 199         void (*enable_crtc_reset)(struct timing_generator *tg,
 200                                   int source_tg_inst,
 201                                   struct crtc_trigger_info *crtc_tp);
 202         void (*disable_reset_trigger)(struct timing_generator *tg);
 203         void (*tear_down_global_swap_lock)(struct timing_generator *tg);
 204         void (*enable_advanced_request)(struct timing_generator *tg,
 205                                         bool enable, const struct dc_crtc_timing *timing);
 206         void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
 207         void (*set_static_screen_control)(struct timing_generator *tg,
 208                                                         uint32_t value);
 209         void (*set_test_pattern)(
 210                 struct timing_generator *tg,
 211                 enum controller_dp_test_pattern test_pattern,
 212                 enum dc_color_depth color_depth);
 213
 214         bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
 215
 216         void (*program_global_sync)(struct timing_generator *tg,
 217                         int vready_offset,
 218                         int vstartup_start,
 219                         int vupdate_offset,
 220                         int vupdate_width);
 221         void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
 222         void (*program_stereo)(struct timing_generator *tg,
 223                 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
 224         bool (*is_stereo_left_eye)(struct timing_generator *tg);
 225
 226         void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
 227
 228         void (*tg_init)(struct timing_generator *tg);
 229         bool (*is_tg_enabled)(struct timing_generator *tg);
 230         bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
 231         void (*clear_optc_underflow)(struct timing_generator *tg);
 232
 233 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 234         void (*set_dwb_source)(struct timing_generator *optc,
 235                 uint32_t dwb_pipe_inst);
 236
 237         void (*get_optc_source)(struct timing_generator *optc,
 238                         uint32_t *num_of_input_segments,
 239                         uint32_t *seg0_src_sel,
 240                         uint32_t *seg1_src_sel);
 241 #endif
 242
 243         /**
 244          * Configure CRCs for the given timing generator. Return false if TG is
 245          * not on.
 246          */
 247         bool (*configure_crc)(struct timing_generator *tg,
 248                                const struct crc_params *params);
 249
 250         /**
 251          * Get CRCs for the given timing generator. Return false if CRCs are
 252          * not enabled (via configure_crc).
 253          */
 254         bool (*get_crc)(struct timing_generator *tg,
 255                         uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
 256
 257         void (*program_manual_trigger)(struct timing_generator *optc);
 258         void (*setup_manual_trigger)(struct timing_generator *optc);
 259
 260         void (*set_vtg_params)(struct timing_generator *optc,
 261                         const struct dc_crtc_timing *dc_crtc_timing);
 262
 263 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 264 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 265         void (*set_dsc_config)(struct timing_generator *optc,
 266                                enum optc_dsc_mode dsc_mode,
 267                                uint32_t dsc_bytes_per_pixel,
 268                                uint32_t dsc_slice_width);
 269 #endif
 270         void (*set_odm_bypass)(struct timing_generator *tg, const struct dc_crtc_timing *dc_crtc_timing);
 271         void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id,
 272                 int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
 273         void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
 274         void (*set_gsl_source_select)(struct timing_generator *optc,
 275                         int group_idx,
 276                         uint32_t gsl_ready_signal);
 277 #endif
 278 };
 279
 280 #endif